Unified Coverage Report :: Module :: sysrst_ctrl_reg_top

Module : sysrst_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.60	100.00	94.41			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.52	99.38	98.40	100.00		99.80	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_auto_block_debounce_ctl_auto_block_enable	100.00	100.00	100.00			100.00
u_auto_block_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_auto_block_debounce_ctl_debounce_timer	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_auto_block_out_ctl_key0_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key0_out_value	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key1_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key1_out_value	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key2_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key2_out_value	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_com_det_ctl_0	100.00	100.00	100.00			100.00
u_com_det_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_1	100.00	100.00	100.00			100.00
u_com_det_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_2	100.00	100.00	100.00			100.00
u_com_det_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_3	100.00	100.00	100.00			100.00
u_com_det_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_0_bat_disable_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_0_ec_rst_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_interrupt_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_rst_req_0	100.00	100.00	100.00			100.00
u_com_out_ctl_1_bat_disable_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_1_ec_rst_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_interrupt_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_rst_req_1	100.00	100.00	100.00			100.00
u_com_out_ctl_2_bat_disable_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_2_ec_rst_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_interrupt_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_rst_req_2	100.00	100.00	100.00			100.00
u_com_out_ctl_3_bat_disable_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_3_ec_rst_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_interrupt_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_rst_req_3	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_0	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_1	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_2	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_3	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_0_ac_present_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_0_key0_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_key1_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_key2_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_pwrb_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_ac_present_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_1_key0_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_key1_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_key2_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_pwrb_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_ac_present_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_2_key0_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_key1_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_key2_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_pwrb_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_ac_present_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_3_key0_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_key1_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_key2_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_pwrb_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_ac_present_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_0_key0_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_key1_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_key2_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_pwrb_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_ac_present_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_1_key0_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_key1_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_key2_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_pwrb_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_ac_present_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_2_key0_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_key1_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_key2_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_pwrb_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_ac_present_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_3_key0_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_key1_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_key2_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_pwrb_in_sel_3	100.00	100.00	100.00			100.00
u_combo_intr_status_combo0_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo1_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo2_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo3_h2l	100.00	100.00	100.00			100.00
u_ec_rst_ctl	100.00	100.00	100.00			100.00
u_ec_rst_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	92.59	77.78	100.00			100.00
u_intr_test	100.00	100.00
u_key_intr_ctl_ac_present_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_ac_present_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_key_intr_ctl_ec_rst_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_ec_rst_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_flash_wp_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_flash_wp_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key0_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key0_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key1_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key1_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key2_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key2_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_pwrb_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_pwrb_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_debounce_ctl	100.00	100.00	100.00			100.00
u_key_intr_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_key_intr_status_ac_present_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_ac_present_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_ec_rst_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_ec_rst_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_flash_wp_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_flash_wp_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key0_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key0_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key1_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key1_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key2_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key2_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_pwrb_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_pwrb_l2h	100.00	100.00	100.00			100.00
u_key_invert_ctl_ac_present	100.00	100.00	100.00			100.00
u_key_invert_ctl_bat_disable	100.00	100.00	100.00			100.00
u_key_invert_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_key_invert_ctl_key0_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key0_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_key1_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key1_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_key2_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key2_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_lid_open	100.00	100.00	100.00			100.00
u_key_invert_ctl_pwrb_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_pwrb_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_z3_wakeup	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_bat_disable_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_bat_disable_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_allowed_ctl_ec_rst_l_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_ec_rst_l_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_flash_wp_l_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_flash_wp_l_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key0_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key0_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key1_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key1_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key2_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key2_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_pwrb_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_pwrb_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_z3_wakeup_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_z3_wakeup_1	100.00	100.00	100.00			100.00
u_pin_in_value_ac_present	92.59	77.78	100.00			100.00
u_pin_in_value_ec_rst_l	92.59	77.78	100.00			100.00
u_pin_in_value_flash_wp_l	92.59	77.78	100.00			100.00
u_pin_in_value_key0_in	92.59	77.78	100.00			100.00
u_pin_in_value_key1_in	92.59	77.78	100.00			100.00
u_pin_in_value_key2_in	92.59	77.78	100.00			100.00
u_pin_in_value_lid_open	92.59	77.78	100.00			100.00
u_pin_in_value_pwrb_in	92.59	77.78	100.00			100.00
u_pin_out_ctl_bat_disable	100.00	100.00	100.00			100.00
u_pin_out_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_out_ctl_ec_rst_l	100.00	100.00	100.00			100.00
u_pin_out_ctl_flash_wp_l	100.00	100.00	100.00			100.00
u_pin_out_ctl_key0_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_key1_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_key2_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_pwrb_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_z3_wakeup	100.00	100.00	100.00			100.00
u_pin_out_value_bat_disable	100.00	100.00	100.00			100.00
u_pin_out_value_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_out_value_ec_rst_l	100.00	100.00	100.00			100.00
u_pin_out_value_flash_wp_l	100.00	100.00	100.00			100.00
u_pin_out_value_key0_out	100.00	100.00	100.00			100.00
u_pin_out_value_key1_out	100.00	100.00	100.00			100.00
u_pin_out_value_key2_out	100.00	100.00	100.00			100.00
u_pin_out_value_pwrb_out	100.00	100.00	100.00			100.00
u_pin_out_value_z3_wakeup	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.98	97.14	98.80			100.00	100.00
u_regwen	100.00	100.00	100.00			100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_ulp_ac_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_ac_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_ctl	100.00	100.00	100.00			100.00
u_ulp_ctl_cdc	99.22	100.00	96.88			100.00	100.00
u_ulp_lid_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_lid_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_pwrb_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_pwrb_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_status	100.00	100.00	100.00			100.00
u_wkup_status	100.00	100.00	100.00			100.00
u_wkup_status_cdc	94.70	96.99	88.57			93.22	100.00

Line Coverage for Module : sysrst_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		512	512	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
ALWAYS	299	2	2	100.00
CONT_ASSIGN	327	1	1	100.00
ALWAYS	338	2	2	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	377	2	2	100.00
CONT_ASSIGN	405	1	1	100.00
ALWAYS	416	2	2	100.00
CONT_ASSIGN	444	1	1	100.00
ALWAYS	454	2	2	100.00
CONT_ASSIGN	482	1	1	100.00
ALWAYS	495	4	4	100.00
CONT_ASSIGN	525	1	1	100.00
ALWAYS	547	13	13	100.00
CONT_ASSIGN	586	1	1	100.00
ALWAYS	612	17	17	100.00
CONT_ASSIGN	655	1	1	100.00
ALWAYS	672	9	9	100.00
CONT_ASSIGN	707	1	1	100.00
ALWAYS	724	9	9	100.00
CONT_ASSIGN	759	1	1	100.00
ALWAYS	783	15	15	100.00
CONT_ASSIGN	824	1	1	100.00
ALWAYS	835	2	2	100.00
CONT_ASSIGN	863	1	1	100.00
ALWAYS	875	3	3	100.00
CONT_ASSIGN	904	1	1	100.00
ALWAYS	920	7	7	100.00
CONT_ASSIGN	953	1	1	100.00
ALWAYS	968	6	6	100.00
CONT_ASSIGN	1000	1	1	100.00
ALWAYS	1015	6	6	100.00
CONT_ASSIGN	1047	1	1	100.00
ALWAYS	1062	6	6	100.00
CONT_ASSIGN	1094	1	1	100.00
ALWAYS	1109	6	6	100.00
CONT_ASSIGN	1141	1	1	100.00
ALWAYS	1152	2	2	100.00
CONT_ASSIGN	1180	1	1	100.00
ALWAYS	1191	2	2	100.00
CONT_ASSIGN	1219	1	1	100.00
ALWAYS	1230	2	2	100.00
CONT_ASSIGN	1258	1	1	100.00
ALWAYS	1269	2	2	100.00
CONT_ASSIGN	1297	1	1	100.00
ALWAYS	1312	6	6	100.00
CONT_ASSIGN	1344	1	1	100.00
ALWAYS	1359	6	6	100.00
CONT_ASSIGN	1391	1	1	100.00
ALWAYS	1406	6	6	100.00
CONT_ASSIGN	1438	1	1	100.00
ALWAYS	1453	6	6	100.00
CONT_ASSIGN	1485	1	1	100.00
ALWAYS	1496	2	2	100.00
CONT_ASSIGN	1524	1	1	100.00
ALWAYS	1535	2	2	100.00
CONT_ASSIGN	1563	1	1	100.00
ALWAYS	1574	2	2	100.00
CONT_ASSIGN	1602	1	1	100.00
ALWAYS	1613	2	2	100.00
CONT_ASSIGN	1641	1	1	100.00
ALWAYS	1655	5	5	100.00
CONT_ASSIGN	1686	1	1	100.00
ALWAYS	1700	5	5	100.00
CONT_ASSIGN	1731	1	1	100.00
ALWAYS	1745	5	5	100.00
CONT_ASSIGN	1776	1	1	100.00
ALWAYS	1790	5	5	100.00
CONT_ASSIGN	1821	1	1	100.00
CONT_ASSIGN	1884	1	1	100.00
CONT_ASSIGN	1898	1	1	100.00
CONT_ASSIGN	1904	1	1	100.00
CONT_ASSIGN	1918	1	1	100.00
CONT_ASSIGN	1952	1	1	100.00
CONT_ASSIGN	1983	1	1	100.00
CONT_ASSIGN	2015	1	1	100.00
CONT_ASSIGN	2047	1	1	100.00
CONT_ASSIGN	2134	1	1	100.00
CONT_ASSIGN	2165	1	1	100.00
CONT_ASSIGN	2494	1	1	100.00
CONT_ASSIGN	3585	1	1	100.00
CONT_ASSIGN	3968	1	1	100.00
CONT_ASSIGN	4000	1	1	100.00
CONT_ASSIGN	4060	1	1	100.00
CONT_ASSIGN	4229	1	1	100.00
CONT_ASSIGN	4370	1	1	100.00
CONT_ASSIGN	4511	1	1	100.00
CONT_ASSIGN	4652	1	1	100.00
CONT_ASSIGN	4793	1	1	100.00
CONT_ASSIGN	4825	1	1	100.00
CONT_ASSIGN	4857	1	1	100.00
CONT_ASSIGN	4889	1	1	100.00
CONT_ASSIGN	4921	1	1	100.00
CONT_ASSIGN	5062	1	1	100.00
CONT_ASSIGN	5203	1	1	100.00
CONT_ASSIGN	5344	1	1	100.00
CONT_ASSIGN	5485	1	1	100.00
CONT_ASSIGN	5517	1	1	100.00
CONT_ASSIGN	5549	1	1	100.00
CONT_ASSIGN	5581	1	1	100.00
CONT_ASSIGN	5613	1	1	100.00
CONT_ASSIGN	5727	1	1	100.00
CONT_ASSIGN	5841	1	1	100.00
CONT_ASSIGN	5955	1	1	100.00
ALWAYS	6558	44	44	100.00
CONT_ASSIGN	6604	1	1	100.00
ALWAYS	6608	1	1	100.00
CONT_ASSIGN	6655	1	1	100.00
CONT_ASSIGN	6657	1	1	100.00
CONT_ASSIGN	6658	1	1	100.00
CONT_ASSIGN	6660	1	1	100.00
CONT_ASSIGN	6661	1	1	100.00
CONT_ASSIGN	6663	1	1	100.00
CONT_ASSIGN	6664	1	1	100.00
CONT_ASSIGN	6666	1	1	100.00
CONT_ASSIGN	6667	1	1	100.00
CONT_ASSIGN	6669	1	1	100.00
CONT_ASSIGN	6671	1	1	100.00
CONT_ASSIGN	6673	1	1	100.00
CONT_ASSIGN	6675	1	1	100.00
CONT_ASSIGN	6677	1	1	100.00
CONT_ASSIGN	6679	1	1	100.00
CONT_ASSIGN	6680	1	1	100.00
CONT_ASSIGN	6682	1	1	100.00
CONT_ASSIGN	6695	1	1	100.00
CONT_ASSIGN	6712	1	1	100.00
CONT_ASSIGN	6721	1	1	100.00
CONT_ASSIGN	6730	1	1	100.00
CONT_ASSIGN	6745	1	1	100.00
CONT_ASSIGN	6747	1	1	100.00
CONT_ASSIGN	6750	1	1	100.00
CONT_ASSIGN	6757	1	1	100.00
CONT_ASSIGN	6763	1	1	100.00
CONT_ASSIGN	6769	1	1	100.00
CONT_ASSIGN	6775	1	1	100.00
CONT_ASSIGN	6781	1	1	100.00
CONT_ASSIGN	6783	1	1	100.00
CONT_ASSIGN	6785	1	1	100.00
CONT_ASSIGN	6787	1	1	100.00
CONT_ASSIGN	6789	1	1	100.00
CONT_ASSIGN	6795	1	1	100.00
CONT_ASSIGN	6801	1	1	100.00
CONT_ASSIGN	6807	1	1	100.00
CONT_ASSIGN	6813	1	1	100.00
CONT_ASSIGN	6815	1	1	100.00
CONT_ASSIGN	6817	1	1	100.00
CONT_ASSIGN	6819	1	1	100.00
CONT_ASSIGN	6821	1	1	100.00
CONT_ASSIGN	6826	1	1	100.00
CONT_ASSIGN	6831	1	1	100.00
CONT_ASSIGN	6836	1	1	100.00
CONT_ASSIGN	6841	1	1	100.00
CONT_ASSIGN	6843	1	1	100.00
CONT_ASSIGN	6845	1	1	100.00
CONT_ASSIGN	6847	1	1	100.00
CONT_ASSIGN	6849	1	1	100.00
CONT_ASSIGN	6850	1	1	100.00
CONT_ASSIGN	6852	1	1	100.00
CONT_ASSIGN	6854	1	1	100.00
CONT_ASSIGN	6856	1	1	100.00
CONT_ASSIGN	6858	1	1	100.00
CONT_ASSIGN	6860	1	1	100.00
CONT_ASSIGN	6862	1	1	100.00
CONT_ASSIGN	6864	1	1	100.00
CONT_ASSIGN	6866	1	1	100.00
CONT_ASSIGN	6868	1	1	100.00
CONT_ASSIGN	6870	1	1	100.00
CONT_ASSIGN	6872	1	1	100.00
CONT_ASSIGN	6874	1	1	100.00
CONT_ASSIGN	6876	1	1	100.00
CONT_ASSIGN	6878	1	1	100.00
ALWAYS	6882	44	44	100.00
ALWAYS	6930	68	68	100.00
CONT_ASSIGN	7105	1	1	100.00
ALWAYS	7107	36	36	100.00
CONT_ASSIGN	7224	1	1	100.00
CONT_ASSIGN	7225	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : sysrst_ctrl_reg_top

	Total	Covered	Percent
Conditions	537	507	94.41
Logical	537	507	94.41
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
60-6608	90.16
6608-7105	100.00

---

Branch Coverage for Module : sysrst_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		84	84	100.00
TERNARY	6604	2	2	100.00
IF	70	3	3	100.00
CASE	6931	44	44	100.00
CASE	7108	35	35	100.00

6604         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

70             if (!rst_ni) begin
               -1-  
71               err_q <= '0;
                 ==>
72             end else if (intg_err || reg_we_err) begin
                        -2-  
73               err_q <= 1'b1;
                 ==>
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T265,T260,T191
0	0	Covered	T1,T4,T5

6931           unique case (1'b1)
                      -1-  
6932             addr_hit[0]: begin
6933               reg_rdata_next[0] = intr_state_qs;
                   ==>
6934             end
6935       
6936             addr_hit[1]: begin
6937               reg_rdata_next[0] = intr_enable_qs;
                   ==>
6938             end
6939       
6940             addr_hit[2]: begin
6941               reg_rdata_next[0] = '0;
                   ==>
6942             end
6943       
6944             addr_hit[3]: begin
6945               reg_rdata_next[0] = '0;
                   ==>
6946             end
6947       
6948             addr_hit[4]: begin
6949               reg_rdata_next[0] = regwen_qs;
                   ==>
6950             end
6951       
6952             addr_hit[5]: begin
6953               reg_rdata_next = DW'(ec_rst_ctl_qs);
                   ==>
6954             end
6955             addr_hit[6]: begin
6956               reg_rdata_next = DW'(ulp_ac_debounce_ctl_qs);
                   ==>
6957             end
6958             addr_hit[7]: begin
6959               reg_rdata_next = DW'(ulp_lid_debounce_ctl_qs);
                   ==>
6960             end
6961             addr_hit[8]: begin
6962               reg_rdata_next = DW'(ulp_pwrb_debounce_ctl_qs);
                   ==>
6963             end
6964             addr_hit[9]: begin
6965               reg_rdata_next = DW'(ulp_ctl_qs);
                   ==>
6966             end
6967             addr_hit[10]: begin
6968               reg_rdata_next[0] = ulp_status_qs;
                   ==>
6969             end
6970       
6971             addr_hit[11]: begin
6972               reg_rdata_next = DW'(wkup_status_qs);
                   ==>
6973             end
6974             addr_hit[12]: begin
6975               reg_rdata_next = DW'(key_invert_ctl_qs);
                   ==>
6976             end
6977             addr_hit[13]: begin
6978               reg_rdata_next = DW'(pin_allowed_ctl_qs);
                   ==>
6979             end
6980             addr_hit[14]: begin
6981               reg_rdata_next = DW'(pin_out_ctl_qs);
                   ==>
6982             end
6983             addr_hit[15]: begin
6984               reg_rdata_next = DW'(pin_out_value_qs);
                   ==>
6985             end
6986             addr_hit[16]: begin
6987               reg_rdata_next[0] = pin_in_value_pwrb_in_qs;
                   ==>
6988               reg_rdata_next[1] = pin_in_value_key0_in_qs;
6989               reg_rdata_next[2] = pin_in_value_key1_in_qs;
6990               reg_rdata_next[3] = pin_in_value_key2_in_qs;
6991               reg_rdata_next[4] = pin_in_value_lid_open_qs;
6992               reg_rdata_next[5] = pin_in_value_ac_present_qs;
6993               reg_rdata_next[6] = pin_in_value_ec_rst_l_qs;
6994               reg_rdata_next[7] = pin_in_value_flash_wp_l_qs;
6995             end
6996       
6997             addr_hit[17]: begin
6998               reg_rdata_next = DW'(key_intr_ctl_qs);
                   ==>
6999             end
7000             addr_hit[18]: begin
7001               reg_rdata_next = DW'(key_intr_debounce_ctl_qs);
                   ==>
7002             end
7003             addr_hit[19]: begin
7004               reg_rdata_next = DW'(auto_block_debounce_ctl_qs);
                   ==>
7005             end
7006             addr_hit[20]: begin
7007               reg_rdata_next = DW'(auto_block_out_ctl_qs);
                   ==>
7008             end
7009             addr_hit[21]: begin
7010               reg_rdata_next = DW'(com_pre_sel_ctl_0_qs);
                   ==>
7011             end
7012             addr_hit[22]: begin
7013               reg_rdata_next = DW'(com_pre_sel_ctl_1_qs);
                   ==>
7014             end
7015             addr_hit[23]: begin
7016               reg_rdata_next = DW'(com_pre_sel_ctl_2_qs);
                   ==>
7017             end
7018             addr_hit[24]: begin
7019               reg_rdata_next = DW'(com_pre_sel_ctl_3_qs);
                   ==>
7020             end
7021             addr_hit[25]: begin
7022               reg_rdata_next = DW'(com_pre_det_ctl_0_qs);
                   ==>
7023             end
7024             addr_hit[26]: begin
7025               reg_rdata_next = DW'(com_pre_det_ctl_1_qs);
                   ==>
7026             end
7027             addr_hit[27]: begin
7028               reg_rdata_next = DW'(com_pre_det_ctl_2_qs);
                   ==>
7029             end
7030             addr_hit[28]: begin
7031               reg_rdata_next = DW'(com_pre_det_ctl_3_qs);
                   ==>
7032             end
7033             addr_hit[29]: begin
7034               reg_rdata_next = DW'(com_sel_ctl_0_qs);
                   ==>
7035             end
7036             addr_hit[30]: begin
7037               reg_rdata_next = DW'(com_sel_ctl_1_qs);
                   ==>
7038             end
7039             addr_hit[31]: begin
7040               reg_rdata_next = DW'(com_sel_ctl_2_qs);
                   ==>
7041             end
7042             addr_hit[32]: begin
7043               reg_rdata_next = DW'(com_sel_ctl_3_qs);
                   ==>
7044             end
7045             addr_hit[33]: begin
7046               reg_rdata_next = DW'(com_det_ctl_0_qs);
                   ==>
7047             end
7048             addr_hit[34]: begin
7049               reg_rdata_next = DW'(com_det_ctl_1_qs);
                   ==>
7050             end
7051             addr_hit[35]: begin
7052               reg_rdata_next = DW'(com_det_ctl_2_qs);
                   ==>
7053             end
7054             addr_hit[36]: begin
7055               reg_rdata_next = DW'(com_det_ctl_3_qs);
                   ==>
7056             end
7057             addr_hit[37]: begin
7058               reg_rdata_next = DW'(com_out_ctl_0_qs);
                   ==>
7059             end
7060             addr_hit[38]: begin
7061               reg_rdata_next = DW'(com_out_ctl_1_qs);
                   ==>
7062             end
7063             addr_hit[39]: begin
7064               reg_rdata_next = DW'(com_out_ctl_2_qs);
                   ==>
7065             end
7066             addr_hit[40]: begin
7067               reg_rdata_next = DW'(com_out_ctl_3_qs);
                   ==>
7068             end
7069             addr_hit[41]: begin
7070               reg_rdata_next[0] = combo_intr_status_combo0_h2l_qs;
                   ==>
7071               reg_rdata_next[1] = combo_intr_status_combo1_h2l_qs;
7072               reg_rdata_next[2] = combo_intr_status_combo2_h2l_qs;
7073               reg_rdata_next[3] = combo_intr_status_combo3_h2l_qs;
7074             end
7075       
7076             addr_hit[42]: begin
7077               reg_rdata_next[0] = key_intr_status_pwrb_h2l_qs;
                   ==>
7078               reg_rdata_next[1] = key_intr_status_key0_in_h2l_qs;
7079               reg_rdata_next[2] = key_intr_status_key1_in_h2l_qs;
7080               reg_rdata_next[3] = key_intr_status_key2_in_h2l_qs;
7081               reg_rdata_next[4] = key_intr_status_ac_present_h2l_qs;
7082               reg_rdata_next[5] = key_intr_status_ec_rst_l_h2l_qs;
7083               reg_rdata_next[6] = key_intr_status_flash_wp_l_h2l_qs;
7084               reg_rdata_next[7] = key_intr_status_pwrb_l2h_qs;
7085               reg_rdata_next[8] = key_intr_status_key0_in_l2h_qs;
7086               reg_rdata_next[9] = key_intr_status_key1_in_l2h_qs;
7087               reg_rdata_next[10] = key_intr_status_key2_in_l2h_qs;
7088               reg_rdata_next[11] = key_intr_status_ac_present_l2h_qs;
7089               reg_rdata_next[12] = key_intr_status_ec_rst_l_l2h_qs;
7090               reg_rdata_next[13] = key_intr_status_flash_wp_l_l2h_qs;
7091             end
7092       
7093             default: begin
7094               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T4,T5
addr_hit[1]	Covered	T1,T4,T5
addr_hit[2]	Covered	T4,T5,T2
addr_hit[3]	Covered	T4,T5,T2
addr_hit[4]	Covered	T1,T4,T5
addr_hit[5]	Covered	T1,T4,T5
addr_hit[6]	Covered	T4,T5,T2
addr_hit[7]	Covered	T4,T5,T2
addr_hit[8]	Covered	T1,T4,T5
addr_hit[9]	Covered	T1,T4,T5
addr_hit[10]	Covered	T4,T5,T2
addr_hit[11]	Covered	T4,T5,T2
addr_hit[12]	Covered	T4,T5,T2
addr_hit[13]	Covered	T1,T4,T5
addr_hit[14]	Covered	T1,T4,T5
addr_hit[15]	Covered	T4,T5,T2
addr_hit[16]	Covered	T1,T4,T5
addr_hit[17]	Covered	T4,T5,T2
addr_hit[18]	Covered	T1,T4,T5
addr_hit[19]	Covered	T4,T5,T2
addr_hit[20]	Covered	T4,T5,T2
addr_hit[21]	Covered	T1,T4,T5
addr_hit[22]	Covered	T4,T5,T2
addr_hit[23]	Covered	T4,T5,T2
addr_hit[24]	Covered	T4,T5,T2
addr_hit[25]	Covered	T1,T4,T5
addr_hit[26]	Covered	T1,T4,T5
addr_hit[27]	Covered	T4,T5,T2
addr_hit[28]	Covered	T4,T5,T2
addr_hit[29]	Covered	T1,T4,T5
addr_hit[30]	Covered	T4,T5,T2
addr_hit[31]	Covered	T4,T5,T2
addr_hit[32]	Covered	T4,T5,T2
addr_hit[33]	Covered	T1,T4,T5
addr_hit[34]	Covered	T4,T5,T2
addr_hit[35]	Covered	T4,T5,T2
addr_hit[36]	Covered	T4,T5,T2
addr_hit[37]	Covered	T1,T4,T5
addr_hit[38]	Covered	T4,T5,T2
addr_hit[39]	Covered	T4,T5,T2
addr_hit[40]	Covered	T1,T4,T5
addr_hit[41]	Covered	T1,T4,T5
addr_hit[42]	Covered	T4,T5,T2
default	Covered	T1,T4,T5

7108           unique case (1'b1)
                      -1-  
7109             addr_hit[5]: begin
7110               reg_busy_sel = ec_rst_ctl_busy;
                   ==>
7111             end
7112             addr_hit[6]: begin
7113               reg_busy_sel = ulp_ac_debounce_ctl_busy;
                   ==>
7114             end
7115             addr_hit[7]: begin
7116               reg_busy_sel = ulp_lid_debounce_ctl_busy;
                   ==>
7117             end
7118             addr_hit[8]: begin
7119               reg_busy_sel = ulp_pwrb_debounce_ctl_busy;
                   ==>
7120             end
7121             addr_hit[9]: begin
7122               reg_busy_sel = ulp_ctl_busy;
                   ==>
7123             end
7124             addr_hit[11]: begin
7125               reg_busy_sel = wkup_status_busy;
                   ==>
7126             end
7127             addr_hit[12]: begin
7128               reg_busy_sel = key_invert_ctl_busy;
                   ==>
7129             end
7130             addr_hit[13]: begin
7131               reg_busy_sel = pin_allowed_ctl_busy;
                   ==>
7132             end
7133             addr_hit[14]: begin
7134               reg_busy_sel = pin_out_ctl_busy;
                   ==>
7135             end
7136             addr_hit[15]: begin
7137               reg_busy_sel = pin_out_value_busy;
                   ==>
7138             end
7139             addr_hit[17]: begin
7140               reg_busy_sel = key_intr_ctl_busy;
                   ==>
7141             end
7142             addr_hit[18]: begin
7143               reg_busy_sel = key_intr_debounce_ctl_busy;
                   ==>
7144             end
7145             addr_hit[19]: begin
7146               reg_busy_sel = auto_block_debounce_ctl_busy;
                   ==>
7147             end
7148             addr_hit[20]: begin
7149               reg_busy_sel = auto_block_out_ctl_busy;
                   ==>
7150             end
7151             addr_hit[21]: begin
7152               reg_busy_sel = com_pre_sel_ctl_0_busy;
                   ==>
7153             end
7154             addr_hit[22]: begin
7155               reg_busy_sel = com_pre_sel_ctl_1_busy;
                   ==>
7156             end
7157             addr_hit[23]: begin
7158               reg_busy_sel = com_pre_sel_ctl_2_busy;
                   ==>
7159             end
7160             addr_hit[24]: begin
7161               reg_busy_sel = com_pre_sel_ctl_3_busy;
                   ==>
7162             end
7163             addr_hit[25]: begin
7164               reg_busy_sel = com_pre_det_ctl_0_busy;
                   ==>
7165             end
7166             addr_hit[26]: begin
7167               reg_busy_sel = com_pre_det_ctl_1_busy;
                   ==>
7168             end
7169             addr_hit[27]: begin
7170               reg_busy_sel = com_pre_det_ctl_2_busy;
                   ==>
7171             end
7172             addr_hit[28]: begin
7173               reg_busy_sel = com_pre_det_ctl_3_busy;
                   ==>
7174             end
7175             addr_hit[29]: begin
7176               reg_busy_sel = com_sel_ctl_0_busy;
                   ==>
7177             end
7178             addr_hit[30]: begin
7179               reg_busy_sel = com_sel_ctl_1_busy;
                   ==>
7180             end
7181             addr_hit[31]: begin
7182               reg_busy_sel = com_sel_ctl_2_busy;
                   ==>
7183             end
7184             addr_hit[32]: begin
7185               reg_busy_sel = com_sel_ctl_3_busy;
                   ==>
7186             end
7187             addr_hit[33]: begin
7188               reg_busy_sel = com_det_ctl_0_busy;
                   ==>
7189             end
7190             addr_hit[34]: begin
7191               reg_busy_sel = com_det_ctl_1_busy;
                   ==>
7192             end
7193             addr_hit[35]: begin
7194               reg_busy_sel = com_det_ctl_2_busy;
                   ==>
7195             end
7196             addr_hit[36]: begin
7197               reg_busy_sel = com_det_ctl_3_busy;
                   ==>
7198             end
7199             addr_hit[37]: begin
7200               reg_busy_sel = com_out_ctl_0_busy;
                   ==>
7201             end
7202             addr_hit[38]: begin
7203               reg_busy_sel = com_out_ctl_1_busy;
                   ==>
7204             end
7205             addr_hit[39]: begin
7206               reg_busy_sel = com_out_ctl_2_busy;
                   ==>
7207             end
7208             addr_hit[40]: begin
7209               reg_busy_sel = com_out_ctl_3_busy;
                   ==>
7210             end
7211             default: begin
7212               reg_busy_sel  = '0;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[5]	Covered	T1,T4,T5
addr_hit[6]	Covered	T4,T5,T2
addr_hit[7]	Covered	T4,T5,T2
addr_hit[8]	Covered	T1,T4,T5
addr_hit[9]	Covered	T1,T4,T5
addr_hit[11]	Covered	T4,T5,T2
addr_hit[12]	Covered	T4,T5,T2
addr_hit[13]	Covered	T1,T4,T5
addr_hit[14]	Covered	T1,T4,T5
addr_hit[15]	Covered	T4,T5,T2
addr_hit[17]	Covered	T4,T5,T2
addr_hit[18]	Covered	T1,T4,T5
addr_hit[19]	Covered	T4,T5,T2
addr_hit[20]	Covered	T4,T5,T2
addr_hit[21]	Covered	T1,T4,T5
addr_hit[22]	Covered	T4,T5,T2
addr_hit[23]	Covered	T4,T5,T2
addr_hit[24]	Covered	T4,T5,T2
addr_hit[25]	Covered	T1,T4,T5
addr_hit[26]	Covered	T1,T4,T5
addr_hit[27]	Covered	T4,T5,T2
addr_hit[28]	Covered	T4,T5,T2
addr_hit[29]	Covered	T1,T4,T5
addr_hit[30]	Covered	T4,T5,T2
addr_hit[31]	Covered	T4,T5,T2
addr_hit[32]	Covered	T4,T5,T2
addr_hit[33]	Covered	T1,T4,T5
addr_hit[34]	Covered	T4,T5,T2
addr_hit[35]	Covered	T4,T5,T2
addr_hit[36]	Covered	T4,T5,T2
addr_hit[37]	Covered	T1,T4,T5
addr_hit[38]	Covered	T4,T5,T2
addr_hit[39]	Covered	T4,T5,T2
addr_hit[40]	Covered	T1,T4,T5
default	Covered	T1,T4,T5

---

Assert Coverage for Module : sysrst_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1278357336	251292	0	0
reAfterRv	1278357336	251292	0	0
rePulse	1278357336	136710	0	0
wePulse	1278357336	114582	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278357336	251292	0	0
T1	68287	14	0	0
T2	215378	11	0	0
T4	55930	46	0	0
T5	235905	44	0	0
T13	202586	2	0	0
T14	128132	62	0	0
T15	173596	5	0	0
T16	337249	16	0	0
T17	159909	238	0	0
T18	57201	44	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278357336	251292	0	0
T1	68287	14	0	0
T2	215378	11	0	0
T4	55930	46	0	0
T5	235905	44	0	0
T13	202586	2	0	0
T14	128132	62	0	0
T15	173596	5	0	0
T16	337249	16	0	0
T17	159909	238	0	0
T18	57201	44	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278357336	136710	0	0
T1	68287	4	0	0
T2	215378	4	0	0
T4	55930	45	0	0
T5	235905	22	0	0
T13	202586	2	0	0
T14	128132	2	0	0
T15	173596	3	0	0
T16	337249	8	0	0
T17	159909	216	0	0
T18	57201	22	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278357336	114582	0	0
T1	68287	10	0	0
T2	215378	7	0	0
T3	0	7	0	0
T4	55930	1	0	0
T5	235905	22	0	0
T13	202586	0	0	0
T14	128132	60	0	0
T15	173596	2	0	0
T16	337249	8	0	0
T17	159909	22	0	0
T18	57201	22	0	0

Line Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
TOTAL		512	512	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
ALWAYS	299	2	2	100.00
CONT_ASSIGN	327	1	1	100.00
ALWAYS	338	2	2	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	377	2	2	100.00
CONT_ASSIGN	405	1	1	100.00
ALWAYS	416	2	2	100.00
CONT_ASSIGN	444	1	1	100.00
ALWAYS	454	2	2	100.00
CONT_ASSIGN	482	1	1	100.00
ALWAYS	495	4	4	100.00
CONT_ASSIGN	525	1	1	100.00
ALWAYS	547	13	13	100.00
CONT_ASSIGN	586	1	1	100.00
ALWAYS	612	17	17	100.00
CONT_ASSIGN	655	1	1	100.00
ALWAYS	672	9	9	100.00
CONT_ASSIGN	707	1	1	100.00
ALWAYS	724	9	9	100.00
CONT_ASSIGN	759	1	1	100.00
ALWAYS	783	15	15	100.00
CONT_ASSIGN	824	1	1	100.00
ALWAYS	835	2	2	100.00
CONT_ASSIGN	863	1	1	100.00
ALWAYS	875	3	3	100.00
CONT_ASSIGN	904	1	1	100.00
ALWAYS	920	7	7	100.00
CONT_ASSIGN	953	1	1	100.00
ALWAYS	968	6	6	100.00
CONT_ASSIGN	1000	1	1	100.00
ALWAYS	1015	6	6	100.00
CONT_ASSIGN	1047	1	1	100.00
ALWAYS	1062	6	6	100.00
CONT_ASSIGN	1094	1	1	100.00
ALWAYS	1109	6	6	100.00
CONT_ASSIGN	1141	1	1	100.00
ALWAYS	1152	2	2	100.00
CONT_ASSIGN	1180	1	1	100.00
ALWAYS	1191	2	2	100.00
CONT_ASSIGN	1219	1	1	100.00
ALWAYS	1230	2	2	100.00
CONT_ASSIGN	1258	1	1	100.00
ALWAYS	1269	2	2	100.00
CONT_ASSIGN	1297	1	1	100.00
ALWAYS	1312	6	6	100.00
CONT_ASSIGN	1344	1	1	100.00
ALWAYS	1359	6	6	100.00
CONT_ASSIGN	1391	1	1	100.00
ALWAYS	1406	6	6	100.00
CONT_ASSIGN	1438	1	1	100.00
ALWAYS	1453	6	6	100.00
CONT_ASSIGN	1485	1	1	100.00
ALWAYS	1496	2	2	100.00
CONT_ASSIGN	1524	1	1	100.00
ALWAYS	1535	2	2	100.00
CONT_ASSIGN	1563	1	1	100.00
ALWAYS	1574	2	2	100.00
CONT_ASSIGN	1602	1	1	100.00
ALWAYS	1613	2	2	100.00
CONT_ASSIGN	1641	1	1	100.00
ALWAYS	1655	5	5	100.00
CONT_ASSIGN	1686	1	1	100.00
ALWAYS	1700	5	5	100.00
CONT_ASSIGN	1731	1	1	100.00
ALWAYS	1745	5	5	100.00
CONT_ASSIGN	1776	1	1	100.00
ALWAYS	1790	5	5	100.00
CONT_ASSIGN	1821	1	1	100.00
CONT_ASSIGN	1884	1	1	100.00
CONT_ASSIGN	1898	1	1	100.00
CONT_ASSIGN	1904	1	1	100.00
CONT_ASSIGN	1918	1	1	100.00
CONT_ASSIGN	1952	1	1	100.00
CONT_ASSIGN	1983	1	1	100.00
CONT_ASSIGN	2015	1	1	100.00
CONT_ASSIGN	2047	1	1	100.00
CONT_ASSIGN	2134	1	1	100.00
CONT_ASSIGN	2165	1	1	100.00
CONT_ASSIGN	2494	1	1	100.00
CONT_ASSIGN	3585	1	1	100.00
CONT_ASSIGN	3968	1	1	100.00
CONT_ASSIGN	4000	1	1	100.00
CONT_ASSIGN	4060	1	1	100.00
CONT_ASSIGN	4229	1	1	100.00
CONT_ASSIGN	4370	1	1	100.00
CONT_ASSIGN	4511	1	1	100.00
CONT_ASSIGN	4652	1	1	100.00
CONT_ASSIGN	4793	1	1	100.00
CONT_ASSIGN	4825	1	1	100.00
CONT_ASSIGN	4857	1	1	100.00
CONT_ASSIGN	4889	1	1	100.00
CONT_ASSIGN	4921	1	1	100.00
CONT_ASSIGN	5062	1	1	100.00
CONT_ASSIGN	5203	1	1	100.00
CONT_ASSIGN	5344	1	1	100.00
CONT_ASSIGN	5485	1	1	100.00
CONT_ASSIGN	5517	1	1	100.00
CONT_ASSIGN	5549	1	1	100.00
CONT_ASSIGN	5581	1	1	100.00
CONT_ASSIGN	5613	1	1	100.00
CONT_ASSIGN	5727	1	1	100.00
CONT_ASSIGN	5841	1	1	100.00
CONT_ASSIGN	5955	1	1	100.00
ALWAYS	6558	44	44	100.00
CONT_ASSIGN	6604	1	1	100.00
ALWAYS	6608	1	1	100.00
CONT_ASSIGN	6655	1	1	100.00
CONT_ASSIGN	6657	1	1	100.00
CONT_ASSIGN	6658	1	1	100.00
CONT_ASSIGN	6660	1	1	100.00
CONT_ASSIGN	6661	1	1	100.00
CONT_ASSIGN	6663	1	1	100.00
CONT_ASSIGN	6664	1	1	100.00
CONT_ASSIGN	6666	1	1	100.00
CONT_ASSIGN	6667	1	1	100.00
CONT_ASSIGN	6669	1	1	100.00
CONT_ASSIGN	6671	1	1	100.00
CONT_ASSIGN	6673	1	1	100.00
CONT_ASSIGN	6675	1	1	100.00
CONT_ASSIGN	6677	1	1	100.00
CONT_ASSIGN	6679	1	1	100.00
CONT_ASSIGN	6680	1	1	100.00
CONT_ASSIGN	6682	1	1	100.00
CONT_ASSIGN	6695	1	1	100.00
CONT_ASSIGN	6712	1	1	100.00
CONT_ASSIGN	6721	1	1	100.00
CONT_ASSIGN	6730	1	1	100.00
CONT_ASSIGN	6745	1	1	100.00
CONT_ASSIGN	6747	1	1	100.00
CONT_ASSIGN	6750	1	1	100.00
CONT_ASSIGN	6757	1	1	100.00
CONT_ASSIGN	6763	1	1	100.00
CONT_ASSIGN	6769	1	1	100.00
CONT_ASSIGN	6775	1	1	100.00
CONT_ASSIGN	6781	1	1	100.00
CONT_ASSIGN	6783	1	1	100.00
CONT_ASSIGN	6785	1	1	100.00
CONT_ASSIGN	6787	1	1	100.00
CONT_ASSIGN	6789	1	1	100.00
CONT_ASSIGN	6795	1	1	100.00
CONT_ASSIGN	6801	1	1	100.00
CONT_ASSIGN	6807	1	1	100.00
CONT_ASSIGN	6813	1	1	100.00
CONT_ASSIGN	6815	1	1	100.00
CONT_ASSIGN	6817	1	1	100.00
CONT_ASSIGN	6819	1	1	100.00
CONT_ASSIGN	6821	1	1	100.00
CONT_ASSIGN	6826	1	1	100.00
CONT_ASSIGN	6831	1	1	100.00
CONT_ASSIGN	6836	1	1	100.00
CONT_ASSIGN	6841	1	1	100.00
CONT_ASSIGN	6843	1	1	100.00
CONT_ASSIGN	6845	1	1	100.00
CONT_ASSIGN	6847	1	1	100.00
CONT_ASSIGN	6849	1	1	100.00
CONT_ASSIGN	6850	1	1	100.00
CONT_ASSIGN	6852	1	1	100.00
CONT_ASSIGN	6854	1	1	100.00
CONT_ASSIGN	6856	1	1	100.00
CONT_ASSIGN	6858	1	1	100.00
CONT_ASSIGN	6860	1	1	100.00
CONT_ASSIGN	6862	1	1	100.00
CONT_ASSIGN	6864	1	1	100.00
CONT_ASSIGN	6866	1	1	100.00
CONT_ASSIGN	6868	1	1	100.00
CONT_ASSIGN	6870	1	1	100.00
CONT_ASSIGN	6872	1	1	100.00
CONT_ASSIGN	6874	1	1	100.00
CONT_ASSIGN	6876	1	1	100.00
CONT_ASSIGN	6878	1	1	100.00
ALWAYS	6882	44	44	100.00
ALWAYS	6930	68	68	100.00
CONT_ASSIGN	7105	1	1	100.00
ALWAYS	7107	36	36	100.00
CONT_ASSIGN	7224	1	1	100.00
CONT_ASSIGN	7225	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut.u_reg

	Total	Covered	Percent
Conditions	507	507	100.00
Logical	507	507	100.00
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
60-6608	100.00
6608-7105	100.00

---

Branch Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
Branches		84	84	100.00
TERNARY	6604	2	2	100.00
IF	70	3	3	100.00
CASE	6931	44	44	100.00
CASE	7108	35	35	100.00

6604         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

70             if (!rst_ni) begin
               -1-  
71               err_q <= '0;
                 ==>
72             end else if (intg_err || reg_we_err) begin
                        -2-  
73               err_q <= 1'b1;
                 ==>
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T265,T260,T191
0	0	Covered	T1,T4,T5

6931           unique case (1'b1)
                      -1-  
6932             addr_hit[0]: begin
6933               reg_rdata_next[0] = intr_state_qs;
                   ==>
6934             end
6935       
6936             addr_hit[1]: begin
6937               reg_rdata_next[0] = intr_enable_qs;
                   ==>
6938             end
6939       
6940             addr_hit[2]: begin
6941               reg_rdata_next[0] = '0;
                   ==>
6942             end
6943       
6944             addr_hit[3]: begin
6945               reg_rdata_next[0] = '0;
                   ==>
6946             end
6947       
6948             addr_hit[4]: begin
6949               reg_rdata_next[0] = regwen_qs;
                   ==>
6950             end
6951       
6952             addr_hit[5]: begin
6953               reg_rdata_next = DW'(ec_rst_ctl_qs);
                   ==>
6954             end
6955             addr_hit[6]: begin
6956               reg_rdata_next = DW'(ulp_ac_debounce_ctl_qs);
                   ==>
6957             end
6958             addr_hit[7]: begin
6959               reg_rdata_next = DW'(ulp_lid_debounce_ctl_qs);
                   ==>
6960             end
6961             addr_hit[8]: begin
6962               reg_rdata_next = DW'(ulp_pwrb_debounce_ctl_qs);
                   ==>
6963             end
6964             addr_hit[9]: begin
6965               reg_rdata_next = DW'(ulp_ctl_qs);
                   ==>
6966             end
6967             addr_hit[10]: begin
6968               reg_rdata_next[0] = ulp_status_qs;
                   ==>
6969             end
6970       
6971             addr_hit[11]: begin
6972               reg_rdata_next = DW'(wkup_status_qs);
                   ==>
6973             end
6974             addr_hit[12]: begin
6975               reg_rdata_next = DW'(key_invert_ctl_qs);
                   ==>
6976             end
6977             addr_hit[13]: begin
6978               reg_rdata_next = DW'(pin_allowed_ctl_qs);
                   ==>
6979             end
6980             addr_hit[14]: begin
6981               reg_rdata_next = DW'(pin_out_ctl_qs);
                   ==>
6982             end
6983             addr_hit[15]: begin
6984               reg_rdata_next = DW'(pin_out_value_qs);
                   ==>
6985             end
6986             addr_hit[16]: begin
6987               reg_rdata_next[0] = pin_in_value_pwrb_in_qs;
                   ==>
6988               reg_rdata_next[1] = pin_in_value_key0_in_qs;
6989               reg_rdata_next[2] = pin_in_value_key1_in_qs;
6990               reg_rdata_next[3] = pin_in_value_key2_in_qs;
6991               reg_rdata_next[4] = pin_in_value_lid_open_qs;
6992               reg_rdata_next[5] = pin_in_value_ac_present_qs;
6993               reg_rdata_next[6] = pin_in_value_ec_rst_l_qs;
6994               reg_rdata_next[7] = pin_in_value_flash_wp_l_qs;
6995             end
6996       
6997             addr_hit[17]: begin
6998               reg_rdata_next = DW'(key_intr_ctl_qs);
                   ==>
6999             end
7000             addr_hit[18]: begin
7001               reg_rdata_next = DW'(key_intr_debounce_ctl_qs);
                   ==>
7002             end
7003             addr_hit[19]: begin
7004               reg_rdata_next = DW'(auto_block_debounce_ctl_qs);
                   ==>
7005             end
7006             addr_hit[20]: begin
7007               reg_rdata_next = DW'(auto_block_out_ctl_qs);
                   ==>
7008             end
7009             addr_hit[21]: begin
7010               reg_rdata_next = DW'(com_pre_sel_ctl_0_qs);
                   ==>
7011             end
7012             addr_hit[22]: begin
7013               reg_rdata_next = DW'(com_pre_sel_ctl_1_qs);
                   ==>
7014             end
7015             addr_hit[23]: begin
7016               reg_rdata_next = DW'(com_pre_sel_ctl_2_qs);
                   ==>
7017             end
7018             addr_hit[24]: begin
7019               reg_rdata_next = DW'(com_pre_sel_ctl_3_qs);
                   ==>
7020             end
7021             addr_hit[25]: begin
7022               reg_rdata_next = DW'(com_pre_det_ctl_0_qs);
                   ==>
7023             end
7024             addr_hit[26]: begin
7025               reg_rdata_next = DW'(com_pre_det_ctl_1_qs);
                   ==>
7026             end
7027             addr_hit[27]: begin
7028               reg_rdata_next = DW'(com_pre_det_ctl_2_qs);
                   ==>
7029             end
7030             addr_hit[28]: begin
7031               reg_rdata_next = DW'(com_pre_det_ctl_3_qs);
                   ==>
7032             end
7033             addr_hit[29]: begin
7034               reg_rdata_next = DW'(com_sel_ctl_0_qs);
                   ==>
7035             end
7036             addr_hit[30]: begin
7037               reg_rdata_next = DW'(com_sel_ctl_1_qs);
                   ==>
7038             end
7039             addr_hit[31]: begin
7040               reg_rdata_next = DW'(com_sel_ctl_2_qs);
                   ==>
7041             end
7042             addr_hit[32]: begin
7043               reg_rdata_next = DW'(com_sel_ctl_3_qs);
                   ==>
7044             end
7045             addr_hit[33]: begin
7046               reg_rdata_next = DW'(com_det_ctl_0_qs);
                   ==>
7047             end
7048             addr_hit[34]: begin
7049               reg_rdata_next = DW'(com_det_ctl_1_qs);
                   ==>
7050             end
7051             addr_hit[35]: begin
7052               reg_rdata_next = DW'(com_det_ctl_2_qs);
                   ==>
7053             end
7054             addr_hit[36]: begin
7055               reg_rdata_next = DW'(com_det_ctl_3_qs);
                   ==>
7056             end
7057             addr_hit[37]: begin
7058               reg_rdata_next = DW'(com_out_ctl_0_qs);
                   ==>
7059             end
7060             addr_hit[38]: begin
7061               reg_rdata_next = DW'(com_out_ctl_1_qs);
                   ==>
7062             end
7063             addr_hit[39]: begin
7064               reg_rdata_next = DW'(com_out_ctl_2_qs);
                   ==>
7065             end
7066             addr_hit[40]: begin
7067               reg_rdata_next = DW'(com_out_ctl_3_qs);
                   ==>
7068             end
7069             addr_hit[41]: begin
7070               reg_rdata_next[0] = combo_intr_status_combo0_h2l_qs;
                   ==>
7071               reg_rdata_next[1] = combo_intr_status_combo1_h2l_qs;
7072               reg_rdata_next[2] = combo_intr_status_combo2_h2l_qs;
7073               reg_rdata_next[3] = combo_intr_status_combo3_h2l_qs;
7074             end
7075       
7076             addr_hit[42]: begin
7077               reg_rdata_next[0] = key_intr_status_pwrb_h2l_qs;
                   ==>
7078               reg_rdata_next[1] = key_intr_status_key0_in_h2l_qs;
7079               reg_rdata_next[2] = key_intr_status_key1_in_h2l_qs;
7080               reg_rdata_next[3] = key_intr_status_key2_in_h2l_qs;
7081               reg_rdata_next[4] = key_intr_status_ac_present_h2l_qs;
7082               reg_rdata_next[5] = key_intr_status_ec_rst_l_h2l_qs;
7083               reg_rdata_next[6] = key_intr_status_flash_wp_l_h2l_qs;
7084               reg_rdata_next[7] = key_intr_status_pwrb_l2h_qs;
7085               reg_rdata_next[8] = key_intr_status_key0_in_l2h_qs;
7086               reg_rdata_next[9] = key_intr_status_key1_in_l2h_qs;
7087               reg_rdata_next[10] = key_intr_status_key2_in_l2h_qs;
7088               reg_rdata_next[11] = key_intr_status_ac_present_l2h_qs;
7089               reg_rdata_next[12] = key_intr_status_ec_rst_l_l2h_qs;
7090               reg_rdata_next[13] = key_intr_status_flash_wp_l_l2h_qs;
7091             end
7092       
7093             default: begin
7094               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T4,T5
addr_hit[1]	Covered	T1,T4,T5
addr_hit[2]	Covered	T4,T5,T2
addr_hit[3]	Covered	T4,T5,T2
addr_hit[4]	Covered	T1,T4,T5
addr_hit[5]	Covered	T1,T4,T5
addr_hit[6]	Covered	T4,T5,T2
addr_hit[7]	Covered	T4,T5,T2
addr_hit[8]	Covered	T1,T4,T5
addr_hit[9]	Covered	T1,T4,T5
addr_hit[10]	Covered	T4,T5,T2
addr_hit[11]	Covered	T4,T5,T2
addr_hit[12]	Covered	T4,T5,T2
addr_hit[13]	Covered	T1,T4,T5
addr_hit[14]	Covered	T1,T4,T5
addr_hit[15]	Covered	T4,T5,T2
addr_hit[16]	Covered	T1,T4,T5
addr_hit[17]	Covered	T4,T5,T2
addr_hit[18]	Covered	T1,T4,T5
addr_hit[19]	Covered	T4,T5,T2
addr_hit[20]	Covered	T4,T5,T2
addr_hit[21]	Covered	T1,T4,T5
addr_hit[22]	Covered	T4,T5,T2
addr_hit[23]	Covered	T4,T5,T2
addr_hit[24]	Covered	T4,T5,T2
addr_hit[25]	Covered	T1,T4,T5
addr_hit[26]	Covered	T1,T4,T5
addr_hit[27]	Covered	T4,T5,T2
addr_hit[28]	Covered	T4,T5,T2
addr_hit[29]	Covered	T1,T4,T5
addr_hit[30]	Covered	T4,T5,T2
addr_hit[31]	Covered	T4,T5,T2
addr_hit[32]	Covered	T4,T5,T2
addr_hit[33]	Covered	T1,T4,T5
addr_hit[34]	Covered	T4,T5,T2
addr_hit[35]	Covered	T4,T5,T2
addr_hit[36]	Covered	T4,T5,T2
addr_hit[37]	Covered	T1,T4,T5
addr_hit[38]	Covered	T4,T5,T2
addr_hit[39]	Covered	T4,T5,T2
addr_hit[40]	Covered	T1,T4,T5
addr_hit[41]	Covered	T1,T4,T5
addr_hit[42]	Covered	T4,T5,T2
default	Covered	T1,T4,T5

7108           unique case (1'b1)
                      -1-  
7109             addr_hit[5]: begin
7110               reg_busy_sel = ec_rst_ctl_busy;
                   ==>
7111             end
7112             addr_hit[6]: begin
7113               reg_busy_sel = ulp_ac_debounce_ctl_busy;
                   ==>
7114             end
7115             addr_hit[7]: begin
7116               reg_busy_sel = ulp_lid_debounce_ctl_busy;
                   ==>
7117             end
7118             addr_hit[8]: begin
7119               reg_busy_sel = ulp_pwrb_debounce_ctl_busy;
                   ==>
7120             end
7121             addr_hit[9]: begin
7122               reg_busy_sel = ulp_ctl_busy;
                   ==>
7123             end
7124             addr_hit[11]: begin
7125               reg_busy_sel = wkup_status_busy;
                   ==>
7126             end
7127             addr_hit[12]: begin
7128               reg_busy_sel = key_invert_ctl_busy;
                   ==>
7129             end
7130             addr_hit[13]: begin
7131               reg_busy_sel = pin_allowed_ctl_busy;
                   ==>
7132             end
7133             addr_hit[14]: begin
7134               reg_busy_sel = pin_out_ctl_busy;
                   ==>
7135             end
7136             addr_hit[15]: begin
7137               reg_busy_sel = pin_out_value_busy;
                   ==>
7138             end
7139             addr_hit[17]: begin
7140               reg_busy_sel = key_intr_ctl_busy;
                   ==>
7141             end
7142             addr_hit[18]: begin
7143               reg_busy_sel = key_intr_debounce_ctl_busy;
                   ==>
7144             end
7145             addr_hit[19]: begin
7146               reg_busy_sel = auto_block_debounce_ctl_busy;
                   ==>
7147             end
7148             addr_hit[20]: begin
7149               reg_busy_sel = auto_block_out_ctl_busy;
                   ==>
7150             end
7151             addr_hit[21]: begin
7152               reg_busy_sel = com_pre_sel_ctl_0_busy;
                   ==>
7153             end
7154             addr_hit[22]: begin
7155               reg_busy_sel = com_pre_sel_ctl_1_busy;
                   ==>
7156             end
7157             addr_hit[23]: begin
7158               reg_busy_sel = com_pre_sel_ctl_2_busy;
                   ==>
7159             end
7160             addr_hit[24]: begin
7161               reg_busy_sel = com_pre_sel_ctl_3_busy;
                   ==>
7162             end
7163             addr_hit[25]: begin
7164               reg_busy_sel = com_pre_det_ctl_0_busy;
                   ==>
7165             end
7166             addr_hit[26]: begin
7167               reg_busy_sel = com_pre_det_ctl_1_busy;
                   ==>
7168             end
7169             addr_hit[27]: begin
7170               reg_busy_sel = com_pre_det_ctl_2_busy;
                   ==>
7171             end
7172             addr_hit[28]: begin
7173               reg_busy_sel = com_pre_det_ctl_3_busy;
                   ==>
7174             end
7175             addr_hit[29]: begin
7176               reg_busy_sel = com_sel_ctl_0_busy;
                   ==>
7177             end
7178             addr_hit[30]: begin
7179               reg_busy_sel = com_sel_ctl_1_busy;
                   ==>
7180             end
7181             addr_hit[31]: begin
7182               reg_busy_sel = com_sel_ctl_2_busy;
                   ==>
7183             end
7184             addr_hit[32]: begin
7185               reg_busy_sel = com_sel_ctl_3_busy;
                   ==>
7186             end
7187             addr_hit[33]: begin
7188               reg_busy_sel = com_det_ctl_0_busy;
                   ==>
7189             end
7190             addr_hit[34]: begin
7191               reg_busy_sel = com_det_ctl_1_busy;
                   ==>
7192             end
7193             addr_hit[35]: begin
7194               reg_busy_sel = com_det_ctl_2_busy;
                   ==>
7195             end
7196             addr_hit[36]: begin
7197               reg_busy_sel = com_det_ctl_3_busy;
                   ==>
7198             end
7199             addr_hit[37]: begin
7200               reg_busy_sel = com_out_ctl_0_busy;
                   ==>
7201             end
7202             addr_hit[38]: begin
7203               reg_busy_sel = com_out_ctl_1_busy;
                   ==>
7204             end
7205             addr_hit[39]: begin
7206               reg_busy_sel = com_out_ctl_2_busy;
                   ==>
7207             end
7208             addr_hit[40]: begin
7209               reg_busy_sel = com_out_ctl_3_busy;
                   ==>
7210             end
7211             default: begin
7212               reg_busy_sel  = '0;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[5]	Covered	T1,T4,T5
addr_hit[6]	Covered	T4,T5,T2
addr_hit[7]	Covered	T4,T5,T2
addr_hit[8]	Covered	T1,T4,T5
addr_hit[9]	Covered	T1,T4,T5
addr_hit[11]	Covered	T4,T5,T2
addr_hit[12]	Covered	T4,T5,T2
addr_hit[13]	Covered	T1,T4,T5
addr_hit[14]	Covered	T1,T4,T5
addr_hit[15]	Covered	T4,T5,T2
addr_hit[17]	Covered	T4,T5,T2
addr_hit[18]	Covered	T1,T4,T5
addr_hit[19]	Covered	T4,T5,T2
addr_hit[20]	Covered	T4,T5,T2
addr_hit[21]	Covered	T1,T4,T5
addr_hit[22]	Covered	T4,T5,T2
addr_hit[23]	Covered	T4,T5,T2
addr_hit[24]	Covered	T4,T5,T2
addr_hit[25]	Covered	T1,T4,T5
addr_hit[26]	Covered	T1,T4,T5
addr_hit[27]	Covered	T4,T5,T2
addr_hit[28]	Covered	T4,T5,T2
addr_hit[29]	Covered	T1,T4,T5
addr_hit[30]	Covered	T4,T5,T2
addr_hit[31]	Covered	T4,T5,T2
addr_hit[32]	Covered	T4,T5,T2
addr_hit[33]	Covered	T1,T4,T5
addr_hit[34]	Covered	T4,T5,T2
addr_hit[35]	Covered	T4,T5,T2
addr_hit[36]	Covered	T4,T5,T2
addr_hit[37]	Covered	T1,T4,T5
addr_hit[38]	Covered	T4,T5,T2
addr_hit[39]	Covered	T4,T5,T2
addr_hit[40]	Covered	T1,T4,T5
default	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1278357336	251292	0	0
reAfterRv	1278357336	251292	0	0
rePulse	1278357336	136710	0	0
wePulse	1278357336	114582	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278357336	251292	0	0
T1	68287	14	0	0
T2	215378	11	0	0
T4	55930	46	0	0
T5	235905	44	0	0
T13	202586	2	0	0
T14	128132	62	0	0
T15	173596	5	0	0
T16	337249	16	0	0
T17	159909	238	0	0
T18	57201	44	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278357336	251292	0	0
T1	68287	14	0	0
T2	215378	11	0	0
T4	55930	46	0	0
T5	235905	44	0	0
T13	202586	2	0	0
T14	128132	62	0	0
T15	173596	5	0	0
T16	337249	16	0	0
T17	159909	238	0	0
T18	57201	44	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278357336	136710	0	0
T1	68287	4	0	0
T2	215378	4	0	0
T4	55930	45	0	0
T5	235905	22	0	0
T13	202586	2	0	0
T14	128132	2	0	0
T15	173596	3	0	0
T16	337249	8	0	0
T17	159909	216	0	0
T18	57201	22	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278357336	114582	0	0
T1	68287	10	0	0
T2	215378	7	0	0
T3	0	7	0	0
T4	55930	1	0	0
T5	235905	22	0	0
T13	202586	0	0	0
T14	128132	60	0	0
T15	173596	2	0	0
T16	337249	8	0	0
T17	159909	22	0	0
T18	57201	22	0	0