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 LINE       6608
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T14
1	1	Covered	T5,T15,T17

 LINE       6608
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T14,T15
1	1	Covered	T5,T14,T17

 LINE       6608
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T14,T15
1	1	Covered	T5,T14,T15

 LINE       6608
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T14,T15
1	1	Covered	T5,T14,T15

 LINE       6608
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T17
1	1	Covered	T5,T15,T16

 LINE       6608
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T15,T16
1	1	Covered	T1,T5,T14

 LINE       6608
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T17,T103
1	1	Covered	T5,T14,T15

 LINE       6608
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T17,T78
1	1	Covered	T5,T14,T15

 LINE       6608
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T5,T15,T17

 LINE       6608
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T15,T17
1	1	Covered	T5,T14,T15

 LINE       6608
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T14,T17
1	1	Covered	T5,T17,T26

 LINE       6608
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T14,T15
1	1	Covered	T5,T14,T15

 LINE       6608
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T5,T15,T16

 LINE       6608
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T17,T103
1	1	Covered	T5,T14,T15

 LINE       6608
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T17,T78
1	1	Covered	T5,T15,T17

 LINE       6608
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T17,T26
1	1	Covered	T5,T15,T17

 LINE       6608
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T5,T14,T15

 LINE       6608
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T15,T17
1	1	Covered	T5,T15,T17

 LINE       6608
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T16,T17
1	1	Covered	T5,T17,T26

 LINE       6608
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T15
1	1	Covered	T5,T15,T17

 LINE       6608
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T5,T2,T14

 LINE       6608
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T5,T17,T3
1	1	Covered	T5,T15,T17

 LINE       6655
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T2
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T33,T275,T276
1	1	1	Covered	T1,T4,T16

 LINE       6658
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T15,T17
1	1	0	Covered	T33,T268,T277
1	1	1	Covered	T68,T62,T266

 LINE       6661
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T15,T17
1	1	0	Covered	T33,T275,T278
1	1	1	Covered	T64,T77,T67

 LINE       6664
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T15
1	1	0	Covered	T33,T268,T278
1	1	1	Covered	T34,T35,T36

 LINE       6667
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T2
1	1	0	Covered	T33,T268,T275
1	1	1	Covered	T1,T2,T15

 LINE       6669
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T33,T268,T276
1	1	1	Covered	T6,T12,T19

 LINE       6671
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T33,T268,T275
1	1	1	Covered	T6,T12,T19

 LINE       6673
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T15
1	1	0	Covered	T268,T276,T278
1	1	1	Covered	T6,T12,T19

 LINE       6675
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T15
1	1	0	Covered	T208,T33,T268
1	1	1	Covered	T6,T12,T19

 LINE       6677
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T33,T275,T276
1	1	1	Covered	T6,T19,T38

 LINE       6680
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T268,T275,T278
1	1	1	Covered	T6,T12,T20

 LINE       6682
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T15,T17
1	1	0	Covered	T33,T268,T275
1	1	1	Covered	T5,T18,T25

 LINE       6695
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T14
1	1	0	Covered	T33,T268,T276
1	1	1	Covered	T5,T14,T17

 LINE       6712
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T2
1	1	0	Covered	T278,T277,T279
1	1	1	Covered	T1,T5,T2

 LINE       6721
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T33,T268,T275
1	1	1	Covered	T14,T17,T26

 LINE       6730
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T33,T278,T277
1	1	1	Covered	T3,T7,T11

 LINE       6745
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T13
1	1	0	Covered	T33,T268,T276
1	1	1	Covered	T1,T2,T3

 LINE       6747
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T181,T33,T275
1	1	1	Covered	T16,T27,T28

 LINE       6750
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T33,T278,T277
1	1	1	Covered	T16,T27,T28

 LINE       6757
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T14
1	1	0	Covered	T33,T268,T275
1	1	1	Covered	T1,T8,T29

 LINE       6763
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T268,T275,T278
1	1	1	Covered	T12,T20,T30

 LINE       6769
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T33,T275,T277
1	1	1	Covered	T12,T20,T30

 LINE       6775
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T276,T278,T277
1	1	1	Covered	T12,T20,T30

 LINE       6781
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T15
1	1	0	Covered	T33,T268,T275
1	1	1	Covered	T1,T8,T29

 LINE       6783
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T14
1	1	0	Covered	T268,T275,T280
1	1	1	Covered	T12,T20,T30

 LINE       6785
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T33,T276,T278
1	1	1	Covered	T12,T20,T30

 LINE       6787
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T13,T14
1	1	0	Covered	T33,T268,T278
1	1	1	Covered	T12,T20,T30

 LINE       6789
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T2
1	1	0	Covered	T33,T268,T281
1	1	1	Covered	T1,T2,T8

 LINE       6795
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T33,T268,T276
1	1	1	Covered	T12,T20,T30

 LINE       6801
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T17
1	1	0	Covered	T33,T268,T276
1	1	1	Covered	T12,T20,T30

 LINE       6807
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T275,T276,T278
1	1	1	Covered	T12,T20,T30

 LINE       6813
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T2
1	1	0	Covered	T33,T276,T278
1	1	1	Covered	T1,T2,T8

 LINE       6815
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T14,T15
1	1	0	Covered	T33,T268,T278
1	1	1	Covered	T12,T20,T30

 LINE       6817
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T15,T17
1	1	0	Covered	T268,T278,T270
1	1	1	Covered	T12,T20,T30

 LINE       6819
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T15,T17
1	1	0	Covered	T36,T268,T275
1	1	1	Covered	T12,T20,T30

 LINE       6821
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T2
1	1	0	Covered	T33,T275,T277
1	1	1	Covered	T1,T2,T8

 LINE       6826
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T15,T17
1	1	0	Covered	T33,T268,T275
1	1	1	Covered	T12,T20,T30

 LINE       6831
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T16,T17
1	1	0	Covered	T33,T268,T275
1	1	1	Covered	T12,T20,T30

 LINE       6836
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T15
1	1	0	Covered	T33,T268,T275
1	1	1	Covered	T12,T20,T30

 LINE       6841
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T5,T2
1	1	0	Covered	T33,T268,T275
1	1	1	Covered	T1,T2,T8

 LINE       6850
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T15,T17
1	1	0	Covered	T268,T275,T278
1	1	1	Covered	T3,T7,T11

 LINE       7105
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2