Go
back
69 always_ff @(posedge clk_i or negedge rst_ni) begin
70 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
71 1/1 err_q <= '0;
Tests: T1 T4 T5
72 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T4 T5
73 1/1 err_q <= 1'b1;
Tests: T265 T260 T191
74 end
MISSING_ELSE
75 end
76
77 // integrity error output is permanent and should be used for alert generation
78 // register errors are transactional
79 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T4 T5
80
81 // outgoing integrity generation
82 tlul_pkg::tl_d2h_t tl_o_pre;
83 tlul_rsp_intg_gen #(
84 .EnableRspIntgGen(1),
85 .EnableDataIntgGen(1)
86 ) u_rsp_intg_gen (
87 .tl_i(tl_o_pre),
88 .tl_o(tl_o)
89 );
90
91 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T4 T5
92 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T4 T5
93
94 tlul_adapter_reg #(
95 .RegAw(AW),
96 .RegDw(DW),
97 .EnableDataIntgGen(0)
98 ) u_reg_if (
99 .clk_i (clk_i),
100 .rst_ni (rst_ni),
101
102 .tl_i (tl_reg_h2d),
103 .tl_o (tl_reg_d2h),
104
105 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
106 .intg_error_o(),
107
108 .we_o (reg_we),
109 .re_o (reg_re),
110 .addr_o (reg_addr),
111 .wdata_o (reg_wdata),
112 .be_o (reg_be),
113 .busy_i (reg_busy),
114 .rdata_i (reg_rdata),
115 .error_i (reg_error)
116 );
117
118 // cdc oversampling signals
119
120 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T4 T5
121 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T4 T2 T17
122
123 // Define SW related signals
124 // Format: <reg>_<field>_{wd|we|qs}
125 // or <reg>_{wd|we|qs} if field == 1 or 0
126 logic intr_state_qs;
127 logic intr_enable_we;
128 logic intr_enable_qs;
129 logic intr_enable_wd;
130 logic intr_test_we;
131 logic intr_test_wd;
132 logic alert_test_we;
133 logic alert_test_wd;
134 logic regwen_we;
135 logic regwen_qs;
136 logic regwen_wd;
137 logic ec_rst_ctl_we;
138 logic [15:0] ec_rst_ctl_qs;
139 logic ec_rst_ctl_busy;
140 logic ulp_ac_debounce_ctl_we;
141 logic [15:0] ulp_ac_debounce_ctl_qs;
142 logic ulp_ac_debounce_ctl_busy;
143 logic ulp_lid_debounce_ctl_we;
144 logic [15:0] ulp_lid_debounce_ctl_qs;
145 logic ulp_lid_debounce_ctl_busy;
146 logic ulp_pwrb_debounce_ctl_we;
147 logic [15:0] ulp_pwrb_debounce_ctl_qs;
148 logic ulp_pwrb_debounce_ctl_busy;
149 logic ulp_ctl_we;
150 logic [0:0] ulp_ctl_qs;
151 logic ulp_ctl_busy;
152 logic ulp_status_we;
153 logic ulp_status_qs;
154 logic ulp_status_wd;
155 logic wkup_status_we;
156 logic [0:0] wkup_status_qs;
157 logic wkup_status_busy;
158 logic key_invert_ctl_we;
159 logic [11:0] key_invert_ctl_qs;
160 logic key_invert_ctl_busy;
161 logic pin_allowed_ctl_we;
162 logic [15:0] pin_allowed_ctl_qs;
163 logic pin_allowed_ctl_busy;
164 logic pin_out_ctl_we;
165 logic [7:0] pin_out_ctl_qs;
166 logic pin_out_ctl_busy;
167 logic pin_out_value_we;
168 logic [7:0] pin_out_value_qs;
169 logic pin_out_value_busy;
170 logic pin_in_value_pwrb_in_qs;
171 logic pin_in_value_key0_in_qs;
172 logic pin_in_value_key1_in_qs;
173 logic pin_in_value_key2_in_qs;
174 logic pin_in_value_lid_open_qs;
175 logic pin_in_value_ac_present_qs;
176 logic pin_in_value_ec_rst_l_qs;
177 logic pin_in_value_flash_wp_l_qs;
178 logic key_intr_ctl_we;
179 logic [13:0] key_intr_ctl_qs;
180 logic key_intr_ctl_busy;
181 logic key_intr_debounce_ctl_we;
182 logic [15:0] key_intr_debounce_ctl_qs;
183 logic key_intr_debounce_ctl_busy;
184 logic auto_block_debounce_ctl_we;
185 logic [16:0] auto_block_debounce_ctl_qs;
186 logic auto_block_debounce_ctl_busy;
187 logic auto_block_out_ctl_we;
188 logic [6:0] auto_block_out_ctl_qs;
189 logic auto_block_out_ctl_busy;
190 logic com_pre_sel_ctl_0_we;
191 logic [4:0] com_pre_sel_ctl_0_qs;
192 logic com_pre_sel_ctl_0_busy;
193 logic com_pre_sel_ctl_1_we;
194 logic [4:0] com_pre_sel_ctl_1_qs;
195 logic com_pre_sel_ctl_1_busy;
196 logic com_pre_sel_ctl_2_we;
197 logic [4:0] com_pre_sel_ctl_2_qs;
198 logic com_pre_sel_ctl_2_busy;
199 logic com_pre_sel_ctl_3_we;
200 logic [4:0] com_pre_sel_ctl_3_qs;
201 logic com_pre_sel_ctl_3_busy;
202 logic com_pre_det_ctl_0_we;
203 logic [31:0] com_pre_det_ctl_0_qs;
204 logic com_pre_det_ctl_0_busy;
205 logic com_pre_det_ctl_1_we;
206 logic [31:0] com_pre_det_ctl_1_qs;
207 logic com_pre_det_ctl_1_busy;
208 logic com_pre_det_ctl_2_we;
209 logic [31:0] com_pre_det_ctl_2_qs;
210 logic com_pre_det_ctl_2_busy;
211 logic com_pre_det_ctl_3_we;
212 logic [31:0] com_pre_det_ctl_3_qs;
213 logic com_pre_det_ctl_3_busy;
214 logic com_sel_ctl_0_we;
215 logic [4:0] com_sel_ctl_0_qs;
216 logic com_sel_ctl_0_busy;
217 logic com_sel_ctl_1_we;
218 logic [4:0] com_sel_ctl_1_qs;
219 logic com_sel_ctl_1_busy;
220 logic com_sel_ctl_2_we;
221 logic [4:0] com_sel_ctl_2_qs;
222 logic com_sel_ctl_2_busy;
223 logic com_sel_ctl_3_we;
224 logic [4:0] com_sel_ctl_3_qs;
225 logic com_sel_ctl_3_busy;
226 logic com_det_ctl_0_we;
227 logic [31:0] com_det_ctl_0_qs;
228 logic com_det_ctl_0_busy;
229 logic com_det_ctl_1_we;
230 logic [31:0] com_det_ctl_1_qs;
231 logic com_det_ctl_1_busy;
232 logic com_det_ctl_2_we;
233 logic [31:0] com_det_ctl_2_qs;
234 logic com_det_ctl_2_busy;
235 logic com_det_ctl_3_we;
236 logic [31:0] com_det_ctl_3_qs;
237 logic com_det_ctl_3_busy;
238 logic com_out_ctl_0_we;
239 logic [3:0] com_out_ctl_0_qs;
240 logic com_out_ctl_0_busy;
241 logic com_out_ctl_1_we;
242 logic [3:0] com_out_ctl_1_qs;
243 logic com_out_ctl_1_busy;
244 logic com_out_ctl_2_we;
245 logic [3:0] com_out_ctl_2_qs;
246 logic com_out_ctl_2_busy;
247 logic com_out_ctl_3_we;
248 logic [3:0] com_out_ctl_3_qs;
249 logic com_out_ctl_3_busy;
250 logic combo_intr_status_we;
251 logic combo_intr_status_combo0_h2l_qs;
252 logic combo_intr_status_combo0_h2l_wd;
253 logic combo_intr_status_combo1_h2l_qs;
254 logic combo_intr_status_combo1_h2l_wd;
255 logic combo_intr_status_combo2_h2l_qs;
256 logic combo_intr_status_combo2_h2l_wd;
257 logic combo_intr_status_combo3_h2l_qs;
258 logic combo_intr_status_combo3_h2l_wd;
259 logic key_intr_status_we;
260 logic key_intr_status_pwrb_h2l_qs;
261 logic key_intr_status_pwrb_h2l_wd;
262 logic key_intr_status_key0_in_h2l_qs;
263 logic key_intr_status_key0_in_h2l_wd;
264 logic key_intr_status_key1_in_h2l_qs;
265 logic key_intr_status_key1_in_h2l_wd;
266 logic key_intr_status_key2_in_h2l_qs;
267 logic key_intr_status_key2_in_h2l_wd;
268 logic key_intr_status_ac_present_h2l_qs;
269 logic key_intr_status_ac_present_h2l_wd;
270 logic key_intr_status_ec_rst_l_h2l_qs;
271 logic key_intr_status_ec_rst_l_h2l_wd;
272 logic key_intr_status_flash_wp_l_h2l_qs;
273 logic key_intr_status_flash_wp_l_h2l_wd;
274 logic key_intr_status_pwrb_l2h_qs;
275 logic key_intr_status_pwrb_l2h_wd;
276 logic key_intr_status_key0_in_l2h_qs;
277 logic key_intr_status_key0_in_l2h_wd;
278 logic key_intr_status_key1_in_l2h_qs;
279 logic key_intr_status_key1_in_l2h_wd;
280 logic key_intr_status_key2_in_l2h_qs;
281 logic key_intr_status_key2_in_l2h_wd;
282 logic key_intr_status_ac_present_l2h_qs;
283 logic key_intr_status_ac_present_l2h_wd;
284 logic key_intr_status_ec_rst_l_l2h_qs;
285 logic key_intr_status_ec_rst_l_l2h_wd;
286 logic key_intr_status_flash_wp_l_l2h_qs;
287 logic key_intr_status_flash_wp_l_l2h_wd;
288 // Define register CDC handling.
289 // CDC handling is done on a per-reg instead of per-field boundary.
290
291 logic [15:0] aon_ec_rst_ctl_qs_int;
292 logic [15:0] aon_ec_rst_ctl_qs;
293 logic [15:0] aon_ec_rst_ctl_wdata;
294 logic aon_ec_rst_ctl_we;
295 logic unused_aon_ec_rst_ctl_wdata;
296 logic aon_ec_rst_ctl_regwen;
297
298 always_comb begin
299 1/1 aon_ec_rst_ctl_qs = 16'h7d0;
Tests: T1 T2 T15
300 1/1 aon_ec_rst_ctl_qs = aon_ec_rst_ctl_qs_int;
Tests: T1 T2 T15
301 end
302
303 prim_reg_cdc #(
304 .DataWidth(16),
305 .ResetVal(16'h7d0),
306 .BitMask(16'hffff),
307 .DstWrReq(0)
308 ) u_ec_rst_ctl_cdc (
309 .clk_src_i (clk_i),
310 .rst_src_ni (rst_ni),
311 .clk_dst_i (clk_aon_i),
312 .rst_dst_ni (rst_aon_ni),
313 .src_regwen_i (regwen_qs),
314 .src_we_i (ec_rst_ctl_we),
315 .src_re_i ('0),
316 .src_wd_i (reg_wdata[15:0]),
317 .src_busy_o (ec_rst_ctl_busy),
318 .src_qs_o (ec_rst_ctl_qs), // for software read back
319 .dst_update_i ('0),
320 .dst_ds_i ('0),
321 .dst_qs_i (aon_ec_rst_ctl_qs),
322 .dst_we_o (aon_ec_rst_ctl_we),
323 .dst_re_o (),
324 .dst_regwen_o (aon_ec_rst_ctl_regwen),
325 .dst_wd_o (aon_ec_rst_ctl_wdata)
326 );
327 1/1 assign unused_aon_ec_rst_ctl_wdata =
Tests: T1 T4 T5
328 ^aon_ec_rst_ctl_wdata;
329
330 logic [15:0] aon_ulp_ac_debounce_ctl_qs_int;
331 logic [15:0] aon_ulp_ac_debounce_ctl_qs;
332 logic [15:0] aon_ulp_ac_debounce_ctl_wdata;
333 logic aon_ulp_ac_debounce_ctl_we;
334 logic unused_aon_ulp_ac_debounce_ctl_wdata;
335 logic aon_ulp_ac_debounce_ctl_regwen;
336
337 always_comb begin
338 1/1 aon_ulp_ac_debounce_ctl_qs = 16'h1f40;
Tests: T6 T12 T19
339 1/1 aon_ulp_ac_debounce_ctl_qs = aon_ulp_ac_debounce_ctl_qs_int;
Tests: T6 T12 T19
340 end
341
342 prim_reg_cdc #(
343 .DataWidth(16),
344 .ResetVal(16'h1f40),
345 .BitMask(16'hffff),
346 .DstWrReq(0)
347 ) u_ulp_ac_debounce_ctl_cdc (
348 .clk_src_i (clk_i),
349 .rst_src_ni (rst_ni),
350 .clk_dst_i (clk_aon_i),
351 .rst_dst_ni (rst_aon_ni),
352 .src_regwen_i (regwen_qs),
353 .src_we_i (ulp_ac_debounce_ctl_we),
354 .src_re_i ('0),
355 .src_wd_i (reg_wdata[15:0]),
356 .src_busy_o (ulp_ac_debounce_ctl_busy),
357 .src_qs_o (ulp_ac_debounce_ctl_qs), // for software read back
358 .dst_update_i ('0),
359 .dst_ds_i ('0),
360 .dst_qs_i (aon_ulp_ac_debounce_ctl_qs),
361 .dst_we_o (aon_ulp_ac_debounce_ctl_we),
362 .dst_re_o (),
363 .dst_regwen_o (aon_ulp_ac_debounce_ctl_regwen),
364 .dst_wd_o (aon_ulp_ac_debounce_ctl_wdata)
365 );
366 1/1 assign unused_aon_ulp_ac_debounce_ctl_wdata =
Tests: T1 T4 T5
367 ^aon_ulp_ac_debounce_ctl_wdata;
368
369 logic [15:0] aon_ulp_lid_debounce_ctl_qs_int;
370 logic [15:0] aon_ulp_lid_debounce_ctl_qs;
371 logic [15:0] aon_ulp_lid_debounce_ctl_wdata;
372 logic aon_ulp_lid_debounce_ctl_we;
373 logic unused_aon_ulp_lid_debounce_ctl_wdata;
374 logic aon_ulp_lid_debounce_ctl_regwen;
375
376 always_comb begin
377 1/1 aon_ulp_lid_debounce_ctl_qs = 16'h1f40;
Tests: T6 T12 T19
378 1/1 aon_ulp_lid_debounce_ctl_qs = aon_ulp_lid_debounce_ctl_qs_int;
Tests: T6 T12 T19
379 end
380
381 prim_reg_cdc #(
382 .DataWidth(16),
383 .ResetVal(16'h1f40),
384 .BitMask(16'hffff),
385 .DstWrReq(0)
386 ) u_ulp_lid_debounce_ctl_cdc (
387 .clk_src_i (clk_i),
388 .rst_src_ni (rst_ni),
389 .clk_dst_i (clk_aon_i),
390 .rst_dst_ni (rst_aon_ni),
391 .src_regwen_i (regwen_qs),
392 .src_we_i (ulp_lid_debounce_ctl_we),
393 .src_re_i ('0),
394 .src_wd_i (reg_wdata[15:0]),
395 .src_busy_o (ulp_lid_debounce_ctl_busy),
396 .src_qs_o (ulp_lid_debounce_ctl_qs), // for software read back
397 .dst_update_i ('0),
398 .dst_ds_i ('0),
399 .dst_qs_i (aon_ulp_lid_debounce_ctl_qs),
400 .dst_we_o (aon_ulp_lid_debounce_ctl_we),
401 .dst_re_o (),
402 .dst_regwen_o (aon_ulp_lid_debounce_ctl_regwen),
403 .dst_wd_o (aon_ulp_lid_debounce_ctl_wdata)
404 );
405 1/1 assign unused_aon_ulp_lid_debounce_ctl_wdata =
Tests: T1 T4 T5
406 ^aon_ulp_lid_debounce_ctl_wdata;
407
408 logic [15:0] aon_ulp_pwrb_debounce_ctl_qs_int;
409 logic [15:0] aon_ulp_pwrb_debounce_ctl_qs;
410 logic [15:0] aon_ulp_pwrb_debounce_ctl_wdata;
411 logic aon_ulp_pwrb_debounce_ctl_we;
412 logic unused_aon_ulp_pwrb_debounce_ctl_wdata;
413 logic aon_ulp_pwrb_debounce_ctl_regwen;
414
415 always_comb begin
416 1/1 aon_ulp_pwrb_debounce_ctl_qs = 16'h1f40;
Tests: T6 T12 T19
417 1/1 aon_ulp_pwrb_debounce_ctl_qs = aon_ulp_pwrb_debounce_ctl_qs_int;
Tests: T6 T12 T19
418 end
419
420 prim_reg_cdc #(
421 .DataWidth(16),
422 .ResetVal(16'h1f40),
423 .BitMask(16'hffff),
424 .DstWrReq(0)
425 ) u_ulp_pwrb_debounce_ctl_cdc (
426 .clk_src_i (clk_i),
427 .rst_src_ni (rst_ni),
428 .clk_dst_i (clk_aon_i),
429 .rst_dst_ni (rst_aon_ni),
430 .src_regwen_i (regwen_qs),
431 .src_we_i (ulp_pwrb_debounce_ctl_we),
432 .src_re_i ('0),
433 .src_wd_i (reg_wdata[15:0]),
434 .src_busy_o (ulp_pwrb_debounce_ctl_busy),
435 .src_qs_o (ulp_pwrb_debounce_ctl_qs), // for software read back
436 .dst_update_i ('0),
437 .dst_ds_i ('0),
438 .dst_qs_i (aon_ulp_pwrb_debounce_ctl_qs),
439 .dst_we_o (aon_ulp_pwrb_debounce_ctl_we),
440 .dst_re_o (),
441 .dst_regwen_o (aon_ulp_pwrb_debounce_ctl_regwen),
442 .dst_wd_o (aon_ulp_pwrb_debounce_ctl_wdata)
443 );
444 1/1 assign unused_aon_ulp_pwrb_debounce_ctl_wdata =
Tests: T1 T4 T5
445 ^aon_ulp_pwrb_debounce_ctl_wdata;
446
447 logic aon_ulp_ctl_qs_int;
448 logic [0:0] aon_ulp_ctl_qs;
449 logic [0:0] aon_ulp_ctl_wdata;
450 logic aon_ulp_ctl_we;
451 logic unused_aon_ulp_ctl_wdata;
452
453 always_comb begin
454 1/1 aon_ulp_ctl_qs = 1'h0;
Tests: T6 T12 T19
455 1/1 aon_ulp_ctl_qs = aon_ulp_ctl_qs_int;
Tests: T6 T12 T19
456 end
457
458 prim_reg_cdc #(
459 .DataWidth(1),
460 .ResetVal(1'h0),
461 .BitMask(1'h1),
462 .DstWrReq(0)
463 ) u_ulp_ctl_cdc (
464 .clk_src_i (clk_i),
465 .rst_src_ni (rst_ni),
466 .clk_dst_i (clk_aon_i),
467 .rst_dst_ni (rst_aon_ni),
468 .src_regwen_i ('0),
469 .src_we_i (ulp_ctl_we),
470 .src_re_i ('0),
471 .src_wd_i (reg_wdata[0:0]),
472 .src_busy_o (ulp_ctl_busy),
473 .src_qs_o (ulp_ctl_qs), // for software read back
474 .dst_update_i ('0),
475 .dst_ds_i ('0),
476 .dst_qs_i (aon_ulp_ctl_qs),
477 .dst_we_o (aon_ulp_ctl_we),
478 .dst_re_o (),
479 .dst_regwen_o (),
480 .dst_wd_o (aon_ulp_ctl_wdata)
481 );
482 1/1 assign unused_aon_ulp_ctl_wdata =
Tests: T1 T4 T5
483 ^aon_ulp_ctl_wdata;
484
485 logic aon_wkup_status_ds_int;
486 logic aon_wkup_status_qs_int;
487 logic [0:0] aon_wkup_status_ds;
488 logic aon_wkup_status_qe;
489 logic [0:0] aon_wkup_status_qs;
490 logic [0:0] aon_wkup_status_wdata;
491 logic aon_wkup_status_we;
492 logic unused_aon_wkup_status_wdata;
493
494 always_comb begin
495 1/1 aon_wkup_status_qs = 1'h0;
Tests: T1 T2 T3
496 1/1 aon_wkup_status_ds = 1'h0;
Tests: T1 T2 T3
497 1/1 aon_wkup_status_ds = aon_wkup_status_ds_int;
Tests: T1 T2 T3
498 1/1 aon_wkup_status_qs = aon_wkup_status_qs_int;
Tests: T1 T2 T3
499 end
500
501 prim_reg_cdc #(
502 .DataWidth(1),
503 .ResetVal(1'h0),
504 .BitMask(1'h1),
505 .DstWrReq(1)
506 ) u_wkup_status_cdc (
507 .clk_src_i (clk_i),
508 .rst_src_ni (rst_ni),
509 .clk_dst_i (clk_aon_i),
510 .rst_dst_ni (rst_aon_ni),
511 .src_regwen_i ('0),
512 .src_we_i (wkup_status_we),
513 .src_re_i ('0),
514 .src_wd_i (reg_wdata[0:0]),
515 .src_busy_o (wkup_status_busy),
516 .src_qs_o (wkup_status_qs), // for software read back
517 .dst_update_i (aon_wkup_status_qe),
518 .dst_ds_i (aon_wkup_status_ds),
519 .dst_qs_i (aon_wkup_status_qs),
520 .dst_we_o (aon_wkup_status_we),
521 .dst_re_o (),
522 .dst_regwen_o (),
523 .dst_wd_o (aon_wkup_status_wdata)
524 );
525 1/1 assign unused_aon_wkup_status_wdata =
Tests: T1 T4 T5
526 ^aon_wkup_status_wdata;
527
528 logic aon_key_invert_ctl_key0_in_qs_int;
529 logic aon_key_invert_ctl_key0_out_qs_int;
530 logic aon_key_invert_ctl_key1_in_qs_int;
531 logic aon_key_invert_ctl_key1_out_qs_int;
532 logic aon_key_invert_ctl_key2_in_qs_int;
533 logic aon_key_invert_ctl_key2_out_qs_int;
534 logic aon_key_invert_ctl_pwrb_in_qs_int;
535 logic aon_key_invert_ctl_pwrb_out_qs_int;
536 logic aon_key_invert_ctl_ac_present_qs_int;
537 logic aon_key_invert_ctl_bat_disable_qs_int;
538 logic aon_key_invert_ctl_lid_open_qs_int;
539 logic aon_key_invert_ctl_z3_wakeup_qs_int;
540 logic [11:0] aon_key_invert_ctl_qs;
541 logic [11:0] aon_key_invert_ctl_wdata;
542 logic aon_key_invert_ctl_we;
543 logic unused_aon_key_invert_ctl_wdata;
544 logic aon_key_invert_ctl_regwen;
545
546 always_comb begin
547 1/1 aon_key_invert_ctl_qs = 12'h0;
Tests: T5 T18 T25
548 1/1 aon_key_invert_ctl_qs[0] = aon_key_invert_ctl_key0_in_qs_int;
Tests: T5 T18 T25
549 1/1 aon_key_invert_ctl_qs[1] = aon_key_invert_ctl_key0_out_qs_int;
Tests: T5 T18 T25
550 1/1 aon_key_invert_ctl_qs[2] = aon_key_invert_ctl_key1_in_qs_int;
Tests: T5 T18 T25
551 1/1 aon_key_invert_ctl_qs[3] = aon_key_invert_ctl_key1_out_qs_int;
Tests: T5 T18 T25
552 1/1 aon_key_invert_ctl_qs[4] = aon_key_invert_ctl_key2_in_qs_int;
Tests: T5 T18 T25
553 1/1 aon_key_invert_ctl_qs[5] = aon_key_invert_ctl_key2_out_qs_int;
Tests: T5 T18 T25
554 1/1 aon_key_invert_ctl_qs[6] = aon_key_invert_ctl_pwrb_in_qs_int;
Tests: T5 T18 T25
555 1/1 aon_key_invert_ctl_qs[7] = aon_key_invert_ctl_pwrb_out_qs_int;
Tests: T5 T18 T25
556 1/1 aon_key_invert_ctl_qs[8] = aon_key_invert_ctl_ac_present_qs_int;
Tests: T5 T18 T25
557 1/1 aon_key_invert_ctl_qs[9] = aon_key_invert_ctl_bat_disable_qs_int;
Tests: T5 T18 T25
558 1/1 aon_key_invert_ctl_qs[10] = aon_key_invert_ctl_lid_open_qs_int;
Tests: T5 T18 T25
559 1/1 aon_key_invert_ctl_qs[11] = aon_key_invert_ctl_z3_wakeup_qs_int;
Tests: T5 T18 T25
560 end
561
562 prim_reg_cdc #(
563 .DataWidth(12),
564 .ResetVal(12'h0),
565 .BitMask(12'hfff),
566 .DstWrReq(0)
567 ) u_key_invert_ctl_cdc (
568 .clk_src_i (clk_i),
569 .rst_src_ni (rst_ni),
570 .clk_dst_i (clk_aon_i),
571 .rst_dst_ni (rst_aon_ni),
572 .src_regwen_i (regwen_qs),
573 .src_we_i (key_invert_ctl_we),
574 .src_re_i ('0),
575 .src_wd_i (reg_wdata[11:0]),
576 .src_busy_o (key_invert_ctl_busy),
577 .src_qs_o (key_invert_ctl_qs), // for software read back
578 .dst_update_i ('0),
579 .dst_ds_i ('0),
580 .dst_qs_i (aon_key_invert_ctl_qs),
581 .dst_we_o (aon_key_invert_ctl_we),
582 .dst_re_o (),
583 .dst_regwen_o (aon_key_invert_ctl_regwen),
584 .dst_wd_o (aon_key_invert_ctl_wdata)
585 );
586 1/1 assign unused_aon_key_invert_ctl_wdata =
Tests: T1 T4 T5
587 ^aon_key_invert_ctl_wdata;
588
589 logic aon_pin_allowed_ctl_bat_disable_0_qs_int;
590 logic aon_pin_allowed_ctl_ec_rst_l_0_qs_int;
591 logic aon_pin_allowed_ctl_pwrb_out_0_qs_int;
592 logic aon_pin_allowed_ctl_key0_out_0_qs_int;
593 logic aon_pin_allowed_ctl_key1_out_0_qs_int;
594 logic aon_pin_allowed_ctl_key2_out_0_qs_int;
595 logic aon_pin_allowed_ctl_z3_wakeup_0_qs_int;
596 logic aon_pin_allowed_ctl_flash_wp_l_0_qs_int;
597 logic aon_pin_allowed_ctl_bat_disable_1_qs_int;
598 logic aon_pin_allowed_ctl_ec_rst_l_1_qs_int;
599 logic aon_pin_allowed_ctl_pwrb_out_1_qs_int;
600 logic aon_pin_allowed_ctl_key0_out_1_qs_int;
601 logic aon_pin_allowed_ctl_key1_out_1_qs_int;
602 logic aon_pin_allowed_ctl_key2_out_1_qs_int;
603 logic aon_pin_allowed_ctl_z3_wakeup_1_qs_int;
604 logic aon_pin_allowed_ctl_flash_wp_l_1_qs_int;
605 logic [15:0] aon_pin_allowed_ctl_qs;
606 logic [15:0] aon_pin_allowed_ctl_wdata;
607 logic aon_pin_allowed_ctl_we;
608 logic unused_aon_pin_allowed_ctl_wdata;
609 logic aon_pin_allowed_ctl_regwen;
610
611 always_comb begin
612 1/1 aon_pin_allowed_ctl_qs = 16'h82;
Tests: T5 T14 T17
613 1/1 aon_pin_allowed_ctl_qs[0] = aon_pin_allowed_ctl_bat_disable_0_qs_int;
Tests: T5 T14 T17
614 1/1 aon_pin_allowed_ctl_qs[1] = aon_pin_allowed_ctl_ec_rst_l_0_qs_int;
Tests: T5 T14 T17
615 1/1 aon_pin_allowed_ctl_qs[2] = aon_pin_allowed_ctl_pwrb_out_0_qs_int;
Tests: T5 T14 T17
616 1/1 aon_pin_allowed_ctl_qs[3] = aon_pin_allowed_ctl_key0_out_0_qs_int;
Tests: T5 T14 T17
617 1/1 aon_pin_allowed_ctl_qs[4] = aon_pin_allowed_ctl_key1_out_0_qs_int;
Tests: T5 T14 T17
618 1/1 aon_pin_allowed_ctl_qs[5] = aon_pin_allowed_ctl_key2_out_0_qs_int;
Tests: T5 T14 T17
619 1/1 aon_pin_allowed_ctl_qs[6] = aon_pin_allowed_ctl_z3_wakeup_0_qs_int;
Tests: T5 T14 T17
620 1/1 aon_pin_allowed_ctl_qs[7] = aon_pin_allowed_ctl_flash_wp_l_0_qs_int;
Tests: T5 T14 T17
621 1/1 aon_pin_allowed_ctl_qs[8] = aon_pin_allowed_ctl_bat_disable_1_qs_int;
Tests: T5 T14 T17
622 1/1 aon_pin_allowed_ctl_qs[9] = aon_pin_allowed_ctl_ec_rst_l_1_qs_int;
Tests: T5 T14 T17
623 1/1 aon_pin_allowed_ctl_qs[10] = aon_pin_allowed_ctl_pwrb_out_1_qs_int;
Tests: T5 T14 T17
624 1/1 aon_pin_allowed_ctl_qs[11] = aon_pin_allowed_ctl_key0_out_1_qs_int;
Tests: T5 T14 T17
625 1/1 aon_pin_allowed_ctl_qs[12] = aon_pin_allowed_ctl_key1_out_1_qs_int;
Tests: T5 T14 T17
626 1/1 aon_pin_allowed_ctl_qs[13] = aon_pin_allowed_ctl_key2_out_1_qs_int;
Tests: T5 T14 T17
627 1/1 aon_pin_allowed_ctl_qs[14] = aon_pin_allowed_ctl_z3_wakeup_1_qs_int;
Tests: T5 T14 T17
628 1/1 aon_pin_allowed_ctl_qs[15] = aon_pin_allowed_ctl_flash_wp_l_1_qs_int;
Tests: T5 T14 T17
629 end
630
631 prim_reg_cdc #(
632 .DataWidth(16),
633 .ResetVal(16'h82),
634 .BitMask(16'hffff),
635 .DstWrReq(0)
636 ) u_pin_allowed_ctl_cdc (
637 .clk_src_i (clk_i),
638 .rst_src_ni (rst_ni),
639 .clk_dst_i (clk_aon_i),
640 .rst_dst_ni (rst_aon_ni),
641 .src_regwen_i (regwen_qs),
642 .src_we_i (pin_allowed_ctl_we),
643 .src_re_i ('0),
644 .src_wd_i (reg_wdata[15:0]),
645 .src_busy_o (pin_allowed_ctl_busy),
646 .src_qs_o (pin_allowed_ctl_qs), // for software read back
647 .dst_update_i ('0),
648 .dst_ds_i ('0),
649 .dst_qs_i (aon_pin_allowed_ctl_qs),
650 .dst_we_o (aon_pin_allowed_ctl_we),
651 .dst_re_o (),
652 .dst_regwen_o (aon_pin_allowed_ctl_regwen),
653 .dst_wd_o (aon_pin_allowed_ctl_wdata)
654 );
655 1/1 assign unused_aon_pin_allowed_ctl_wdata =
Tests: T1 T4 T5
656 ^aon_pin_allowed_ctl_wdata;
657
658 logic aon_pin_out_ctl_bat_disable_qs_int;
659 logic aon_pin_out_ctl_ec_rst_l_qs_int;
660 logic aon_pin_out_ctl_pwrb_out_qs_int;
661 logic aon_pin_out_ctl_key0_out_qs_int;
662 logic aon_pin_out_ctl_key1_out_qs_int;
663 logic aon_pin_out_ctl_key2_out_qs_int;
664 logic aon_pin_out_ctl_z3_wakeup_qs_int;
665 logic aon_pin_out_ctl_flash_wp_l_qs_int;
666 logic [7:0] aon_pin_out_ctl_qs;
667 logic [7:0] aon_pin_out_ctl_wdata;
668 logic aon_pin_out_ctl_we;
669 logic unused_aon_pin_out_ctl_wdata;
670
671 always_comb begin
672 1/1 aon_pin_out_ctl_qs = 8'h82;
Tests: T1 T5 T2
673 1/1 aon_pin_out_ctl_qs[0] = aon_pin_out_ctl_bat_disable_qs_int;
Tests: T1 T5 T2
674 1/1 aon_pin_out_ctl_qs[1] = aon_pin_out_ctl_ec_rst_l_qs_int;
Tests: T1 T5 T2
675 1/1 aon_pin_out_ctl_qs[2] = aon_pin_out_ctl_pwrb_out_qs_int;
Tests: T1 T5 T2
676 1/1 aon_pin_out_ctl_qs[3] = aon_pin_out_ctl_key0_out_qs_int;
Tests: T1 T5 T2
677 1/1 aon_pin_out_ctl_qs[4] = aon_pin_out_ctl_key1_out_qs_int;
Tests: T1 T5 T2
678 1/1 aon_pin_out_ctl_qs[5] = aon_pin_out_ctl_key2_out_qs_int;
Tests: T1 T5 T2
679 1/1 aon_pin_out_ctl_qs[6] = aon_pin_out_ctl_z3_wakeup_qs_int;
Tests: T1 T5 T2
680 1/1 aon_pin_out_ctl_qs[7] = aon_pin_out_ctl_flash_wp_l_qs_int;
Tests: T1 T5 T2
681 end
682
683 prim_reg_cdc #(
684 .DataWidth(8),
685 .ResetVal(8'h82),
686 .BitMask(8'hff),
687 .DstWrReq(0)
688 ) u_pin_out_ctl_cdc (
689 .clk_src_i (clk_i),
690 .rst_src_ni (rst_ni),
691 .clk_dst_i (clk_aon_i),
692 .rst_dst_ni (rst_aon_ni),
693 .src_regwen_i ('0),
694 .src_we_i (pin_out_ctl_we),
695 .src_re_i ('0),
696 .src_wd_i (reg_wdata[7:0]),
697 .src_busy_o (pin_out_ctl_busy),
698 .src_qs_o (pin_out_ctl_qs), // for software read back
699 .dst_update_i ('0),
700 .dst_ds_i ('0),
701 .dst_qs_i (aon_pin_out_ctl_qs),
702 .dst_we_o (aon_pin_out_ctl_we),
703 .dst_re_o (),
704 .dst_regwen_o (),
705 .dst_wd_o (aon_pin_out_ctl_wdata)
706 );
707 1/1 assign unused_aon_pin_out_ctl_wdata =
Tests: T1 T4 T5
708 ^aon_pin_out_ctl_wdata;
709
710 logic aon_pin_out_value_bat_disable_qs_int;
711 logic aon_pin_out_value_ec_rst_l_qs_int;
712 logic aon_pin_out_value_pwrb_out_qs_int;
713 logic aon_pin_out_value_key0_out_qs_int;
714 logic aon_pin_out_value_key1_out_qs_int;
715 logic aon_pin_out_value_key2_out_qs_int;
716 logic aon_pin_out_value_z3_wakeup_qs_int;
717 logic aon_pin_out_value_flash_wp_l_qs_int;
718 logic [7:0] aon_pin_out_value_qs;
719 logic [7:0] aon_pin_out_value_wdata;
720 logic aon_pin_out_value_we;
721 logic unused_aon_pin_out_value_wdata;
722
723 always_comb begin
724 1/1 aon_pin_out_value_qs = 8'h0;
Tests: T14 T17 T26
725 1/1 aon_pin_out_value_qs[0] = aon_pin_out_value_bat_disable_qs_int;
Tests: T14 T17 T26
726 1/1 aon_pin_out_value_qs[1] = aon_pin_out_value_ec_rst_l_qs_int;
Tests: T14 T17 T26
727 1/1 aon_pin_out_value_qs[2] = aon_pin_out_value_pwrb_out_qs_int;
Tests: T14 T17 T26
728 1/1 aon_pin_out_value_qs[3] = aon_pin_out_value_key0_out_qs_int;
Tests: T14 T17 T26
729 1/1 aon_pin_out_value_qs[4] = aon_pin_out_value_key1_out_qs_int;
Tests: T14 T17 T26
730 1/1 aon_pin_out_value_qs[5] = aon_pin_out_value_key2_out_qs_int;
Tests: T14 T17 T26
731 1/1 aon_pin_out_value_qs[6] = aon_pin_out_value_z3_wakeup_qs_int;
Tests: T14 T17 T26
732 1/1 aon_pin_out_value_qs[7] = aon_pin_out_value_flash_wp_l_qs_int;
Tests: T14 T17 T26
733 end
734
735 prim_reg_cdc #(
736 .DataWidth(8),
737 .ResetVal(8'h0),
738 .BitMask(8'hff),
739 .DstWrReq(0)
740 ) u_pin_out_value_cdc (
741 .clk_src_i (clk_i),
742 .rst_src_ni (rst_ni),
743 .clk_dst_i (clk_aon_i),
744 .rst_dst_ni (rst_aon_ni),
745 .src_regwen_i ('0),
746 .src_we_i (pin_out_value_we),
747 .src_re_i ('0),
748 .src_wd_i (reg_wdata[7:0]),
749 .src_busy_o (pin_out_value_busy),
750 .src_qs_o (pin_out_value_qs), // for software read back
751 .dst_update_i ('0),
752 .dst_ds_i ('0),
753 .dst_qs_i (aon_pin_out_value_qs),
754 .dst_we_o (aon_pin_out_value_we),
755 .dst_re_o (),
756 .dst_regwen_o (),
757 .dst_wd_o (aon_pin_out_value_wdata)
758 );
759 1/1 assign unused_aon_pin_out_value_wdata =
Tests: T1 T4 T5
760 ^aon_pin_out_value_wdata;
761
762 logic aon_key_intr_ctl_pwrb_in_h2l_qs_int;
763 logic aon_key_intr_ctl_key0_in_h2l_qs_int;
764 logic aon_key_intr_ctl_key1_in_h2l_qs_int;
765 logic aon_key_intr_ctl_key2_in_h2l_qs_int;
766 logic aon_key_intr_ctl_ac_present_h2l_qs_int;
767 logic aon_key_intr_ctl_ec_rst_l_h2l_qs_int;
768 logic aon_key_intr_ctl_flash_wp_l_h2l_qs_int;
769 logic aon_key_intr_ctl_pwrb_in_l2h_qs_int;
770 logic aon_key_intr_ctl_key0_in_l2h_qs_int;
771 logic aon_key_intr_ctl_key1_in_l2h_qs_int;
772 logic aon_key_intr_ctl_key2_in_l2h_qs_int;
773 logic aon_key_intr_ctl_ac_present_l2h_qs_int;
774 logic aon_key_intr_ctl_ec_rst_l_l2h_qs_int;
775 logic aon_key_intr_ctl_flash_wp_l_l2h_qs_int;
776 logic [13:0] aon_key_intr_ctl_qs;
777 logic [13:0] aon_key_intr_ctl_wdata;
778 logic aon_key_intr_ctl_we;
779 logic unused_aon_key_intr_ctl_wdata;
780 logic aon_key_intr_ctl_regwen;
781
782 always_comb begin
783 1/1 aon_key_intr_ctl_qs = 14'h0;
Tests: T3 T7 T11
784 1/1 aon_key_intr_ctl_qs[0] = aon_key_intr_ctl_pwrb_in_h2l_qs_int;
Tests: T3 T7 T11
785 1/1 aon_key_intr_ctl_qs[1] = aon_key_intr_ctl_key0_in_h2l_qs_int;
Tests: T3 T7 T11
786 1/1 aon_key_intr_ctl_qs[2] = aon_key_intr_ctl_key1_in_h2l_qs_int;
Tests: T3 T7 T11
787 1/1 aon_key_intr_ctl_qs[3] = aon_key_intr_ctl_key2_in_h2l_qs_int;
Tests: T3 T7 T11
788 1/1 aon_key_intr_ctl_qs[4] = aon_key_intr_ctl_ac_present_h2l_qs_int;
Tests: T3 T7 T11
789 1/1 aon_key_intr_ctl_qs[5] = aon_key_intr_ctl_ec_rst_l_h2l_qs_int;
Tests: T3 T7 T11
790 1/1 aon_key_intr_ctl_qs[6] = aon_key_intr_ctl_flash_wp_l_h2l_qs_int;
Tests: T3 T7 T11
791 1/1 aon_key_intr_ctl_qs[7] = aon_key_intr_ctl_pwrb_in_l2h_qs_int;
Tests: T3 T7 T11
792 1/1 aon_key_intr_ctl_qs[8] = aon_key_intr_ctl_key0_in_l2h_qs_int;
Tests: T3 T7 T11
793 1/1 aon_key_intr_ctl_qs[9] = aon_key_intr_ctl_key1_in_l2h_qs_int;
Tests: T3 T7 T11
794 1/1 aon_key_intr_ctl_qs[10] = aon_key_intr_ctl_key2_in_l2h_qs_int;
Tests: T3 T7 T11
795 1/1 aon_key_intr_ctl_qs[11] = aon_key_intr_ctl_ac_present_l2h_qs_int;
Tests: T3 T7 T11
796 1/1 aon_key_intr_ctl_qs[12] = aon_key_intr_ctl_ec_rst_l_l2h_qs_int;
Tests: T3 T7 T11
797 1/1 aon_key_intr_ctl_qs[13] = aon_key_intr_ctl_flash_wp_l_l2h_qs_int;
Tests: T3 T7 T11
798 end
799
800 prim_reg_cdc #(
801 .DataWidth(14),
802 .ResetVal(14'h0),
803 .BitMask(14'h3fff),
804 .DstWrReq(0)
805 ) u_key_intr_ctl_cdc (
806 .clk_src_i (clk_i),
807 .rst_src_ni (rst_ni),
808 .clk_dst_i (clk_aon_i),
809 .rst_dst_ni (rst_aon_ni),
810 .src_regwen_i (regwen_qs),
811 .src_we_i (key_intr_ctl_we),
812 .src_re_i ('0),
813 .src_wd_i (reg_wdata[13:0]),
814 .src_busy_o (key_intr_ctl_busy),
815 .src_qs_o (key_intr_ctl_qs), // for software read back
816 .dst_update_i ('0),
817 .dst_ds_i ('0),
818 .dst_qs_i (aon_key_intr_ctl_qs),
819 .dst_we_o (aon_key_intr_ctl_we),
820 .dst_re_o (),
821 .dst_regwen_o (aon_key_intr_ctl_regwen),
822 .dst_wd_o (aon_key_intr_ctl_wdata)
823 );
824 1/1 assign unused_aon_key_intr_ctl_wdata =
Tests: T1 T4 T5
825 ^aon_key_intr_ctl_wdata;
826
827 logic [15:0] aon_key_intr_debounce_ctl_qs_int;
828 logic [15:0] aon_key_intr_debounce_ctl_qs;
829 logic [15:0] aon_key_intr_debounce_ctl_wdata;
830 logic aon_key_intr_debounce_ctl_we;
831 logic unused_aon_key_intr_debounce_ctl_wdata;
832 logic aon_key_intr_debounce_ctl_regwen;
833
834 always_comb begin
835 1/1 aon_key_intr_debounce_ctl_qs = 16'h7d0;
Tests: T1 T2 T3
836 1/1 aon_key_intr_debounce_ctl_qs = aon_key_intr_debounce_ctl_qs_int;
Tests: T1 T2 T3
837 end
838
839 prim_reg_cdc #(
840 .DataWidth(16),
841 .ResetVal(16'h7d0),
842 .BitMask(16'hffff),
843 .DstWrReq(0)
844 ) u_key_intr_debounce_ctl_cdc (
845 .clk_src_i (clk_i),
846 .rst_src_ni (rst_ni),
847 .clk_dst_i (clk_aon_i),
848 .rst_dst_ni (rst_aon_ni),
849 .src_regwen_i (regwen_qs),
850 .src_we_i (key_intr_debounce_ctl_we),
851 .src_re_i ('0),
852 .src_wd_i (reg_wdata[15:0]),
853 .src_busy_o (key_intr_debounce_ctl_busy),
854 .src_qs_o (key_intr_debounce_ctl_qs), // for software read back
855 .dst_update_i ('0),
856 .dst_ds_i ('0),
857 .dst_qs_i (aon_key_intr_debounce_ctl_qs),
858 .dst_we_o (aon_key_intr_debounce_ctl_we),
859 .dst_re_o (),
860 .dst_regwen_o (aon_key_intr_debounce_ctl_regwen),
861 .dst_wd_o (aon_key_intr_debounce_ctl_wdata)
862 );
863 1/1 assign unused_aon_key_intr_debounce_ctl_wdata =
Tests: T1 T4 T5
864 ^aon_key_intr_debounce_ctl_wdata;
865
866 logic [15:0] aon_auto_block_debounce_ctl_debounce_timer_qs_int;
867 logic aon_auto_block_debounce_ctl_auto_block_enable_qs_int;
868 logic [16:0] aon_auto_block_debounce_ctl_qs;
869 logic [16:0] aon_auto_block_debounce_ctl_wdata;
870 logic aon_auto_block_debounce_ctl_we;
871 logic unused_aon_auto_block_debounce_ctl_wdata;
872 logic aon_auto_block_debounce_ctl_regwen;
873
874 always_comb begin
875 1/1 aon_auto_block_debounce_ctl_qs = 17'h7d0;
Tests: T16 T27 T28
876 1/1 aon_auto_block_debounce_ctl_qs[15:0] = aon_auto_block_debounce_ctl_debounce_timer_qs_int;
Tests: T16 T27 T28
877 1/1 aon_auto_block_debounce_ctl_qs[16] = aon_auto_block_debounce_ctl_auto_block_enable_qs_int;
Tests: T16 T27 T28
878 end
879
880 prim_reg_cdc #(
881 .DataWidth(17),
882 .ResetVal(17'h7d0),
883 .BitMask(17'h1ffff),
884 .DstWrReq(0)
885 ) u_auto_block_debounce_ctl_cdc (
886 .clk_src_i (clk_i),
887 .rst_src_ni (rst_ni),
888 .clk_dst_i (clk_aon_i),
889 .rst_dst_ni (rst_aon_ni),
890 .src_regwen_i (regwen_qs),
891 .src_we_i (auto_block_debounce_ctl_we),
892 .src_re_i ('0),
893 .src_wd_i (reg_wdata[16:0]),
894 .src_busy_o (auto_block_debounce_ctl_busy),
895 .src_qs_o (auto_block_debounce_ctl_qs), // for software read back
896 .dst_update_i ('0),
897 .dst_ds_i ('0),
898 .dst_qs_i (aon_auto_block_debounce_ctl_qs),
899 .dst_we_o (aon_auto_block_debounce_ctl_we),
900 .dst_re_o (),
901 .dst_regwen_o (aon_auto_block_debounce_ctl_regwen),
902 .dst_wd_o (aon_auto_block_debounce_ctl_wdata)
903 );
904 1/1 assign unused_aon_auto_block_debounce_ctl_wdata =
Tests: T1 T4 T5
905 ^aon_auto_block_debounce_ctl_wdata;
906
907 logic aon_auto_block_out_ctl_key0_out_sel_qs_int;
908 logic aon_auto_block_out_ctl_key1_out_sel_qs_int;
909 logic aon_auto_block_out_ctl_key2_out_sel_qs_int;
910 logic aon_auto_block_out_ctl_key0_out_value_qs_int;
911 logic aon_auto_block_out_ctl_key1_out_value_qs_int;
912 logic aon_auto_block_out_ctl_key2_out_value_qs_int;
913 logic [6:0] aon_auto_block_out_ctl_qs;
914 logic [6:0] aon_auto_block_out_ctl_wdata;
915 logic aon_auto_block_out_ctl_we;
916 logic unused_aon_auto_block_out_ctl_wdata;
917 logic aon_auto_block_out_ctl_regwen;
918
919 always_comb begin
920 1/1 aon_auto_block_out_ctl_qs = 7'h0;
Tests: T16 T27 T28
921 1/1 aon_auto_block_out_ctl_qs[0] = aon_auto_block_out_ctl_key0_out_sel_qs_int;
Tests: T16 T27 T28
922 1/1 aon_auto_block_out_ctl_qs[1] = aon_auto_block_out_ctl_key1_out_sel_qs_int;
Tests: T16 T27 T28
923 1/1 aon_auto_block_out_ctl_qs[2] = aon_auto_block_out_ctl_key2_out_sel_qs_int;
Tests: T16 T27 T28
924 1/1 aon_auto_block_out_ctl_qs[4] = aon_auto_block_out_ctl_key0_out_value_qs_int;
Tests: T16 T27 T28
925 1/1 aon_auto_block_out_ctl_qs[5] = aon_auto_block_out_ctl_key1_out_value_qs_int;
Tests: T16 T27 T28
926 1/1 aon_auto_block_out_ctl_qs[6] = aon_auto_block_out_ctl_key2_out_value_qs_int;
Tests: T16 T27 T28
927 end
928
929 prim_reg_cdc #(
930 .DataWidth(7),
931 .ResetVal(7'h0),
932 .BitMask(7'h77),
933 .DstWrReq(0)
934 ) u_auto_block_out_ctl_cdc (
935 .clk_src_i (clk_i),
936 .rst_src_ni (rst_ni),
937 .clk_dst_i (clk_aon_i),
938 .rst_dst_ni (rst_aon_ni),
939 .src_regwen_i (regwen_qs),
940 .src_we_i (auto_block_out_ctl_we),
941 .src_re_i ('0),
942 .src_wd_i (reg_wdata[6:0]),
943 .src_busy_o (auto_block_out_ctl_busy),
944 .src_qs_o (auto_block_out_ctl_qs), // for software read back
945 .dst_update_i ('0),
946 .dst_ds_i ('0),
947 .dst_qs_i (aon_auto_block_out_ctl_qs),
948 .dst_we_o (aon_auto_block_out_ctl_we),
949 .dst_re_o (),
950 .dst_regwen_o (aon_auto_block_out_ctl_regwen),
951 .dst_wd_o (aon_auto_block_out_ctl_wdata)
952 );
953 1/1 assign unused_aon_auto_block_out_ctl_wdata =
Tests: T1 T4 T5
954 ^aon_auto_block_out_ctl_wdata;
955
956 logic aon_com_pre_sel_ctl_0_key0_in_sel_0_qs_int;
957 logic aon_com_pre_sel_ctl_0_key1_in_sel_0_qs_int;
958 logic aon_com_pre_sel_ctl_0_key2_in_sel_0_qs_int;
959 logic aon_com_pre_sel_ctl_0_pwrb_in_sel_0_qs_int;
960 logic aon_com_pre_sel_ctl_0_ac_present_sel_0_qs_int;
961 logic [4:0] aon_com_pre_sel_ctl_0_qs;
962 logic [4:0] aon_com_pre_sel_ctl_0_wdata;
963 logic aon_com_pre_sel_ctl_0_we;
964 logic unused_aon_com_pre_sel_ctl_0_wdata;
965 logic aon_com_pre_sel_ctl_0_regwen;
966
967 always_comb begin
968 1/1 aon_com_pre_sel_ctl_0_qs = 5'h0;
Tests: T1 T8 T29
969 1/1 aon_com_pre_sel_ctl_0_qs[0] = aon_com_pre_sel_ctl_0_key0_in_sel_0_qs_int;
Tests: T1 T8 T29
970 1/1 aon_com_pre_sel_ctl_0_qs[1] = aon_com_pre_sel_ctl_0_key1_in_sel_0_qs_int;
Tests: T1 T8 T29
971 1/1 aon_com_pre_sel_ctl_0_qs[2] = aon_com_pre_sel_ctl_0_key2_in_sel_0_qs_int;
Tests: T1 T8 T29
972 1/1 aon_com_pre_sel_ctl_0_qs[3] = aon_com_pre_sel_ctl_0_pwrb_in_sel_0_qs_int;
Tests: T1 T8 T29
973 1/1 aon_com_pre_sel_ctl_0_qs[4] = aon_com_pre_sel_ctl_0_ac_present_sel_0_qs_int;
Tests: T1 T8 T29
974 end
975
976 prim_reg_cdc #(
977 .DataWidth(5),
978 .ResetVal(5'h0),
979 .BitMask(5'h1f),
980 .DstWrReq(0)
981 ) u_com_pre_sel_ctl_0_cdc (
982 .clk_src_i (clk_i),
983 .rst_src_ni (rst_ni),
984 .clk_dst_i (clk_aon_i),
985 .rst_dst_ni (rst_aon_ni),
986 .src_regwen_i (regwen_qs),
987 .src_we_i (com_pre_sel_ctl_0_we),
988 .src_re_i ('0),
989 .src_wd_i (reg_wdata[4:0]),
990 .src_busy_o (com_pre_sel_ctl_0_busy),
991 .src_qs_o (com_pre_sel_ctl_0_qs), // for software read back
992 .dst_update_i ('0),
993 .dst_ds_i ('0),
994 .dst_qs_i (aon_com_pre_sel_ctl_0_qs),
995 .dst_we_o (aon_com_pre_sel_ctl_0_we),
996 .dst_re_o (),
997 .dst_regwen_o (aon_com_pre_sel_ctl_0_regwen),
998 .dst_wd_o (aon_com_pre_sel_ctl_0_wdata)
999 );
1000 1/1 assign unused_aon_com_pre_sel_ctl_0_wdata =
Tests: T1 T4 T5
1001 ^aon_com_pre_sel_ctl_0_wdata;
1002
1003 logic aon_com_pre_sel_ctl_1_key0_in_sel_1_qs_int;
1004 logic aon_com_pre_sel_ctl_1_key1_in_sel_1_qs_int;
1005 logic aon_com_pre_sel_ctl_1_key2_in_sel_1_qs_int;
1006 logic aon_com_pre_sel_ctl_1_pwrb_in_sel_1_qs_int;
1007 logic aon_com_pre_sel_ctl_1_ac_present_sel_1_qs_int;
1008 logic [4:0] aon_com_pre_sel_ctl_1_qs;
1009 logic [4:0] aon_com_pre_sel_ctl_1_wdata;
1010 logic aon_com_pre_sel_ctl_1_we;
1011 logic unused_aon_com_pre_sel_ctl_1_wdata;
1012 logic aon_com_pre_sel_ctl_1_regwen;
1013
1014 always_comb begin
1015 1/1 aon_com_pre_sel_ctl_1_qs = 5'h0;
Tests: T12 T20 T30
1016 1/1 aon_com_pre_sel_ctl_1_qs[0] = aon_com_pre_sel_ctl_1_key0_in_sel_1_qs_int;
Tests: T12 T20 T30
1017 1/1 aon_com_pre_sel_ctl_1_qs[1] = aon_com_pre_sel_ctl_1_key1_in_sel_1_qs_int;
Tests: T12 T20 T30
1018 1/1 aon_com_pre_sel_ctl_1_qs[2] = aon_com_pre_sel_ctl_1_key2_in_sel_1_qs_int;
Tests: T12 T20 T30
1019 1/1 aon_com_pre_sel_ctl_1_qs[3] = aon_com_pre_sel_ctl_1_pwrb_in_sel_1_qs_int;
Tests: T12 T20 T30
1020 1/1 aon_com_pre_sel_ctl_1_qs[4] = aon_com_pre_sel_ctl_1_ac_present_sel_1_qs_int;
Tests: T12 T20 T30
1021 end
1022
1023 prim_reg_cdc #(
1024 .DataWidth(5),
1025 .ResetVal(5'h0),
1026 .BitMask(5'h1f),
1027 .DstWrReq(0)
1028 ) u_com_pre_sel_ctl_1_cdc (
1029 .clk_src_i (clk_i),
1030 .rst_src_ni (rst_ni),
1031 .clk_dst_i (clk_aon_i),
1032 .rst_dst_ni (rst_aon_ni),
1033 .src_regwen_i (regwen_qs),
1034 .src_we_i (com_pre_sel_ctl_1_we),
1035 .src_re_i ('0),
1036 .src_wd_i (reg_wdata[4:0]),
1037 .src_busy_o (com_pre_sel_ctl_1_busy),
1038 .src_qs_o (com_pre_sel_ctl_1_qs), // for software read back
1039 .dst_update_i ('0),
1040 .dst_ds_i ('0),
1041 .dst_qs_i (aon_com_pre_sel_ctl_1_qs),
1042 .dst_we_o (aon_com_pre_sel_ctl_1_we),
1043 .dst_re_o (),
1044 .dst_regwen_o (aon_com_pre_sel_ctl_1_regwen),
1045 .dst_wd_o (aon_com_pre_sel_ctl_1_wdata)
1046 );
1047 1/1 assign unused_aon_com_pre_sel_ctl_1_wdata =
Tests: T1 T4 T5
1048 ^aon_com_pre_sel_ctl_1_wdata;
1049
1050 logic aon_com_pre_sel_ctl_2_key0_in_sel_2_qs_int;
1051 logic aon_com_pre_sel_ctl_2_key1_in_sel_2_qs_int;
1052 logic aon_com_pre_sel_ctl_2_key2_in_sel_2_qs_int;
1053 logic aon_com_pre_sel_ctl_2_pwrb_in_sel_2_qs_int;
1054 logic aon_com_pre_sel_ctl_2_ac_present_sel_2_qs_int;
1055 logic [4:0] aon_com_pre_sel_ctl_2_qs;
1056 logic [4:0] aon_com_pre_sel_ctl_2_wdata;
1057 logic aon_com_pre_sel_ctl_2_we;
1058 logic unused_aon_com_pre_sel_ctl_2_wdata;
1059 logic aon_com_pre_sel_ctl_2_regwen;
1060
1061 always_comb begin
1062 1/1 aon_com_pre_sel_ctl_2_qs = 5'h0;
Tests: T12 T20 T30
1063 1/1 aon_com_pre_sel_ctl_2_qs[0] = aon_com_pre_sel_ctl_2_key0_in_sel_2_qs_int;
Tests: T12 T20 T30
1064 1/1 aon_com_pre_sel_ctl_2_qs[1] = aon_com_pre_sel_ctl_2_key1_in_sel_2_qs_int;
Tests: T12 T20 T30
1065 1/1 aon_com_pre_sel_ctl_2_qs[2] = aon_com_pre_sel_ctl_2_key2_in_sel_2_qs_int;
Tests: T12 T20 T30
1066 1/1 aon_com_pre_sel_ctl_2_qs[3] = aon_com_pre_sel_ctl_2_pwrb_in_sel_2_qs_int;
Tests: T12 T20 T30
1067 1/1 aon_com_pre_sel_ctl_2_qs[4] = aon_com_pre_sel_ctl_2_ac_present_sel_2_qs_int;
Tests: T12 T20 T30
1068 end
1069
1070 prim_reg_cdc #(
1071 .DataWidth(5),
1072 .ResetVal(5'h0),
1073 .BitMask(5'h1f),
1074 .DstWrReq(0)
1075 ) u_com_pre_sel_ctl_2_cdc (
1076 .clk_src_i (clk_i),
1077 .rst_src_ni (rst_ni),
1078 .clk_dst_i (clk_aon_i),
1079 .rst_dst_ni (rst_aon_ni),
1080 .src_regwen_i (regwen_qs),
1081 .src_we_i (com_pre_sel_ctl_2_we),
1082 .src_re_i ('0),
1083 .src_wd_i (reg_wdata[4:0]),
1084 .src_busy_o (com_pre_sel_ctl_2_busy),
1085 .src_qs_o (com_pre_sel_ctl_2_qs), // for software read back
1086 .dst_update_i ('0),
1087 .dst_ds_i ('0),
1088 .dst_qs_i (aon_com_pre_sel_ctl_2_qs),
1089 .dst_we_o (aon_com_pre_sel_ctl_2_we),
1090 .dst_re_o (),
1091 .dst_regwen_o (aon_com_pre_sel_ctl_2_regwen),
1092 .dst_wd_o (aon_com_pre_sel_ctl_2_wdata)
1093 );
1094 1/1 assign unused_aon_com_pre_sel_ctl_2_wdata =
Tests: T1 T4 T5
1095 ^aon_com_pre_sel_ctl_2_wdata;
1096
1097 logic aon_com_pre_sel_ctl_3_key0_in_sel_3_qs_int;
1098 logic aon_com_pre_sel_ctl_3_key1_in_sel_3_qs_int;
1099 logic aon_com_pre_sel_ctl_3_key2_in_sel_3_qs_int;
1100 logic aon_com_pre_sel_ctl_3_pwrb_in_sel_3_qs_int;
1101 logic aon_com_pre_sel_ctl_3_ac_present_sel_3_qs_int;
1102 logic [4:0] aon_com_pre_sel_ctl_3_qs;
1103 logic [4:0] aon_com_pre_sel_ctl_3_wdata;
1104 logic aon_com_pre_sel_ctl_3_we;
1105 logic unused_aon_com_pre_sel_ctl_3_wdata;
1106 logic aon_com_pre_sel_ctl_3_regwen;
1107
1108 always_comb begin
1109 1/1 aon_com_pre_sel_ctl_3_qs = 5'h0;
Tests: T12 T20 T30
1110 1/1 aon_com_pre_sel_ctl_3_qs[0] = aon_com_pre_sel_ctl_3_key0_in_sel_3_qs_int;
Tests: T12 T20 T30
1111 1/1 aon_com_pre_sel_ctl_3_qs[1] = aon_com_pre_sel_ctl_3_key1_in_sel_3_qs_int;
Tests: T12 T20 T30
1112 1/1 aon_com_pre_sel_ctl_3_qs[2] = aon_com_pre_sel_ctl_3_key2_in_sel_3_qs_int;
Tests: T12 T20 T30
1113 1/1 aon_com_pre_sel_ctl_3_qs[3] = aon_com_pre_sel_ctl_3_pwrb_in_sel_3_qs_int;
Tests: T12 T20 T30
1114 1/1 aon_com_pre_sel_ctl_3_qs[4] = aon_com_pre_sel_ctl_3_ac_present_sel_3_qs_int;
Tests: T12 T20 T30
1115 end
1116
1117 prim_reg_cdc #(
1118 .DataWidth(5),
1119 .ResetVal(5'h0),
1120 .BitMask(5'h1f),
1121 .DstWrReq(0)
1122 ) u_com_pre_sel_ctl_3_cdc (
1123 .clk_src_i (clk_i),
1124 .rst_src_ni (rst_ni),
1125 .clk_dst_i (clk_aon_i),
1126 .rst_dst_ni (rst_aon_ni),
1127 .src_regwen_i (regwen_qs),
1128 .src_we_i (com_pre_sel_ctl_3_we),
1129 .src_re_i ('0),
1130 .src_wd_i (reg_wdata[4:0]),
1131 .src_busy_o (com_pre_sel_ctl_3_busy),
1132 .src_qs_o (com_pre_sel_ctl_3_qs), // for software read back
1133 .dst_update_i ('0),
1134 .dst_ds_i ('0),
1135 .dst_qs_i (aon_com_pre_sel_ctl_3_qs),
1136 .dst_we_o (aon_com_pre_sel_ctl_3_we),
1137 .dst_re_o (),
1138 .dst_regwen_o (aon_com_pre_sel_ctl_3_regwen),
1139 .dst_wd_o (aon_com_pre_sel_ctl_3_wdata)
1140 );
1141 1/1 assign unused_aon_com_pre_sel_ctl_3_wdata =
Tests: T1 T4 T5
1142 ^aon_com_pre_sel_ctl_3_wdata;
1143
1144 logic [31:0] aon_com_pre_det_ctl_0_qs_int;
1145 logic [31:0] aon_com_pre_det_ctl_0_qs;
1146 logic [31:0] aon_com_pre_det_ctl_0_wdata;
1147 logic aon_com_pre_det_ctl_0_we;
1148 logic unused_aon_com_pre_det_ctl_0_wdata;
1149 logic aon_com_pre_det_ctl_0_regwen;
1150
1151 always_comb begin
1152 1/1 aon_com_pre_det_ctl_0_qs = 32'h0;
Tests: T1 T8 T29
1153 1/1 aon_com_pre_det_ctl_0_qs = aon_com_pre_det_ctl_0_qs_int;
Tests: T1 T8 T29
1154 end
1155
1156 prim_reg_cdc #(
1157 .DataWidth(32),
1158 .ResetVal(32'h0),
1159 .BitMask(32'hffffffff),
1160 .DstWrReq(0)
1161 ) u_com_pre_det_ctl_0_cdc (
1162 .clk_src_i (clk_i),
1163 .rst_src_ni (rst_ni),
1164 .clk_dst_i (clk_aon_i),
1165 .rst_dst_ni (rst_aon_ni),
1166 .src_regwen_i (regwen_qs),
1167 .src_we_i (com_pre_det_ctl_0_we),
1168 .src_re_i ('0),
1169 .src_wd_i (reg_wdata[31:0]),
1170 .src_busy_o (com_pre_det_ctl_0_busy),
1171 .src_qs_o (com_pre_det_ctl_0_qs), // for software read back
1172 .dst_update_i ('0),
1173 .dst_ds_i ('0),
1174 .dst_qs_i (aon_com_pre_det_ctl_0_qs),
1175 .dst_we_o (aon_com_pre_det_ctl_0_we),
1176 .dst_re_o (),
1177 .dst_regwen_o (aon_com_pre_det_ctl_0_regwen),
1178 .dst_wd_o (aon_com_pre_det_ctl_0_wdata)
1179 );
1180 1/1 assign unused_aon_com_pre_det_ctl_0_wdata =
Tests: T1 T4 T5
1181 ^aon_com_pre_det_ctl_0_wdata;
1182
1183 logic [31:0] aon_com_pre_det_ctl_1_qs_int;
1184 logic [31:0] aon_com_pre_det_ctl_1_qs;
1185 logic [31:0] aon_com_pre_det_ctl_1_wdata;
1186 logic aon_com_pre_det_ctl_1_we;
1187 logic unused_aon_com_pre_det_ctl_1_wdata;
1188 logic aon_com_pre_det_ctl_1_regwen;
1189
1190 always_comb begin
1191 1/1 aon_com_pre_det_ctl_1_qs = 32'h0;
Tests: T12 T20 T30
1192 1/1 aon_com_pre_det_ctl_1_qs = aon_com_pre_det_ctl_1_qs_int;
Tests: T12 T20 T30
1193 end
1194
1195 prim_reg_cdc #(
1196 .DataWidth(32),
1197 .ResetVal(32'h0),
1198 .BitMask(32'hffffffff),
1199 .DstWrReq(0)
1200 ) u_com_pre_det_ctl_1_cdc (
1201 .clk_src_i (clk_i),
1202 .rst_src_ni (rst_ni),
1203 .clk_dst_i (clk_aon_i),
1204 .rst_dst_ni (rst_aon_ni),
1205 .src_regwen_i (regwen_qs),
1206 .src_we_i (com_pre_det_ctl_1_we),
1207 .src_re_i ('0),
1208 .src_wd_i (reg_wdata[31:0]),
1209 .src_busy_o (com_pre_det_ctl_1_busy),
1210 .src_qs_o (com_pre_det_ctl_1_qs), // for software read back
1211 .dst_update_i ('0),
1212 .dst_ds_i ('0),
1213 .dst_qs_i (aon_com_pre_det_ctl_1_qs),
1214 .dst_we_o (aon_com_pre_det_ctl_1_we),
1215 .dst_re_o (),
1216 .dst_regwen_o (aon_com_pre_det_ctl_1_regwen),
1217 .dst_wd_o (aon_com_pre_det_ctl_1_wdata)
1218 );
1219 1/1 assign unused_aon_com_pre_det_ctl_1_wdata =
Tests: T1 T4 T5
1220 ^aon_com_pre_det_ctl_1_wdata;
1221
1222 logic [31:0] aon_com_pre_det_ctl_2_qs_int;
1223 logic [31:0] aon_com_pre_det_ctl_2_qs;
1224 logic [31:0] aon_com_pre_det_ctl_2_wdata;
1225 logic aon_com_pre_det_ctl_2_we;
1226 logic unused_aon_com_pre_det_ctl_2_wdata;
1227 logic aon_com_pre_det_ctl_2_regwen;
1228
1229 always_comb begin
1230 1/1 aon_com_pre_det_ctl_2_qs = 32'h0;
Tests: T12 T20 T30
1231 1/1 aon_com_pre_det_ctl_2_qs = aon_com_pre_det_ctl_2_qs_int;
Tests: T12 T20 T30
1232 end
1233
1234 prim_reg_cdc #(
1235 .DataWidth(32),
1236 .ResetVal(32'h0),
1237 .BitMask(32'hffffffff),
1238 .DstWrReq(0)
1239 ) u_com_pre_det_ctl_2_cdc (
1240 .clk_src_i (clk_i),
1241 .rst_src_ni (rst_ni),
1242 .clk_dst_i (clk_aon_i),
1243 .rst_dst_ni (rst_aon_ni),
1244 .src_regwen_i (regwen_qs),
1245 .src_we_i (com_pre_det_ctl_2_we),
1246 .src_re_i ('0),
1247 .src_wd_i (reg_wdata[31:0]),
1248 .src_busy_o (com_pre_det_ctl_2_busy),
1249 .src_qs_o (com_pre_det_ctl_2_qs), // for software read back
1250 .dst_update_i ('0),
1251 .dst_ds_i ('0),
1252 .dst_qs_i (aon_com_pre_det_ctl_2_qs),
1253 .dst_we_o (aon_com_pre_det_ctl_2_we),
1254 .dst_re_o (),
1255 .dst_regwen_o (aon_com_pre_det_ctl_2_regwen),
1256 .dst_wd_o (aon_com_pre_det_ctl_2_wdata)
1257 );
1258 1/1 assign unused_aon_com_pre_det_ctl_2_wdata =
Tests: T1 T4 T5
1259 ^aon_com_pre_det_ctl_2_wdata;
1260
1261 logic [31:0] aon_com_pre_det_ctl_3_qs_int;
1262 logic [31:0] aon_com_pre_det_ctl_3_qs;
1263 logic [31:0] aon_com_pre_det_ctl_3_wdata;
1264 logic aon_com_pre_det_ctl_3_we;
1265 logic unused_aon_com_pre_det_ctl_3_wdata;
1266 logic aon_com_pre_det_ctl_3_regwen;
1267
1268 always_comb begin
1269 1/1 aon_com_pre_det_ctl_3_qs = 32'h0;
Tests: T12 T20 T30
1270 1/1 aon_com_pre_det_ctl_3_qs = aon_com_pre_det_ctl_3_qs_int;
Tests: T12 T20 T30
1271 end
1272
1273 prim_reg_cdc #(
1274 .DataWidth(32),
1275 .ResetVal(32'h0),
1276 .BitMask(32'hffffffff),
1277 .DstWrReq(0)
1278 ) u_com_pre_det_ctl_3_cdc (
1279 .clk_src_i (clk_i),
1280 .rst_src_ni (rst_ni),
1281 .clk_dst_i (clk_aon_i),
1282 .rst_dst_ni (rst_aon_ni),
1283 .src_regwen_i (regwen_qs),
1284 .src_we_i (com_pre_det_ctl_3_we),
1285 .src_re_i ('0),
1286 .src_wd_i (reg_wdata[31:0]),
1287 .src_busy_o (com_pre_det_ctl_3_busy),
1288 .src_qs_o (com_pre_det_ctl_3_qs), // for software read back
1289 .dst_update_i ('0),
1290 .dst_ds_i ('0),
1291 .dst_qs_i (aon_com_pre_det_ctl_3_qs),
1292 .dst_we_o (aon_com_pre_det_ctl_3_we),
1293 .dst_re_o (),
1294 .dst_regwen_o (aon_com_pre_det_ctl_3_regwen),
1295 .dst_wd_o (aon_com_pre_det_ctl_3_wdata)
1296 );
1297 1/1 assign unused_aon_com_pre_det_ctl_3_wdata =
Tests: T1 T4 T5
1298 ^aon_com_pre_det_ctl_3_wdata;
1299
1300 logic aon_com_sel_ctl_0_key0_in_sel_0_qs_int;
1301 logic aon_com_sel_ctl_0_key1_in_sel_0_qs_int;
1302 logic aon_com_sel_ctl_0_key2_in_sel_0_qs_int;
1303 logic aon_com_sel_ctl_0_pwrb_in_sel_0_qs_int;
1304 logic aon_com_sel_ctl_0_ac_present_sel_0_qs_int;
1305 logic [4:0] aon_com_sel_ctl_0_qs;
1306 logic [4:0] aon_com_sel_ctl_0_wdata;
1307 logic aon_com_sel_ctl_0_we;
1308 logic unused_aon_com_sel_ctl_0_wdata;
1309 logic aon_com_sel_ctl_0_regwen;
1310
1311 always_comb begin
1312 1/1 aon_com_sel_ctl_0_qs = 5'h0;
Tests: T1 T2 T8
1313 1/1 aon_com_sel_ctl_0_qs[0] = aon_com_sel_ctl_0_key0_in_sel_0_qs_int;
Tests: T1 T2 T8
1314 1/1 aon_com_sel_ctl_0_qs[1] = aon_com_sel_ctl_0_key1_in_sel_0_qs_int;
Tests: T1 T2 T8
1315 1/1 aon_com_sel_ctl_0_qs[2] = aon_com_sel_ctl_0_key2_in_sel_0_qs_int;
Tests: T1 T2 T8
1316 1/1 aon_com_sel_ctl_0_qs[3] = aon_com_sel_ctl_0_pwrb_in_sel_0_qs_int;
Tests: T1 T2 T8
1317 1/1 aon_com_sel_ctl_0_qs[4] = aon_com_sel_ctl_0_ac_present_sel_0_qs_int;
Tests: T1 T2 T8
1318 end
1319
1320 prim_reg_cdc #(
1321 .DataWidth(5),
1322 .ResetVal(5'h0),
1323 .BitMask(5'h1f),
1324 .DstWrReq(0)
1325 ) u_com_sel_ctl_0_cdc (
1326 .clk_src_i (clk_i),
1327 .rst_src_ni (rst_ni),
1328 .clk_dst_i (clk_aon_i),
1329 .rst_dst_ni (rst_aon_ni),
1330 .src_regwen_i (regwen_qs),
1331 .src_we_i (com_sel_ctl_0_we),
1332 .src_re_i ('0),
1333 .src_wd_i (reg_wdata[4:0]),
1334 .src_busy_o (com_sel_ctl_0_busy),
1335 .src_qs_o (com_sel_ctl_0_qs), // for software read back
1336 .dst_update_i ('0),
1337 .dst_ds_i ('0),
1338 .dst_qs_i (aon_com_sel_ctl_0_qs),
1339 .dst_we_o (aon_com_sel_ctl_0_we),
1340 .dst_re_o (),
1341 .dst_regwen_o (aon_com_sel_ctl_0_regwen),
1342 .dst_wd_o (aon_com_sel_ctl_0_wdata)
1343 );
1344 1/1 assign unused_aon_com_sel_ctl_0_wdata =
Tests: T1 T4 T5
1345 ^aon_com_sel_ctl_0_wdata;
1346
1347 logic aon_com_sel_ctl_1_key0_in_sel_1_qs_int;
1348 logic aon_com_sel_ctl_1_key1_in_sel_1_qs_int;
1349 logic aon_com_sel_ctl_1_key2_in_sel_1_qs_int;
1350 logic aon_com_sel_ctl_1_pwrb_in_sel_1_qs_int;
1351 logic aon_com_sel_ctl_1_ac_present_sel_1_qs_int;
1352 logic [4:0] aon_com_sel_ctl_1_qs;
1353 logic [4:0] aon_com_sel_ctl_1_wdata;
1354 logic aon_com_sel_ctl_1_we;
1355 logic unused_aon_com_sel_ctl_1_wdata;
1356 logic aon_com_sel_ctl_1_regwen;
1357
1358 always_comb begin
1359 1/1 aon_com_sel_ctl_1_qs = 5'h0;
Tests: T12 T20 T30
1360 1/1 aon_com_sel_ctl_1_qs[0] = aon_com_sel_ctl_1_key0_in_sel_1_qs_int;
Tests: T12 T20 T30
1361 1/1 aon_com_sel_ctl_1_qs[1] = aon_com_sel_ctl_1_key1_in_sel_1_qs_int;
Tests: T12 T20 T30
1362 1/1 aon_com_sel_ctl_1_qs[2] = aon_com_sel_ctl_1_key2_in_sel_1_qs_int;
Tests: T12 T20 T30
1363 1/1 aon_com_sel_ctl_1_qs[3] = aon_com_sel_ctl_1_pwrb_in_sel_1_qs_int;
Tests: T12 T20 T30
1364 1/1 aon_com_sel_ctl_1_qs[4] = aon_com_sel_ctl_1_ac_present_sel_1_qs_int;
Tests: T12 T20 T30
1365 end
1366
1367 prim_reg_cdc #(
1368 .DataWidth(5),
1369 .ResetVal(5'h0),
1370 .BitMask(5'h1f),
1371 .DstWrReq(0)
1372 ) u_com_sel_ctl_1_cdc (
1373 .clk_src_i (clk_i),
1374 .rst_src_ni (rst_ni),
1375 .clk_dst_i (clk_aon_i),
1376 .rst_dst_ni (rst_aon_ni),
1377 .src_regwen_i (regwen_qs),
1378 .src_we_i (com_sel_ctl_1_we),
1379 .src_re_i ('0),
1380 .src_wd_i (reg_wdata[4:0]),
1381 .src_busy_o (com_sel_ctl_1_busy),
1382 .src_qs_o (com_sel_ctl_1_qs), // for software read back
1383 .dst_update_i ('0),
1384 .dst_ds_i ('0),
1385 .dst_qs_i (aon_com_sel_ctl_1_qs),
1386 .dst_we_o (aon_com_sel_ctl_1_we),
1387 .dst_re_o (),
1388 .dst_regwen_o (aon_com_sel_ctl_1_regwen),
1389 .dst_wd_o (aon_com_sel_ctl_1_wdata)
1390 );
1391 1/1 assign unused_aon_com_sel_ctl_1_wdata =
Tests: T1 T4 T5
1392 ^aon_com_sel_ctl_1_wdata;
1393
1394 logic aon_com_sel_ctl_2_key0_in_sel_2_qs_int;
1395 logic aon_com_sel_ctl_2_key1_in_sel_2_qs_int;
1396 logic aon_com_sel_ctl_2_key2_in_sel_2_qs_int;
1397 logic aon_com_sel_ctl_2_pwrb_in_sel_2_qs_int;
1398 logic aon_com_sel_ctl_2_ac_present_sel_2_qs_int;
1399 logic [4:0] aon_com_sel_ctl_2_qs;
1400 logic [4:0] aon_com_sel_ctl_2_wdata;
1401 logic aon_com_sel_ctl_2_we;
1402 logic unused_aon_com_sel_ctl_2_wdata;
1403 logic aon_com_sel_ctl_2_regwen;
1404
1405 always_comb begin
1406 1/1 aon_com_sel_ctl_2_qs = 5'h0;
Tests: T12 T20 T30
1407 1/1 aon_com_sel_ctl_2_qs[0] = aon_com_sel_ctl_2_key0_in_sel_2_qs_int;
Tests: T12 T20 T30
1408 1/1 aon_com_sel_ctl_2_qs[1] = aon_com_sel_ctl_2_key1_in_sel_2_qs_int;
Tests: T12 T20 T30
1409 1/1 aon_com_sel_ctl_2_qs[2] = aon_com_sel_ctl_2_key2_in_sel_2_qs_int;
Tests: T12 T20 T30
1410 1/1 aon_com_sel_ctl_2_qs[3] = aon_com_sel_ctl_2_pwrb_in_sel_2_qs_int;
Tests: T12 T20 T30
1411 1/1 aon_com_sel_ctl_2_qs[4] = aon_com_sel_ctl_2_ac_present_sel_2_qs_int;
Tests: T12 T20 T30
1412 end
1413
1414 prim_reg_cdc #(
1415 .DataWidth(5),
1416 .ResetVal(5'h0),
1417 .BitMask(5'h1f),
1418 .DstWrReq(0)
1419 ) u_com_sel_ctl_2_cdc (
1420 .clk_src_i (clk_i),
1421 .rst_src_ni (rst_ni),
1422 .clk_dst_i (clk_aon_i),
1423 .rst_dst_ni (rst_aon_ni),
1424 .src_regwen_i (regwen_qs),
1425 .src_we_i (com_sel_ctl_2_we),
1426 .src_re_i ('0),
1427 .src_wd_i (reg_wdata[4:0]),
1428 .src_busy_o (com_sel_ctl_2_busy),
1429 .src_qs_o (com_sel_ctl_2_qs), // for software read back
1430 .dst_update_i ('0),
1431 .dst_ds_i ('0),
1432 .dst_qs_i (aon_com_sel_ctl_2_qs),
1433 .dst_we_o (aon_com_sel_ctl_2_we),
1434 .dst_re_o (),
1435 .dst_regwen_o (aon_com_sel_ctl_2_regwen),
1436 .dst_wd_o (aon_com_sel_ctl_2_wdata)
1437 );
1438 1/1 assign unused_aon_com_sel_ctl_2_wdata =
Tests: T1 T4 T5
1439 ^aon_com_sel_ctl_2_wdata;
1440
1441 logic aon_com_sel_ctl_3_key0_in_sel_3_qs_int;
1442 logic aon_com_sel_ctl_3_key1_in_sel_3_qs_int;
1443 logic aon_com_sel_ctl_3_key2_in_sel_3_qs_int;
1444 logic aon_com_sel_ctl_3_pwrb_in_sel_3_qs_int;
1445 logic aon_com_sel_ctl_3_ac_present_sel_3_qs_int;
1446 logic [4:0] aon_com_sel_ctl_3_qs;
1447 logic [4:0] aon_com_sel_ctl_3_wdata;
1448 logic aon_com_sel_ctl_3_we;
1449 logic unused_aon_com_sel_ctl_3_wdata;
1450 logic aon_com_sel_ctl_3_regwen;
1451
1452 always_comb begin
1453 1/1 aon_com_sel_ctl_3_qs = 5'h0;
Tests: T12 T20 T30
1454 1/1 aon_com_sel_ctl_3_qs[0] = aon_com_sel_ctl_3_key0_in_sel_3_qs_int;
Tests: T12 T20 T30
1455 1/1 aon_com_sel_ctl_3_qs[1] = aon_com_sel_ctl_3_key1_in_sel_3_qs_int;
Tests: T12 T20 T30
1456 1/1 aon_com_sel_ctl_3_qs[2] = aon_com_sel_ctl_3_key2_in_sel_3_qs_int;
Tests: T12 T20 T30
1457 1/1 aon_com_sel_ctl_3_qs[3] = aon_com_sel_ctl_3_pwrb_in_sel_3_qs_int;
Tests: T12 T20 T30
1458 1/1 aon_com_sel_ctl_3_qs[4] = aon_com_sel_ctl_3_ac_present_sel_3_qs_int;
Tests: T12 T20 T30
1459 end
1460
1461 prim_reg_cdc #(
1462 .DataWidth(5),
1463 .ResetVal(5'h0),
1464 .BitMask(5'h1f),
1465 .DstWrReq(0)
1466 ) u_com_sel_ctl_3_cdc (
1467 .clk_src_i (clk_i),
1468 .rst_src_ni (rst_ni),
1469 .clk_dst_i (clk_aon_i),
1470 .rst_dst_ni (rst_aon_ni),
1471 .src_regwen_i (regwen_qs),
1472 .src_we_i (com_sel_ctl_3_we),
1473 .src_re_i ('0),
1474 .src_wd_i (reg_wdata[4:0]),
1475 .src_busy_o (com_sel_ctl_3_busy),
1476 .src_qs_o (com_sel_ctl_3_qs), // for software read back
1477 .dst_update_i ('0),
1478 .dst_ds_i ('0),
1479 .dst_qs_i (aon_com_sel_ctl_3_qs),
1480 .dst_we_o (aon_com_sel_ctl_3_we),
1481 .dst_re_o (),
1482 .dst_regwen_o (aon_com_sel_ctl_3_regwen),
1483 .dst_wd_o (aon_com_sel_ctl_3_wdata)
1484 );
1485 1/1 assign unused_aon_com_sel_ctl_3_wdata =
Tests: T1 T4 T5
1486 ^aon_com_sel_ctl_3_wdata;
1487
1488 logic [31:0] aon_com_det_ctl_0_qs_int;
1489 logic [31:0] aon_com_det_ctl_0_qs;
1490 logic [31:0] aon_com_det_ctl_0_wdata;
1491 logic aon_com_det_ctl_0_we;
1492 logic unused_aon_com_det_ctl_0_wdata;
1493 logic aon_com_det_ctl_0_regwen;
1494
1495 always_comb begin
1496 1/1 aon_com_det_ctl_0_qs = 32'h0;
Tests: T1 T2 T8
1497 1/1 aon_com_det_ctl_0_qs = aon_com_det_ctl_0_qs_int;
Tests: T1 T2 T8
1498 end
1499
1500 prim_reg_cdc #(
1501 .DataWidth(32),
1502 .ResetVal(32'h0),
1503 .BitMask(32'hffffffff),
1504 .DstWrReq(0)
1505 ) u_com_det_ctl_0_cdc (
1506 .clk_src_i (clk_i),
1507 .rst_src_ni (rst_ni),
1508 .clk_dst_i (clk_aon_i),
1509 .rst_dst_ni (rst_aon_ni),
1510 .src_regwen_i (regwen_qs),
1511 .src_we_i (com_det_ctl_0_we),
1512 .src_re_i ('0),
1513 .src_wd_i (reg_wdata[31:0]),
1514 .src_busy_o (com_det_ctl_0_busy),
1515 .src_qs_o (com_det_ctl_0_qs), // for software read back
1516 .dst_update_i ('0),
1517 .dst_ds_i ('0),
1518 .dst_qs_i (aon_com_det_ctl_0_qs),
1519 .dst_we_o (aon_com_det_ctl_0_we),
1520 .dst_re_o (),
1521 .dst_regwen_o (aon_com_det_ctl_0_regwen),
1522 .dst_wd_o (aon_com_det_ctl_0_wdata)
1523 );
1524 1/1 assign unused_aon_com_det_ctl_0_wdata =
Tests: T1 T4 T5
1525 ^aon_com_det_ctl_0_wdata;
1526
1527 logic [31:0] aon_com_det_ctl_1_qs_int;
1528 logic [31:0] aon_com_det_ctl_1_qs;
1529 logic [31:0] aon_com_det_ctl_1_wdata;
1530 logic aon_com_det_ctl_1_we;
1531 logic unused_aon_com_det_ctl_1_wdata;
1532 logic aon_com_det_ctl_1_regwen;
1533
1534 always_comb begin
1535 1/1 aon_com_det_ctl_1_qs = 32'h0;
Tests: T12 T20 T30
1536 1/1 aon_com_det_ctl_1_qs = aon_com_det_ctl_1_qs_int;
Tests: T12 T20 T30
1537 end
1538
1539 prim_reg_cdc #(
1540 .DataWidth(32),
1541 .ResetVal(32'h0),
1542 .BitMask(32'hffffffff),
1543 .DstWrReq(0)
1544 ) u_com_det_ctl_1_cdc (
1545 .clk_src_i (clk_i),
1546 .rst_src_ni (rst_ni),
1547 .clk_dst_i (clk_aon_i),
1548 .rst_dst_ni (rst_aon_ni),
1549 .src_regwen_i (regwen_qs),
1550 .src_we_i (com_det_ctl_1_we),
1551 .src_re_i ('0),
1552 .src_wd_i (reg_wdata[31:0]),
1553 .src_busy_o (com_det_ctl_1_busy),
1554 .src_qs_o (com_det_ctl_1_qs), // for software read back
1555 .dst_update_i ('0),
1556 .dst_ds_i ('0),
1557 .dst_qs_i (aon_com_det_ctl_1_qs),
1558 .dst_we_o (aon_com_det_ctl_1_we),
1559 .dst_re_o (),
1560 .dst_regwen_o (aon_com_det_ctl_1_regwen),
1561 .dst_wd_o (aon_com_det_ctl_1_wdata)
1562 );
1563 1/1 assign unused_aon_com_det_ctl_1_wdata =
Tests: T1 T4 T5
1564 ^aon_com_det_ctl_1_wdata;
1565
1566 logic [31:0] aon_com_det_ctl_2_qs_int;
1567 logic [31:0] aon_com_det_ctl_2_qs;
1568 logic [31:0] aon_com_det_ctl_2_wdata;
1569 logic aon_com_det_ctl_2_we;
1570 logic unused_aon_com_det_ctl_2_wdata;
1571 logic aon_com_det_ctl_2_regwen;
1572
1573 always_comb begin
1574 1/1 aon_com_det_ctl_2_qs = 32'h0;
Tests: T12 T20 T30
1575 1/1 aon_com_det_ctl_2_qs = aon_com_det_ctl_2_qs_int;
Tests: T12 T20 T30
1576 end
1577
1578 prim_reg_cdc #(
1579 .DataWidth(32),
1580 .ResetVal(32'h0),
1581 .BitMask(32'hffffffff),
1582 .DstWrReq(0)
1583 ) u_com_det_ctl_2_cdc (
1584 .clk_src_i (clk_i),
1585 .rst_src_ni (rst_ni),
1586 .clk_dst_i (clk_aon_i),
1587 .rst_dst_ni (rst_aon_ni),
1588 .src_regwen_i (regwen_qs),
1589 .src_we_i (com_det_ctl_2_we),
1590 .src_re_i ('0),
1591 .src_wd_i (reg_wdata[31:0]),
1592 .src_busy_o (com_det_ctl_2_busy),
1593 .src_qs_o (com_det_ctl_2_qs), // for software read back
1594 .dst_update_i ('0),
1595 .dst_ds_i ('0),
1596 .dst_qs_i (aon_com_det_ctl_2_qs),
1597 .dst_we_o (aon_com_det_ctl_2_we),
1598 .dst_re_o (),
1599 .dst_regwen_o (aon_com_det_ctl_2_regwen),
1600 .dst_wd_o (aon_com_det_ctl_2_wdata)
1601 );
1602 1/1 assign unused_aon_com_det_ctl_2_wdata =
Tests: T1 T4 T5
1603 ^aon_com_det_ctl_2_wdata;
1604
1605 logic [31:0] aon_com_det_ctl_3_qs_int;
1606 logic [31:0] aon_com_det_ctl_3_qs;
1607 logic [31:0] aon_com_det_ctl_3_wdata;
1608 logic aon_com_det_ctl_3_we;
1609 logic unused_aon_com_det_ctl_3_wdata;
1610 logic aon_com_det_ctl_3_regwen;
1611
1612 always_comb begin
1613 1/1 aon_com_det_ctl_3_qs = 32'h0;
Tests: T12 T20 T30
1614 1/1 aon_com_det_ctl_3_qs = aon_com_det_ctl_3_qs_int;
Tests: T12 T20 T30
1615 end
1616
1617 prim_reg_cdc #(
1618 .DataWidth(32),
1619 .ResetVal(32'h0),
1620 .BitMask(32'hffffffff),
1621 .DstWrReq(0)
1622 ) u_com_det_ctl_3_cdc (
1623 .clk_src_i (clk_i),
1624 .rst_src_ni (rst_ni),
1625 .clk_dst_i (clk_aon_i),
1626 .rst_dst_ni (rst_aon_ni),
1627 .src_regwen_i (regwen_qs),
1628 .src_we_i (com_det_ctl_3_we),
1629 .src_re_i ('0),
1630 .src_wd_i (reg_wdata[31:0]),
1631 .src_busy_o (com_det_ctl_3_busy),
1632 .src_qs_o (com_det_ctl_3_qs), // for software read back
1633 .dst_update_i ('0),
1634 .dst_ds_i ('0),
1635 .dst_qs_i (aon_com_det_ctl_3_qs),
1636 .dst_we_o (aon_com_det_ctl_3_we),
1637 .dst_re_o (),
1638 .dst_regwen_o (aon_com_det_ctl_3_regwen),
1639 .dst_wd_o (aon_com_det_ctl_3_wdata)
1640 );
1641 1/1 assign unused_aon_com_det_ctl_3_wdata =
Tests: T1 T4 T5
1642 ^aon_com_det_ctl_3_wdata;
1643
1644 logic aon_com_out_ctl_0_bat_disable_0_qs_int;
1645 logic aon_com_out_ctl_0_interrupt_0_qs_int;
1646 logic aon_com_out_ctl_0_ec_rst_0_qs_int;
1647 logic aon_com_out_ctl_0_rst_req_0_qs_int;
1648 logic [3:0] aon_com_out_ctl_0_qs;
1649 logic [3:0] aon_com_out_ctl_0_wdata;
1650 logic aon_com_out_ctl_0_we;
1651 logic unused_aon_com_out_ctl_0_wdata;
1652 logic aon_com_out_ctl_0_regwen;
1653
1654 always_comb begin
1655 1/1 aon_com_out_ctl_0_qs = 4'h0;
Tests: T1 T2 T8
1656 1/1 aon_com_out_ctl_0_qs[0] = aon_com_out_ctl_0_bat_disable_0_qs_int;
Tests: T1 T2 T8
1657 1/1 aon_com_out_ctl_0_qs[1] = aon_com_out_ctl_0_interrupt_0_qs_int;
Tests: T1 T2 T8
1658 1/1 aon_com_out_ctl_0_qs[2] = aon_com_out_ctl_0_ec_rst_0_qs_int;
Tests: T1 T2 T8
1659 1/1 aon_com_out_ctl_0_qs[3] = aon_com_out_ctl_0_rst_req_0_qs_int;
Tests: T1 T2 T8
1660 end
1661
1662 prim_reg_cdc #(
1663 .DataWidth(4),
1664 .ResetVal(4'h0),
1665 .BitMask(4'hf),
1666 .DstWrReq(0)
1667 ) u_com_out_ctl_0_cdc (
1668 .clk_src_i (clk_i),
1669 .rst_src_ni (rst_ni),
1670 .clk_dst_i (clk_aon_i),
1671 .rst_dst_ni (rst_aon_ni),
1672 .src_regwen_i (regwen_qs),
1673 .src_we_i (com_out_ctl_0_we),
1674 .src_re_i ('0),
1675 .src_wd_i (reg_wdata[3:0]),
1676 .src_busy_o (com_out_ctl_0_busy),
1677 .src_qs_o (com_out_ctl_0_qs), // for software read back
1678 .dst_update_i ('0),
1679 .dst_ds_i ('0),
1680 .dst_qs_i (aon_com_out_ctl_0_qs),
1681 .dst_we_o (aon_com_out_ctl_0_we),
1682 .dst_re_o (),
1683 .dst_regwen_o (aon_com_out_ctl_0_regwen),
1684 .dst_wd_o (aon_com_out_ctl_0_wdata)
1685 );
1686 1/1 assign unused_aon_com_out_ctl_0_wdata =
Tests: T1 T4 T5
1687 ^aon_com_out_ctl_0_wdata;
1688
1689 logic aon_com_out_ctl_1_bat_disable_1_qs_int;
1690 logic aon_com_out_ctl_1_interrupt_1_qs_int;
1691 logic aon_com_out_ctl_1_ec_rst_1_qs_int;
1692 logic aon_com_out_ctl_1_rst_req_1_qs_int;
1693 logic [3:0] aon_com_out_ctl_1_qs;
1694 logic [3:0] aon_com_out_ctl_1_wdata;
1695 logic aon_com_out_ctl_1_we;
1696 logic unused_aon_com_out_ctl_1_wdata;
1697 logic aon_com_out_ctl_1_regwen;
1698
1699 always_comb begin
1700 1/1 aon_com_out_ctl_1_qs = 4'h0;
Tests: T12 T20 T30
1701 1/1 aon_com_out_ctl_1_qs[0] = aon_com_out_ctl_1_bat_disable_1_qs_int;
Tests: T12 T20 T30
1702 1/1 aon_com_out_ctl_1_qs[1] = aon_com_out_ctl_1_interrupt_1_qs_int;
Tests: T12 T20 T30
1703 1/1 aon_com_out_ctl_1_qs[2] = aon_com_out_ctl_1_ec_rst_1_qs_int;
Tests: T12 T20 T30
1704 1/1 aon_com_out_ctl_1_qs[3] = aon_com_out_ctl_1_rst_req_1_qs_int;
Tests: T12 T20 T30
1705 end
1706
1707 prim_reg_cdc #(
1708 .DataWidth(4),
1709 .ResetVal(4'h0),
1710 .BitMask(4'hf),
1711 .DstWrReq(0)
1712 ) u_com_out_ctl_1_cdc (
1713 .clk_src_i (clk_i),
1714 .rst_src_ni (rst_ni),
1715 .clk_dst_i (clk_aon_i),
1716 .rst_dst_ni (rst_aon_ni),
1717 .src_regwen_i (regwen_qs),
1718 .src_we_i (com_out_ctl_1_we),
1719 .src_re_i ('0),
1720 .src_wd_i (reg_wdata[3:0]),
1721 .src_busy_o (com_out_ctl_1_busy),
1722 .src_qs_o (com_out_ctl_1_qs), // for software read back
1723 .dst_update_i ('0),
1724 .dst_ds_i ('0),
1725 .dst_qs_i (aon_com_out_ctl_1_qs),
1726 .dst_we_o (aon_com_out_ctl_1_we),
1727 .dst_re_o (),
1728 .dst_regwen_o (aon_com_out_ctl_1_regwen),
1729 .dst_wd_o (aon_com_out_ctl_1_wdata)
1730 );
1731 1/1 assign unused_aon_com_out_ctl_1_wdata =
Tests: T1 T4 T5
1732 ^aon_com_out_ctl_1_wdata;
1733
1734 logic aon_com_out_ctl_2_bat_disable_2_qs_int;
1735 logic aon_com_out_ctl_2_interrupt_2_qs_int;
1736 logic aon_com_out_ctl_2_ec_rst_2_qs_int;
1737 logic aon_com_out_ctl_2_rst_req_2_qs_int;
1738 logic [3:0] aon_com_out_ctl_2_qs;
1739 logic [3:0] aon_com_out_ctl_2_wdata;
1740 logic aon_com_out_ctl_2_we;
1741 logic unused_aon_com_out_ctl_2_wdata;
1742 logic aon_com_out_ctl_2_regwen;
1743
1744 always_comb begin
1745 1/1 aon_com_out_ctl_2_qs = 4'h0;
Tests: T12 T20 T30
1746 1/1 aon_com_out_ctl_2_qs[0] = aon_com_out_ctl_2_bat_disable_2_qs_int;
Tests: T12 T20 T30
1747 1/1 aon_com_out_ctl_2_qs[1] = aon_com_out_ctl_2_interrupt_2_qs_int;
Tests: T12 T20 T30
1748 1/1 aon_com_out_ctl_2_qs[2] = aon_com_out_ctl_2_ec_rst_2_qs_int;
Tests: T12 T20 T30
1749 1/1 aon_com_out_ctl_2_qs[3] = aon_com_out_ctl_2_rst_req_2_qs_int;
Tests: T12 T20 T30
1750 end
1751
1752 prim_reg_cdc #(
1753 .DataWidth(4),
1754 .ResetVal(4'h0),
1755 .BitMask(4'hf),
1756 .DstWrReq(0)
1757 ) u_com_out_ctl_2_cdc (
1758 .clk_src_i (clk_i),
1759 .rst_src_ni (rst_ni),
1760 .clk_dst_i (clk_aon_i),
1761 .rst_dst_ni (rst_aon_ni),
1762 .src_regwen_i (regwen_qs),
1763 .src_we_i (com_out_ctl_2_we),
1764 .src_re_i ('0),
1765 .src_wd_i (reg_wdata[3:0]),
1766 .src_busy_o (com_out_ctl_2_busy),
1767 .src_qs_o (com_out_ctl_2_qs), // for software read back
1768 .dst_update_i ('0),
1769 .dst_ds_i ('0),
1770 .dst_qs_i (aon_com_out_ctl_2_qs),
1771 .dst_we_o (aon_com_out_ctl_2_we),
1772 .dst_re_o (),
1773 .dst_regwen_o (aon_com_out_ctl_2_regwen),
1774 .dst_wd_o (aon_com_out_ctl_2_wdata)
1775 );
1776 1/1 assign unused_aon_com_out_ctl_2_wdata =
Tests: T1 T4 T5
1777 ^aon_com_out_ctl_2_wdata;
1778
1779 logic aon_com_out_ctl_3_bat_disable_3_qs_int;
1780 logic aon_com_out_ctl_3_interrupt_3_qs_int;
1781 logic aon_com_out_ctl_3_ec_rst_3_qs_int;
1782 logic aon_com_out_ctl_3_rst_req_3_qs_int;
1783 logic [3:0] aon_com_out_ctl_3_qs;
1784 logic [3:0] aon_com_out_ctl_3_wdata;
1785 logic aon_com_out_ctl_3_we;
1786 logic unused_aon_com_out_ctl_3_wdata;
1787 logic aon_com_out_ctl_3_regwen;
1788
1789 always_comb begin
1790 1/1 aon_com_out_ctl_3_qs = 4'h0;
Tests: T12 T31 T32
1791 1/1 aon_com_out_ctl_3_qs[0] = aon_com_out_ctl_3_bat_disable_3_qs_int;
Tests: T12 T31 T32
1792 1/1 aon_com_out_ctl_3_qs[1] = aon_com_out_ctl_3_interrupt_3_qs_int;
Tests: T12 T31 T32
1793 1/1 aon_com_out_ctl_3_qs[2] = aon_com_out_ctl_3_ec_rst_3_qs_int;
Tests: T12 T31 T32
1794 1/1 aon_com_out_ctl_3_qs[3] = aon_com_out_ctl_3_rst_req_3_qs_int;
Tests: T12 T31 T32
1795 end
1796
1797 prim_reg_cdc #(
1798 .DataWidth(4),
1799 .ResetVal(4'h0),
1800 .BitMask(4'hf),
1801 .DstWrReq(0)
1802 ) u_com_out_ctl_3_cdc (
1803 .clk_src_i (clk_i),
1804 .rst_src_ni (rst_ni),
1805 .clk_dst_i (clk_aon_i),
1806 .rst_dst_ni (rst_aon_ni),
1807 .src_regwen_i (regwen_qs),
1808 .src_we_i (com_out_ctl_3_we),
1809 .src_re_i ('0),
1810 .src_wd_i (reg_wdata[3:0]),
1811 .src_busy_o (com_out_ctl_3_busy),
1812 .src_qs_o (com_out_ctl_3_qs), // for software read back
1813 .dst_update_i ('0),
1814 .dst_ds_i ('0),
1815 .dst_qs_i (aon_com_out_ctl_3_qs),
1816 .dst_we_o (aon_com_out_ctl_3_we),
1817 .dst_re_o (),
1818 .dst_regwen_o (aon_com_out_ctl_3_regwen),
1819 .dst_wd_o (aon_com_out_ctl_3_wdata)
1820 );
1821 1/1 assign unused_aon_com_out_ctl_3_wdata =
Tests: T1 T4 T5
1822 ^aon_com_out_ctl_3_wdata;
1823
1824 // Register instances
1825 // R[intr_state]: V(False)
1826 prim_subreg #(
1827 .DW (1),
1828 .SwAccess(prim_subreg_pkg::SwAccessRO),
1829 .RESVAL (1'h0),
1830 .Mubi (1'b0)
1831 ) u_intr_state (
1832 .clk_i (clk_i),
1833 .rst_ni (rst_ni),
1834
1835 // from register interface
1836 .we (1'b0),
1837 .wd ('0),
1838
1839 // from internal hardware
1840 .de (hw2reg.intr_state.de),
1841 .d (hw2reg.intr_state.d),
1842
1843 // to internal hardware
1844 .qe (),
1845 .q (reg2hw.intr_state.q),
1846 .ds (),
1847
1848 // to register interface (read)
1849 .qs (intr_state_qs)
1850 );
1851
1852
1853 // R[intr_enable]: V(False)
1854 prim_subreg #(
1855 .DW (1),
1856 .SwAccess(prim_subreg_pkg::SwAccessRW),
1857 .RESVAL (1'h0),
1858 .Mubi (1'b0)
1859 ) u_intr_enable (
1860 .clk_i (clk_i),
1861 .rst_ni (rst_ni),
1862
1863 // from register interface
1864 .we (intr_enable_we),
1865 .wd (intr_enable_wd),
1866
1867 // from internal hardware
1868 .de (1'b0),
1869 .d ('0),
1870
1871 // to internal hardware
1872 .qe (),
1873 .q (reg2hw.intr_enable.q),
1874 .ds (),
1875
1876 // to register interface (read)
1877 .qs (intr_enable_qs)
1878 );
1879
1880
1881 // R[intr_test]: V(True)
1882 logic intr_test_qe;
1883 logic [0:0] intr_test_flds_we;
1884 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T68 T62 T266
1885 prim_subreg_ext #(
1886 .DW (1)
1887 ) u_intr_test (
1888 .re (1'b0),
1889 .we (intr_test_we),
1890 .wd (intr_test_wd),
1891 .d ('0),
1892 .qre (),
1893 .qe (intr_test_flds_we[0]),
1894 .q (reg2hw.intr_test.q),
1895 .ds (),
1896 .qs ()
1897 );
1898 1/1 assign reg2hw.intr_test.qe = intr_test_qe;
Tests: T68 T62 T266
1899
1900
1901 // R[alert_test]: V(True)
1902 logic alert_test_qe;
1903 logic [0:0] alert_test_flds_we;
1904 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T64 T77 T67
1905 prim_subreg_ext #(
1906 .DW (1)
1907 ) u_alert_test (
1908 .re (1'b0),
1909 .we (alert_test_we),
1910 .wd (alert_test_wd),
1911 .d ('0),
1912 .qre (),
1913 .qe (alert_test_flds_we[0]),
1914 .q (reg2hw.alert_test.q),
1915 .ds (),
1916 .qs ()
1917 );
1918 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T64 T77 T67
1919
1920
1921 // R[regwen]: V(False)
1922 prim_subreg #(
1923 .DW (1),
1924 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1925 .RESVAL (1'h1),
1926 .Mubi (1'b0)
1927 ) u_regwen (
1928 .clk_i (clk_i),
1929 .rst_ni (rst_ni),
1930
1931 // from register interface
1932 .we (regwen_we),
1933 .wd (regwen_wd),
1934
1935 // from internal hardware
1936 .de (1'b0),
1937 .d ('0),
1938
1939 // to internal hardware
1940 .qe (),
1941 .q (),
1942 .ds (),
1943
1944 // to register interface (read)
1945 .qs (regwen_qs)
1946 );
1947
1948
1949 // R[ec_rst_ctl]: V(False)
1950 // Create REGWEN-gated WE signal
1951 logic aon_ec_rst_ctl_gated_we;
1952 1/1 assign aon_ec_rst_ctl_gated_we = aon_ec_rst_ctl_we & aon_ec_rst_ctl_regwen;
Tests: T1 T2 T15
1953 prim_subreg #(
1954 .DW (16),
1955 .SwAccess(prim_subreg_pkg::SwAccessRW),
1956 .RESVAL (16'h7d0),
1957 .Mubi (1'b0)
1958 ) u_ec_rst_ctl (
1959 .clk_i (clk_aon_i),
1960 .rst_ni (rst_aon_ni),
1961
1962 // from register interface
1963 .we (aon_ec_rst_ctl_gated_we),
1964 .wd (aon_ec_rst_ctl_wdata[15:0]),
1965
1966 // from internal hardware
1967 .de (1'b0),
1968 .d ('0),
1969
1970 // to internal hardware
1971 .qe (),
1972 .q (reg2hw.ec_rst_ctl.q),
1973 .ds (),
1974
1975 // to register interface (read)
1976 .qs (aon_ec_rst_ctl_qs_int)
1977 );
1978
1979
1980 // R[ulp_ac_debounce_ctl]: V(False)
1981 // Create REGWEN-gated WE signal
1982 logic aon_ulp_ac_debounce_ctl_gated_we;
1983 1/1 assign aon_ulp_ac_debounce_ctl_gated_we =
Tests: T6 T12 T19
1984 aon_ulp_ac_debounce_ctl_we & aon_ulp_ac_debounce_ctl_regwen;
1985 prim_subreg #(
1986 .DW (16),
1987 .SwAccess(prim_subreg_pkg::SwAccessRW),
1988 .RESVAL (16'h1f40),
1989 .Mubi (1'b0)
1990 ) u_ulp_ac_debounce_ctl (
1991 .clk_i (clk_aon_i),
1992 .rst_ni (rst_aon_ni),
1993
1994 // from register interface
1995 .we (aon_ulp_ac_debounce_ctl_gated_we),
1996 .wd (aon_ulp_ac_debounce_ctl_wdata[15:0]),
1997
1998 // from internal hardware
1999 .de (1'b0),
2000 .d ('0),
2001
2002 // to internal hardware
2003 .qe (),
2004 .q (reg2hw.ulp_ac_debounce_ctl.q),
2005 .ds (),
2006
2007 // to register interface (read)
2008 .qs (aon_ulp_ac_debounce_ctl_qs_int)
2009 );
2010
2011
2012 // R[ulp_lid_debounce_ctl]: V(False)
2013 // Create REGWEN-gated WE signal
2014 logic aon_ulp_lid_debounce_ctl_gated_we;
2015 1/1 assign aon_ulp_lid_debounce_ctl_gated_we =
Tests: T6 T12 T19
2016 aon_ulp_lid_debounce_ctl_we & aon_ulp_lid_debounce_ctl_regwen;
2017 prim_subreg #(
2018 .DW (16),
2019 .SwAccess(prim_subreg_pkg::SwAccessRW),
2020 .RESVAL (16'h1f40),
2021 .Mubi (1'b0)
2022 ) u_ulp_lid_debounce_ctl (
2023 .clk_i (clk_aon_i),
2024 .rst_ni (rst_aon_ni),
2025
2026 // from register interface
2027 .we (aon_ulp_lid_debounce_ctl_gated_we),
2028 .wd (aon_ulp_lid_debounce_ctl_wdata[15:0]),
2029
2030 // from internal hardware
2031 .de (1'b0),
2032 .d ('0),
2033
2034 // to internal hardware
2035 .qe (),
2036 .q (reg2hw.ulp_lid_debounce_ctl.q),
2037 .ds (),
2038
2039 // to register interface (read)
2040 .qs (aon_ulp_lid_debounce_ctl_qs_int)
2041 );
2042
2043
2044 // R[ulp_pwrb_debounce_ctl]: V(False)
2045 // Create REGWEN-gated WE signal
2046 logic aon_ulp_pwrb_debounce_ctl_gated_we;
2047 1/1 assign aon_ulp_pwrb_debounce_ctl_gated_we =
Tests: T6 T12 T19
2048 aon_ulp_pwrb_debounce_ctl_we & aon_ulp_pwrb_debounce_ctl_regwen;
2049 prim_subreg #(
2050 .DW (16),
2051 .SwAccess(prim_subreg_pkg::SwAccessRW),
2052 .RESVAL (16'h1f40),
2053 .Mubi (1'b0)
2054 ) u_ulp_pwrb_debounce_ctl (
2055 .clk_i (clk_aon_i),
2056 .rst_ni (rst_aon_ni),
2057
2058 // from register interface
2059 .we (aon_ulp_pwrb_debounce_ctl_gated_we),
2060 .wd (aon_ulp_pwrb_debounce_ctl_wdata[15:0]),
2061
2062 // from internal hardware
2063 .de (1'b0),
2064 .d ('0),
2065
2066 // to internal hardware
2067 .qe (),
2068 .q (reg2hw.ulp_pwrb_debounce_ctl.q),
2069 .ds (),
2070
2071 // to register interface (read)
2072 .qs (aon_ulp_pwrb_debounce_ctl_qs_int)
2073 );
2074
2075
2076 // R[ulp_ctl]: V(False)
2077 prim_subreg #(
2078 .DW (1),
2079 .SwAccess(prim_subreg_pkg::SwAccessRW),
2080 .RESVAL (1'h0),
2081 .Mubi (1'b0)
2082 ) u_ulp_ctl (
2083 .clk_i (clk_aon_i),
2084 .rst_ni (rst_aon_ni),
2085
2086 // from register interface
2087 .we (aon_ulp_ctl_we),
2088 .wd (aon_ulp_ctl_wdata[0]),
2089
2090 // from internal hardware
2091 .de (1'b0),
2092 .d ('0),
2093
2094 // to internal hardware
2095 .qe (),
2096 .q (reg2hw.ulp_ctl.q),
2097 .ds (),
2098
2099 // to register interface (read)
2100 .qs (aon_ulp_ctl_qs_int)
2101 );
2102
2103
2104 // R[ulp_status]: V(False)
2105 prim_subreg #(
2106 .DW (1),
2107 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2108 .RESVAL (1'h0),
2109 .Mubi (1'b0)
2110 ) u_ulp_status (
2111 .clk_i (clk_i),
2112 .rst_ni (rst_ni),
2113
2114 // from register interface
2115 .we (ulp_status_we),
2116 .wd (ulp_status_wd),
2117
2118 // from internal hardware
2119 .de (hw2reg.ulp_status.de),
2120 .d (hw2reg.ulp_status.d),
2121
2122 // to internal hardware
2123 .qe (),
2124 .q (reg2hw.ulp_status.q),
2125 .ds (),
2126
2127 // to register interface (read)
2128 .qs (ulp_status_qs)
2129 );
2130
2131
2132 // R[wkup_status]: V(False)
2133 logic [0:0] wkup_status_flds_we;
2134 1/1 assign aon_wkup_status_qe = |wkup_status_flds_we;
Tests: T1 T2 T3
2135 prim_subreg #(
2136 .DW (1),
2137 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2138 .RESVAL (1'h0),
2139 .Mubi (1'b0)
2140 ) u_wkup_status (
2141 .clk_i (clk_aon_i),
2142 .rst_ni (rst_aon_ni),
2143
2144 // from register interface
2145 .we (aon_wkup_status_we),
2146 .wd (aon_wkup_status_wdata[0]),
2147
2148 // from internal hardware
2149 .de (hw2reg.wkup_status.de),
2150 .d (hw2reg.wkup_status.d),
2151
2152 // to internal hardware
2153 .qe (wkup_status_flds_we[0]),
2154 .q (reg2hw.wkup_status.q),
2155 .ds (aon_wkup_status_ds_int),
2156
2157 // to register interface (read)
2158 .qs (aon_wkup_status_qs_int)
2159 );
2160
2161
2162 // R[key_invert_ctl]: V(False)
2163 // Create REGWEN-gated WE signal
2164 logic aon_key_invert_ctl_gated_we;
2165 1/1 assign aon_key_invert_ctl_gated_we = aon_key_invert_ctl_we & aon_key_invert_ctl_regwen;
Tests: T5 T18 T25
2166 // F[key0_in]: 0:0
2167 prim_subreg #(
2168 .DW (1),
2169 .SwAccess(prim_subreg_pkg::SwAccessRW),
2170 .RESVAL (1'h0),
2171 .Mubi (1'b0)
2172 ) u_key_invert_ctl_key0_in (
2173 .clk_i (clk_aon_i),
2174 .rst_ni (rst_aon_ni),
2175
2176 // from register interface
2177 .we (aon_key_invert_ctl_gated_we),
2178 .wd (aon_key_invert_ctl_wdata[0]),
2179
2180 // from internal hardware
2181 .de (1'b0),
2182 .d ('0),
2183
2184 // to internal hardware
2185 .qe (),
2186 .q (reg2hw.key_invert_ctl.key0_in.q),
2187 .ds (),
2188
2189 // to register interface (read)
2190 .qs (aon_key_invert_ctl_key0_in_qs_int)
2191 );
2192
2193 // F[key0_out]: 1:1
2194 prim_subreg #(
2195 .DW (1),
2196 .SwAccess(prim_subreg_pkg::SwAccessRW),
2197 .RESVAL (1'h0),
2198 .Mubi (1'b0)
2199 ) u_key_invert_ctl_key0_out (
2200 .clk_i (clk_aon_i),
2201 .rst_ni (rst_aon_ni),
2202
2203 // from register interface
2204 .we (aon_key_invert_ctl_gated_we),
2205 .wd (aon_key_invert_ctl_wdata[1]),
2206
2207 // from internal hardware
2208 .de (1'b0),
2209 .d ('0),
2210
2211 // to internal hardware
2212 .qe (),
2213 .q (reg2hw.key_invert_ctl.key0_out.q),
2214 .ds (),
2215
2216 // to register interface (read)
2217 .qs (aon_key_invert_ctl_key0_out_qs_int)
2218 );
2219
2220 // F[key1_in]: 2:2
2221 prim_subreg #(
2222 .DW (1),
2223 .SwAccess(prim_subreg_pkg::SwAccessRW),
2224 .RESVAL (1'h0),
2225 .Mubi (1'b0)
2226 ) u_key_invert_ctl_key1_in (
2227 .clk_i (clk_aon_i),
2228 .rst_ni (rst_aon_ni),
2229
2230 // from register interface
2231 .we (aon_key_invert_ctl_gated_we),
2232 .wd (aon_key_invert_ctl_wdata[2]),
2233
2234 // from internal hardware
2235 .de (1'b0),
2236 .d ('0),
2237
2238 // to internal hardware
2239 .qe (),
2240 .q (reg2hw.key_invert_ctl.key1_in.q),
2241 .ds (),
2242
2243 // to register interface (read)
2244 .qs (aon_key_invert_ctl_key1_in_qs_int)
2245 );
2246
2247 // F[key1_out]: 3:3
2248 prim_subreg #(
2249 .DW (1),
2250 .SwAccess(prim_subreg_pkg::SwAccessRW),
2251 .RESVAL (1'h0),
2252 .Mubi (1'b0)
2253 ) u_key_invert_ctl_key1_out (
2254 .clk_i (clk_aon_i),
2255 .rst_ni (rst_aon_ni),
2256
2257 // from register interface
2258 .we (aon_key_invert_ctl_gated_we),
2259 .wd (aon_key_invert_ctl_wdata[3]),
2260
2261 // from internal hardware
2262 .de (1'b0),
2263 .d ('0),
2264
2265 // to internal hardware
2266 .qe (),
2267 .q (reg2hw.key_invert_ctl.key1_out.q),
2268 .ds (),
2269
2270 // to register interface (read)
2271 .qs (aon_key_invert_ctl_key1_out_qs_int)
2272 );
2273
2274 // F[key2_in]: 4:4
2275 prim_subreg #(
2276 .DW (1),
2277 .SwAccess(prim_subreg_pkg::SwAccessRW),
2278 .RESVAL (1'h0),
2279 .Mubi (1'b0)
2280 ) u_key_invert_ctl_key2_in (
2281 .clk_i (clk_aon_i),
2282 .rst_ni (rst_aon_ni),
2283
2284 // from register interface
2285 .we (aon_key_invert_ctl_gated_we),
2286 .wd (aon_key_invert_ctl_wdata[4]),
2287
2288 // from internal hardware
2289 .de (1'b0),
2290 .d ('0),
2291
2292 // to internal hardware
2293 .qe (),
2294 .q (reg2hw.key_invert_ctl.key2_in.q),
2295 .ds (),
2296
2297 // to register interface (read)
2298 .qs (aon_key_invert_ctl_key2_in_qs_int)
2299 );
2300
2301 // F[key2_out]: 5:5
2302 prim_subreg #(
2303 .DW (1),
2304 .SwAccess(prim_subreg_pkg::SwAccessRW),
2305 .RESVAL (1'h0),
2306 .Mubi (1'b0)
2307 ) u_key_invert_ctl_key2_out (
2308 .clk_i (clk_aon_i),
2309 .rst_ni (rst_aon_ni),
2310
2311 // from register interface
2312 .we (aon_key_invert_ctl_gated_we),
2313 .wd (aon_key_invert_ctl_wdata[5]),
2314
2315 // from internal hardware
2316 .de (1'b0),
2317 .d ('0),
2318
2319 // to internal hardware
2320 .qe (),
2321 .q (reg2hw.key_invert_ctl.key2_out.q),
2322 .ds (),
2323
2324 // to register interface (read)
2325 .qs (aon_key_invert_ctl_key2_out_qs_int)
2326 );
2327
2328 // F[pwrb_in]: 6:6
2329 prim_subreg #(
2330 .DW (1),
2331 .SwAccess(prim_subreg_pkg::SwAccessRW),
2332 .RESVAL (1'h0),
2333 .Mubi (1'b0)
2334 ) u_key_invert_ctl_pwrb_in (
2335 .clk_i (clk_aon_i),
2336 .rst_ni (rst_aon_ni),
2337
2338 // from register interface
2339 .we (aon_key_invert_ctl_gated_we),
2340 .wd (aon_key_invert_ctl_wdata[6]),
2341
2342 // from internal hardware
2343 .de (1'b0),
2344 .d ('0),
2345
2346 // to internal hardware
2347 .qe (),
2348 .q (reg2hw.key_invert_ctl.pwrb_in.q),
2349 .ds (),
2350
2351 // to register interface (read)
2352 .qs (aon_key_invert_ctl_pwrb_in_qs_int)
2353 );
2354
2355 // F[pwrb_out]: 7:7
2356 prim_subreg #(
2357 .DW (1),
2358 .SwAccess(prim_subreg_pkg::SwAccessRW),
2359 .RESVAL (1'h0),
2360 .Mubi (1'b0)
2361 ) u_key_invert_ctl_pwrb_out (
2362 .clk_i (clk_aon_i),
2363 .rst_ni (rst_aon_ni),
2364
2365 // from register interface
2366 .we (aon_key_invert_ctl_gated_we),
2367 .wd (aon_key_invert_ctl_wdata[7]),
2368
2369 // from internal hardware
2370 .de (1'b0),
2371 .d ('0),
2372
2373 // to internal hardware
2374 .qe (),
2375 .q (reg2hw.key_invert_ctl.pwrb_out.q),
2376 .ds (),
2377
2378 // to register interface (read)
2379 .qs (aon_key_invert_ctl_pwrb_out_qs_int)
2380 );
2381
2382 // F[ac_present]: 8:8
2383 prim_subreg #(
2384 .DW (1),
2385 .SwAccess(prim_subreg_pkg::SwAccessRW),
2386 .RESVAL (1'h0),
2387 .Mubi (1'b0)
2388 ) u_key_invert_ctl_ac_present (
2389 .clk_i (clk_aon_i),
2390 .rst_ni (rst_aon_ni),
2391
2392 // from register interface
2393 .we (aon_key_invert_ctl_gated_we),
2394 .wd (aon_key_invert_ctl_wdata[8]),
2395
2396 // from internal hardware
2397 .de (1'b0),
2398 .d ('0),
2399
2400 // to internal hardware
2401 .qe (),
2402 .q (reg2hw.key_invert_ctl.ac_present.q),
2403 .ds (),
2404
2405 // to register interface (read)
2406 .qs (aon_key_invert_ctl_ac_present_qs_int)
2407 );
2408
2409 // F[bat_disable]: 9:9
2410 prim_subreg #(
2411 .DW (1),
2412 .SwAccess(prim_subreg_pkg::SwAccessRW),
2413 .RESVAL (1'h0),
2414 .Mubi (1'b0)
2415 ) u_key_invert_ctl_bat_disable (
2416 .clk_i (clk_aon_i),
2417 .rst_ni (rst_aon_ni),
2418
2419 // from register interface
2420 .we (aon_key_invert_ctl_gated_we),
2421 .wd (aon_key_invert_ctl_wdata[9]),
2422
2423 // from internal hardware
2424 .de (1'b0),
2425 .d ('0),
2426
2427 // to internal hardware
2428 .qe (),
2429 .q (reg2hw.key_invert_ctl.bat_disable.q),
2430 .ds (),
2431
2432 // to register interface (read)
2433 .qs (aon_key_invert_ctl_bat_disable_qs_int)
2434 );
2435
2436 // F[lid_open]: 10:10
2437 prim_subreg #(
2438 .DW (1),
2439 .SwAccess(prim_subreg_pkg::SwAccessRW),
2440 .RESVAL (1'h0),
2441 .Mubi (1'b0)
2442 ) u_key_invert_ctl_lid_open (
2443 .clk_i (clk_aon_i),
2444 .rst_ni (rst_aon_ni),
2445
2446 // from register interface
2447 .we (aon_key_invert_ctl_gated_we),
2448 .wd (aon_key_invert_ctl_wdata[10]),
2449
2450 // from internal hardware
2451 .de (1'b0),
2452 .d ('0),
2453
2454 // to internal hardware
2455 .qe (),
2456 .q (reg2hw.key_invert_ctl.lid_open.q),
2457 .ds (),
2458
2459 // to register interface (read)
2460 .qs (aon_key_invert_ctl_lid_open_qs_int)
2461 );
2462
2463 // F[z3_wakeup]: 11:11
2464 prim_subreg #(
2465 .DW (1),
2466 .SwAccess(prim_subreg_pkg::SwAccessRW),
2467 .RESVAL (1'h0),
2468 .Mubi (1'b0)
2469 ) u_key_invert_ctl_z3_wakeup (
2470 .clk_i (clk_aon_i),
2471 .rst_ni (rst_aon_ni),
2472
2473 // from register interface
2474 .we (aon_key_invert_ctl_gated_we),
2475 .wd (aon_key_invert_ctl_wdata[11]),
2476
2477 // from internal hardware
2478 .de (1'b0),
2479 .d ('0),
2480
2481 // to internal hardware
2482 .qe (),
2483 .q (reg2hw.key_invert_ctl.z3_wakeup.q),
2484 .ds (),
2485
2486 // to register interface (read)
2487 .qs (aon_key_invert_ctl_z3_wakeup_qs_int)
2488 );
2489
2490
2491 // R[pin_allowed_ctl]: V(False)
2492 // Create REGWEN-gated WE signal
2493 logic aon_pin_allowed_ctl_gated_we;
2494 1/1 assign aon_pin_allowed_ctl_gated_we = aon_pin_allowed_ctl_we & aon_pin_allowed_ctl_regwen;
Tests: T5 T14 T17
2495 // F[bat_disable_0]: 0:0
2496 prim_subreg #(
2497 .DW (1),
2498 .SwAccess(prim_subreg_pkg::SwAccessRW),
2499 .RESVAL (1'h0),
2500 .Mubi (1'b0)
2501 ) u_pin_allowed_ctl_bat_disable_0 (
2502 .clk_i (clk_aon_i),
2503 .rst_ni (rst_aon_ni),
2504
2505 // from register interface
2506 .we (aon_pin_allowed_ctl_gated_we),
2507 .wd (aon_pin_allowed_ctl_wdata[0]),
2508
2509 // from internal hardware
2510 .de (1'b0),
2511 .d ('0),
2512
2513 // to internal hardware
2514 .qe (),
2515 .q (reg2hw.pin_allowed_ctl.bat_disable_0.q),
2516 .ds (),
2517
2518 // to register interface (read)
2519 .qs (aon_pin_allowed_ctl_bat_disable_0_qs_int)
2520 );
2521
2522 // F[ec_rst_l_0]: 1:1
2523 prim_subreg #(
2524 .DW (1),
2525 .SwAccess(prim_subreg_pkg::SwAccessRW),
2526 .RESVAL (1'h1),
2527 .Mubi (1'b0)
2528 ) u_pin_allowed_ctl_ec_rst_l_0 (
2529 .clk_i (clk_aon_i),
2530 .rst_ni (rst_aon_ni),
2531
2532 // from register interface
2533 .we (aon_pin_allowed_ctl_gated_we),
2534 .wd (aon_pin_allowed_ctl_wdata[1]),
2535
2536 // from internal hardware
2537 .de (1'b0),
2538 .d ('0),
2539
2540 // to internal hardware
2541 .qe (),
2542 .q (reg2hw.pin_allowed_ctl.ec_rst_l_0.q),
2543 .ds (),
2544
2545 // to register interface (read)
2546 .qs (aon_pin_allowed_ctl_ec_rst_l_0_qs_int)
2547 );
2548
2549 // F[pwrb_out_0]: 2:2
2550 prim_subreg #(
2551 .DW (1),
2552 .SwAccess(prim_subreg_pkg::SwAccessRW),
2553 .RESVAL (1'h0),
2554 .Mubi (1'b0)
2555 ) u_pin_allowed_ctl_pwrb_out_0 (
2556 .clk_i (clk_aon_i),
2557 .rst_ni (rst_aon_ni),
2558
2559 // from register interface
2560 .we (aon_pin_allowed_ctl_gated_we),
2561 .wd (aon_pin_allowed_ctl_wdata[2]),
2562
2563 // from internal hardware
2564 .de (1'b0),
2565 .d ('0),
2566
2567 // to internal hardware
2568 .qe (),
2569 .q (reg2hw.pin_allowed_ctl.pwrb_out_0.q),
2570 .ds (),
2571
2572 // to register interface (read)
2573 .qs (aon_pin_allowed_ctl_pwrb_out_0_qs_int)
2574 );
2575
2576 // F[key0_out_0]: 3:3
2577 prim_subreg #(
2578 .DW (1),
2579 .SwAccess(prim_subreg_pkg::SwAccessRW),
2580 .RESVAL (1'h0),
2581 .Mubi (1'b0)
2582 ) u_pin_allowed_ctl_key0_out_0 (
2583 .clk_i (clk_aon_i),
2584 .rst_ni (rst_aon_ni),
2585
2586 // from register interface
2587 .we (aon_pin_allowed_ctl_gated_we),
2588 .wd (aon_pin_allowed_ctl_wdata[3]),
2589
2590 // from internal hardware
2591 .de (1'b0),
2592 .d ('0),
2593
2594 // to internal hardware
2595 .qe (),
2596 .q (reg2hw.pin_allowed_ctl.key0_out_0.q),
2597 .ds (),
2598
2599 // to register interface (read)
2600 .qs (aon_pin_allowed_ctl_key0_out_0_qs_int)
2601 );
2602
2603 // F[key1_out_0]: 4:4
2604 prim_subreg #(
2605 .DW (1),
2606 .SwAccess(prim_subreg_pkg::SwAccessRW),
2607 .RESVAL (1'h0),
2608 .Mubi (1'b0)
2609 ) u_pin_allowed_ctl_key1_out_0 (
2610 .clk_i (clk_aon_i),
2611 .rst_ni (rst_aon_ni),
2612
2613 // from register interface
2614 .we (aon_pin_allowed_ctl_gated_we),
2615 .wd (aon_pin_allowed_ctl_wdata[4]),
2616
2617 // from internal hardware
2618 .de (1'b0),
2619 .d ('0),
2620
2621 // to internal hardware
2622 .qe (),
2623 .q (reg2hw.pin_allowed_ctl.key1_out_0.q),
2624 .ds (),
2625
2626 // to register interface (read)
2627 .qs (aon_pin_allowed_ctl_key1_out_0_qs_int)
2628 );
2629
2630 // F[key2_out_0]: 5:5
2631 prim_subreg #(
2632 .DW (1),
2633 .SwAccess(prim_subreg_pkg::SwAccessRW),
2634 .RESVAL (1'h0),
2635 .Mubi (1'b0)
2636 ) u_pin_allowed_ctl_key2_out_0 (
2637 .clk_i (clk_aon_i),
2638 .rst_ni (rst_aon_ni),
2639
2640 // from register interface
2641 .we (aon_pin_allowed_ctl_gated_we),
2642 .wd (aon_pin_allowed_ctl_wdata[5]),
2643
2644 // from internal hardware
2645 .de (1'b0),
2646 .d ('0),
2647
2648 // to internal hardware
2649 .qe (),
2650 .q (reg2hw.pin_allowed_ctl.key2_out_0.q),
2651 .ds (),
2652
2653 // to register interface (read)
2654 .qs (aon_pin_allowed_ctl_key2_out_0_qs_int)
2655 );
2656
2657 // F[z3_wakeup_0]: 6:6
2658 prim_subreg #(
2659 .DW (1),
2660 .SwAccess(prim_subreg_pkg::SwAccessRW),
2661 .RESVAL (1'h0),
2662 .Mubi (1'b0)
2663 ) u_pin_allowed_ctl_z3_wakeup_0 (
2664 .clk_i (clk_aon_i),
2665 .rst_ni (rst_aon_ni),
2666
2667 // from register interface
2668 .we (aon_pin_allowed_ctl_gated_we),
2669 .wd (aon_pin_allowed_ctl_wdata[6]),
2670
2671 // from internal hardware
2672 .de (1'b0),
2673 .d ('0),
2674
2675 // to internal hardware
2676 .qe (),
2677 .q (reg2hw.pin_allowed_ctl.z3_wakeup_0.q),
2678 .ds (),
2679
2680 // to register interface (read)
2681 .qs (aon_pin_allowed_ctl_z3_wakeup_0_qs_int)
2682 );
2683
2684 // F[flash_wp_l_0]: 7:7
2685 prim_subreg #(
2686 .DW (1),
2687 .SwAccess(prim_subreg_pkg::SwAccessRW),
2688 .RESVAL (1'h1),
2689 .Mubi (1'b0)
2690 ) u_pin_allowed_ctl_flash_wp_l_0 (
2691 .clk_i (clk_aon_i),
2692 .rst_ni (rst_aon_ni),
2693
2694 // from register interface
2695 .we (aon_pin_allowed_ctl_gated_we),
2696 .wd (aon_pin_allowed_ctl_wdata[7]),
2697
2698 // from internal hardware
2699 .de (1'b0),
2700 .d ('0),
2701
2702 // to internal hardware
2703 .qe (),
2704 .q (reg2hw.pin_allowed_ctl.flash_wp_l_0.q),
2705 .ds (),
2706
2707 // to register interface (read)
2708 .qs (aon_pin_allowed_ctl_flash_wp_l_0_qs_int)
2709 );
2710
2711 // F[bat_disable_1]: 8:8
2712 prim_subreg #(
2713 .DW (1),
2714 .SwAccess(prim_subreg_pkg::SwAccessRW),
2715 .RESVAL (1'h0),
2716 .Mubi (1'b0)
2717 ) u_pin_allowed_ctl_bat_disable_1 (
2718 .clk_i (clk_aon_i),
2719 .rst_ni (rst_aon_ni),
2720
2721 // from register interface
2722 .we (aon_pin_allowed_ctl_gated_we),
2723 .wd (aon_pin_allowed_ctl_wdata[8]),
2724
2725 // from internal hardware
2726 .de (1'b0),
2727 .d ('0),
2728
2729 // to internal hardware
2730 .qe (),
2731 .q (reg2hw.pin_allowed_ctl.bat_disable_1.q),
2732 .ds (),
2733
2734 // to register interface (read)
2735 .qs (aon_pin_allowed_ctl_bat_disable_1_qs_int)
2736 );
2737
2738 // F[ec_rst_l_1]: 9:9
2739 prim_subreg #(
2740 .DW (1),
2741 .SwAccess(prim_subreg_pkg::SwAccessRW),
2742 .RESVAL (1'h0),
2743 .Mubi (1'b0)
2744 ) u_pin_allowed_ctl_ec_rst_l_1 (
2745 .clk_i (clk_aon_i),
2746 .rst_ni (rst_aon_ni),
2747
2748 // from register interface
2749 .we (aon_pin_allowed_ctl_gated_we),
2750 .wd (aon_pin_allowed_ctl_wdata[9]),
2751
2752 // from internal hardware
2753 .de (1'b0),
2754 .d ('0),
2755
2756 // to internal hardware
2757 .qe (),
2758 .q (reg2hw.pin_allowed_ctl.ec_rst_l_1.q),
2759 .ds (),
2760
2761 // to register interface (read)
2762 .qs (aon_pin_allowed_ctl_ec_rst_l_1_qs_int)
2763 );
2764
2765 // F[pwrb_out_1]: 10:10
2766 prim_subreg #(
2767 .DW (1),
2768 .SwAccess(prim_subreg_pkg::SwAccessRW),
2769 .RESVAL (1'h0),
2770 .Mubi (1'b0)
2771 ) u_pin_allowed_ctl_pwrb_out_1 (
2772 .clk_i (clk_aon_i),
2773 .rst_ni (rst_aon_ni),
2774
2775 // from register interface
2776 .we (aon_pin_allowed_ctl_gated_we),
2777 .wd (aon_pin_allowed_ctl_wdata[10]),
2778
2779 // from internal hardware
2780 .de (1'b0),
2781 .d ('0),
2782
2783 // to internal hardware
2784 .qe (),
2785 .q (reg2hw.pin_allowed_ctl.pwrb_out_1.q),
2786 .ds (),
2787
2788 // to register interface (read)
2789 .qs (aon_pin_allowed_ctl_pwrb_out_1_qs_int)
2790 );
2791
2792 // F[key0_out_1]: 11:11
2793 prim_subreg #(
2794 .DW (1),
2795 .SwAccess(prim_subreg_pkg::SwAccessRW),
2796 .RESVAL (1'h0),
2797 .Mubi (1'b0)
2798 ) u_pin_allowed_ctl_key0_out_1 (
2799 .clk_i (clk_aon_i),
2800 .rst_ni (rst_aon_ni),
2801
2802 // from register interface
2803 .we (aon_pin_allowed_ctl_gated_we),
2804 .wd (aon_pin_allowed_ctl_wdata[11]),
2805
2806 // from internal hardware
2807 .de (1'b0),
2808 .d ('0),
2809
2810 // to internal hardware
2811 .qe (),
2812 .q (reg2hw.pin_allowed_ctl.key0_out_1.q),
2813 .ds (),
2814
2815 // to register interface (read)
2816 .qs (aon_pin_allowed_ctl_key0_out_1_qs_int)
2817 );
2818
2819 // F[key1_out_1]: 12:12
2820 prim_subreg #(
2821 .DW (1),
2822 .SwAccess(prim_subreg_pkg::SwAccessRW),
2823 .RESVAL (1'h0),
2824 .Mubi (1'b0)
2825 ) u_pin_allowed_ctl_key1_out_1 (
2826 .clk_i (clk_aon_i),
2827 .rst_ni (rst_aon_ni),
2828
2829 // from register interface
2830 .we (aon_pin_allowed_ctl_gated_we),
2831 .wd (aon_pin_allowed_ctl_wdata[12]),
2832
2833 // from internal hardware
2834 .de (1'b0),
2835 .d ('0),
2836
2837 // to internal hardware
2838 .qe (),
2839 .q (reg2hw.pin_allowed_ctl.key1_out_1.q),
2840 .ds (),
2841
2842 // to register interface (read)
2843 .qs (aon_pin_allowed_ctl_key1_out_1_qs_int)
2844 );
2845
2846 // F[key2_out_1]: 13:13
2847 prim_subreg #(
2848 .DW (1),
2849 .SwAccess(prim_subreg_pkg::SwAccessRW),
2850 .RESVAL (1'h0),
2851 .Mubi (1'b0)
2852 ) u_pin_allowed_ctl_key2_out_1 (
2853 .clk_i (clk_aon_i),
2854 .rst_ni (rst_aon_ni),
2855
2856 // from register interface
2857 .we (aon_pin_allowed_ctl_gated_we),
2858 .wd (aon_pin_allowed_ctl_wdata[13]),
2859
2860 // from internal hardware
2861 .de (1'b0),
2862 .d ('0),
2863
2864 // to internal hardware
2865 .qe (),
2866 .q (reg2hw.pin_allowed_ctl.key2_out_1.q),
2867 .ds (),
2868
2869 // to register interface (read)
2870 .qs (aon_pin_allowed_ctl_key2_out_1_qs_int)
2871 );
2872
2873 // F[z3_wakeup_1]: 14:14
2874 prim_subreg #(
2875 .DW (1),
2876 .SwAccess(prim_subreg_pkg::SwAccessRW),
2877 .RESVAL (1'h0),
2878 .Mubi (1'b0)
2879 ) u_pin_allowed_ctl_z3_wakeup_1 (
2880 .clk_i (clk_aon_i),
2881 .rst_ni (rst_aon_ni),
2882
2883 // from register interface
2884 .we (aon_pin_allowed_ctl_gated_we),
2885 .wd (aon_pin_allowed_ctl_wdata[14]),
2886
2887 // from internal hardware
2888 .de (1'b0),
2889 .d ('0),
2890
2891 // to internal hardware
2892 .qe (),
2893 .q (reg2hw.pin_allowed_ctl.z3_wakeup_1.q),
2894 .ds (),
2895
2896 // to register interface (read)
2897 .qs (aon_pin_allowed_ctl_z3_wakeup_1_qs_int)
2898 );
2899
2900 // F[flash_wp_l_1]: 15:15
2901 prim_subreg #(
2902 .DW (1),
2903 .SwAccess(prim_subreg_pkg::SwAccessRW),
2904 .RESVAL (1'h0),
2905 .Mubi (1'b0)
2906 ) u_pin_allowed_ctl_flash_wp_l_1 (
2907 .clk_i (clk_aon_i),
2908 .rst_ni (rst_aon_ni),
2909
2910 // from register interface
2911 .we (aon_pin_allowed_ctl_gated_we),
2912 .wd (aon_pin_allowed_ctl_wdata[15]),
2913
2914 // from internal hardware
2915 .de (1'b0),
2916 .d ('0),
2917
2918 // to internal hardware
2919 .qe (),
2920 .q (reg2hw.pin_allowed_ctl.flash_wp_l_1.q),
2921 .ds (),
2922
2923 // to register interface (read)
2924 .qs (aon_pin_allowed_ctl_flash_wp_l_1_qs_int)
2925 );
2926
2927
2928 // R[pin_out_ctl]: V(False)
2929 // F[bat_disable]: 0:0
2930 prim_subreg #(
2931 .DW (1),
2932 .SwAccess(prim_subreg_pkg::SwAccessRW),
2933 .RESVAL (1'h0),
2934 .Mubi (1'b0)
2935 ) u_pin_out_ctl_bat_disable (
2936 .clk_i (clk_aon_i),
2937 .rst_ni (rst_aon_ni),
2938
2939 // from register interface
2940 .we (aon_pin_out_ctl_we),
2941 .wd (aon_pin_out_ctl_wdata[0]),
2942
2943 // from internal hardware
2944 .de (1'b0),
2945 .d ('0),
2946
2947 // to internal hardware
2948 .qe (),
2949 .q (reg2hw.pin_out_ctl.bat_disable.q),
2950 .ds (),
2951
2952 // to register interface (read)
2953 .qs (aon_pin_out_ctl_bat_disable_qs_int)
2954 );
2955
2956 // F[ec_rst_l]: 1:1
2957 prim_subreg #(
2958 .DW (1),
2959 .SwAccess(prim_subreg_pkg::SwAccessRW),
2960 .RESVAL (1'h1),
2961 .Mubi (1'b0)
2962 ) u_pin_out_ctl_ec_rst_l (
2963 .clk_i (clk_aon_i),
2964 .rst_ni (rst_aon_ni),
2965
2966 // from register interface
2967 .we (aon_pin_out_ctl_we),
2968 .wd (aon_pin_out_ctl_wdata[1]),
2969
2970 // from internal hardware
2971 .de (1'b0),
2972 .d ('0),
2973
2974 // to internal hardware
2975 .qe (),
2976 .q (reg2hw.pin_out_ctl.ec_rst_l.q),
2977 .ds (),
2978
2979 // to register interface (read)
2980 .qs (aon_pin_out_ctl_ec_rst_l_qs_int)
2981 );
2982
2983 // F[pwrb_out]: 2:2
2984 prim_subreg #(
2985 .DW (1),
2986 .SwAccess(prim_subreg_pkg::SwAccessRW),
2987 .RESVAL (1'h0),
2988 .Mubi (1'b0)
2989 ) u_pin_out_ctl_pwrb_out (
2990 .clk_i (clk_aon_i),
2991 .rst_ni (rst_aon_ni),
2992
2993 // from register interface
2994 .we (aon_pin_out_ctl_we),
2995 .wd (aon_pin_out_ctl_wdata[2]),
2996
2997 // from internal hardware
2998 .de (1'b0),
2999 .d ('0),
3000
3001 // to internal hardware
3002 .qe (),
3003 .q (reg2hw.pin_out_ctl.pwrb_out.q),
3004 .ds (),
3005
3006 // to register interface (read)
3007 .qs (aon_pin_out_ctl_pwrb_out_qs_int)
3008 );
3009
3010 // F[key0_out]: 3:3
3011 prim_subreg #(
3012 .DW (1),
3013 .SwAccess(prim_subreg_pkg::SwAccessRW),
3014 .RESVAL (1'h0),
3015 .Mubi (1'b0)
3016 ) u_pin_out_ctl_key0_out (
3017 .clk_i (clk_aon_i),
3018 .rst_ni (rst_aon_ni),
3019
3020 // from register interface
3021 .we (aon_pin_out_ctl_we),
3022 .wd (aon_pin_out_ctl_wdata[3]),
3023
3024 // from internal hardware
3025 .de (1'b0),
3026 .d ('0),
3027
3028 // to internal hardware
3029 .qe (),
3030 .q (reg2hw.pin_out_ctl.key0_out.q),
3031 .ds (),
3032
3033 // to register interface (read)
3034 .qs (aon_pin_out_ctl_key0_out_qs_int)
3035 );
3036
3037 // F[key1_out]: 4:4
3038 prim_subreg #(
3039 .DW (1),
3040 .SwAccess(prim_subreg_pkg::SwAccessRW),
3041 .RESVAL (1'h0),
3042 .Mubi (1'b0)
3043 ) u_pin_out_ctl_key1_out (
3044 .clk_i (clk_aon_i),
3045 .rst_ni (rst_aon_ni),
3046
3047 // from register interface
3048 .we (aon_pin_out_ctl_we),
3049 .wd (aon_pin_out_ctl_wdata[4]),
3050
3051 // from internal hardware
3052 .de (1'b0),
3053 .d ('0),
3054
3055 // to internal hardware
3056 .qe (),
3057 .q (reg2hw.pin_out_ctl.key1_out.q),
3058 .ds (),
3059
3060 // to register interface (read)
3061 .qs (aon_pin_out_ctl_key1_out_qs_int)
3062 );
3063
3064 // F[key2_out]: 5:5
3065 prim_subreg #(
3066 .DW (1),
3067 .SwAccess(prim_subreg_pkg::SwAccessRW),
3068 .RESVAL (1'h0),
3069 .Mubi (1'b0)
3070 ) u_pin_out_ctl_key2_out (
3071 .clk_i (clk_aon_i),
3072 .rst_ni (rst_aon_ni),
3073
3074 // from register interface
3075 .we (aon_pin_out_ctl_we),
3076 .wd (aon_pin_out_ctl_wdata[5]),
3077
3078 // from internal hardware
3079 .de (1'b0),
3080 .d ('0),
3081
3082 // to internal hardware
3083 .qe (),
3084 .q (reg2hw.pin_out_ctl.key2_out.q),
3085 .ds (),
3086
3087 // to register interface (read)
3088 .qs (aon_pin_out_ctl_key2_out_qs_int)
3089 );
3090
3091 // F[z3_wakeup]: 6:6
3092 prim_subreg #(
3093 .DW (1),
3094 .SwAccess(prim_subreg_pkg::SwAccessRW),
3095 .RESVAL (1'h0),
3096 .Mubi (1'b0)
3097 ) u_pin_out_ctl_z3_wakeup (
3098 .clk_i (clk_aon_i),
3099 .rst_ni (rst_aon_ni),
3100
3101 // from register interface
3102 .we (aon_pin_out_ctl_we),
3103 .wd (aon_pin_out_ctl_wdata[6]),
3104
3105 // from internal hardware
3106 .de (1'b0),
3107 .d ('0),
3108
3109 // to internal hardware
3110 .qe (),
3111 .q (reg2hw.pin_out_ctl.z3_wakeup.q),
3112 .ds (),
3113
3114 // to register interface (read)
3115 .qs (aon_pin_out_ctl_z3_wakeup_qs_int)
3116 );
3117
3118 // F[flash_wp_l]: 7:7
3119 prim_subreg #(
3120 .DW (1),
3121 .SwAccess(prim_subreg_pkg::SwAccessRW),
3122 .RESVAL (1'h1),
3123 .Mubi (1'b0)
3124 ) u_pin_out_ctl_flash_wp_l (
3125 .clk_i (clk_aon_i),
3126 .rst_ni (rst_aon_ni),
3127
3128 // from register interface
3129 .we (aon_pin_out_ctl_we),
3130 .wd (aon_pin_out_ctl_wdata[7]),
3131
3132 // from internal hardware
3133 .de (1'b0),
3134 .d ('0),
3135
3136 // to internal hardware
3137 .qe (),
3138 .q (reg2hw.pin_out_ctl.flash_wp_l.q),
3139 .ds (),
3140
3141 // to register interface (read)
3142 .qs (aon_pin_out_ctl_flash_wp_l_qs_int)
3143 );
3144
3145
3146 // R[pin_out_value]: V(False)
3147 // F[bat_disable]: 0:0
3148 prim_subreg #(
3149 .DW (1),
3150 .SwAccess(prim_subreg_pkg::SwAccessRW),
3151 .RESVAL (1'h0),
3152 .Mubi (1'b0)
3153 ) u_pin_out_value_bat_disable (
3154 .clk_i (clk_aon_i),
3155 .rst_ni (rst_aon_ni),
3156
3157 // from register interface
3158 .we (aon_pin_out_value_we),
3159 .wd (aon_pin_out_value_wdata[0]),
3160
3161 // from internal hardware
3162 .de (1'b0),
3163 .d ('0),
3164
3165 // to internal hardware
3166 .qe (),
3167 .q (reg2hw.pin_out_value.bat_disable.q),
3168 .ds (),
3169
3170 // to register interface (read)
3171 .qs (aon_pin_out_value_bat_disable_qs_int)
3172 );
3173
3174 // F[ec_rst_l]: 1:1
3175 prim_subreg #(
3176 .DW (1),
3177 .SwAccess(prim_subreg_pkg::SwAccessRW),
3178 .RESVAL (1'h0),
3179 .Mubi (1'b0)
3180 ) u_pin_out_value_ec_rst_l (
3181 .clk_i (clk_aon_i),
3182 .rst_ni (rst_aon_ni),
3183
3184 // from register interface
3185 .we (aon_pin_out_value_we),
3186 .wd (aon_pin_out_value_wdata[1]),
3187
3188 // from internal hardware
3189 .de (1'b0),
3190 .d ('0),
3191
3192 // to internal hardware
3193 .qe (),
3194 .q (reg2hw.pin_out_value.ec_rst_l.q),
3195 .ds (),
3196
3197 // to register interface (read)
3198 .qs (aon_pin_out_value_ec_rst_l_qs_int)
3199 );
3200
3201 // F[pwrb_out]: 2:2
3202 prim_subreg #(
3203 .DW (1),
3204 .SwAccess(prim_subreg_pkg::SwAccessRW),
3205 .RESVAL (1'h0),
3206 .Mubi (1'b0)
3207 ) u_pin_out_value_pwrb_out (
3208 .clk_i (clk_aon_i),
3209 .rst_ni (rst_aon_ni),
3210
3211 // from register interface
3212 .we (aon_pin_out_value_we),
3213 .wd (aon_pin_out_value_wdata[2]),
3214
3215 // from internal hardware
3216 .de (1'b0),
3217 .d ('0),
3218
3219 // to internal hardware
3220 .qe (),
3221 .q (reg2hw.pin_out_value.pwrb_out.q),
3222 .ds (),
3223
3224 // to register interface (read)
3225 .qs (aon_pin_out_value_pwrb_out_qs_int)
3226 );
3227
3228 // F[key0_out]: 3:3
3229 prim_subreg #(
3230 .DW (1),
3231 .SwAccess(prim_subreg_pkg::SwAccessRW),
3232 .RESVAL (1'h0),
3233 .Mubi (1'b0)
3234 ) u_pin_out_value_key0_out (
3235 .clk_i (clk_aon_i),
3236 .rst_ni (rst_aon_ni),
3237
3238 // from register interface
3239 .we (aon_pin_out_value_we),
3240 .wd (aon_pin_out_value_wdata[3]),
3241
3242 // from internal hardware
3243 .de (1'b0),
3244 .d ('0),
3245
3246 // to internal hardware
3247 .qe (),
3248 .q (reg2hw.pin_out_value.key0_out.q),
3249 .ds (),
3250
3251 // to register interface (read)
3252 .qs (aon_pin_out_value_key0_out_qs_int)
3253 );
3254
3255 // F[key1_out]: 4:4
3256 prim_subreg #(
3257 .DW (1),
3258 .SwAccess(prim_subreg_pkg::SwAccessRW),
3259 .RESVAL (1'h0),
3260 .Mubi (1'b0)
3261 ) u_pin_out_value_key1_out (
3262 .clk_i (clk_aon_i),
3263 .rst_ni (rst_aon_ni),
3264
3265 // from register interface
3266 .we (aon_pin_out_value_we),
3267 .wd (aon_pin_out_value_wdata[4]),
3268
3269 // from internal hardware
3270 .de (1'b0),
3271 .d ('0),
3272
3273 // to internal hardware
3274 .qe (),
3275 .q (reg2hw.pin_out_value.key1_out.q),
3276 .ds (),
3277
3278 // to register interface (read)
3279 .qs (aon_pin_out_value_key1_out_qs_int)
3280 );
3281
3282 // F[key2_out]: 5:5
3283 prim_subreg #(
3284 .DW (1),
3285 .SwAccess(prim_subreg_pkg::SwAccessRW),
3286 .RESVAL (1'h0),
3287 .Mubi (1'b0)
3288 ) u_pin_out_value_key2_out (
3289 .clk_i (clk_aon_i),
3290 .rst_ni (rst_aon_ni),
3291
3292 // from register interface
3293 .we (aon_pin_out_value_we),
3294 .wd (aon_pin_out_value_wdata[5]),
3295
3296 // from internal hardware
3297 .de (1'b0),
3298 .d ('0),
3299
3300 // to internal hardware
3301 .qe (),
3302 .q (reg2hw.pin_out_value.key2_out.q),
3303 .ds (),
3304
3305 // to register interface (read)
3306 .qs (aon_pin_out_value_key2_out_qs_int)
3307 );
3308
3309 // F[z3_wakeup]: 6:6
3310 prim_subreg #(
3311 .DW (1),
3312 .SwAccess(prim_subreg_pkg::SwAccessRW),
3313 .RESVAL (1'h0),
3314 .Mubi (1'b0)
3315 ) u_pin_out_value_z3_wakeup (
3316 .clk_i (clk_aon_i),
3317 .rst_ni (rst_aon_ni),
3318
3319 // from register interface
3320 .we (aon_pin_out_value_we),
3321 .wd (aon_pin_out_value_wdata[6]),
3322
3323 // from internal hardware
3324 .de (1'b0),
3325 .d ('0),
3326
3327 // to internal hardware
3328 .qe (),
3329 .q (reg2hw.pin_out_value.z3_wakeup.q),
3330 .ds (),
3331
3332 // to register interface (read)
3333 .qs (aon_pin_out_value_z3_wakeup_qs_int)
3334 );
3335
3336 // F[flash_wp_l]: 7:7
3337 prim_subreg #(
3338 .DW (1),
3339 .SwAccess(prim_subreg_pkg::SwAccessRW),
3340 .RESVAL (1'h0),
3341 .Mubi (1'b0)
3342 ) u_pin_out_value_flash_wp_l (
3343 .clk_i (clk_aon_i),
3344 .rst_ni (rst_aon_ni),
3345
3346 // from register interface
3347 .we (aon_pin_out_value_we),
3348 .wd (aon_pin_out_value_wdata[7]),
3349
3350 // from internal hardware
3351 .de (1'b0),
3352 .d ('0),
3353
3354 // to internal hardware
3355 .qe (),
3356 .q (reg2hw.pin_out_value.flash_wp_l.q),
3357 .ds (),
3358
3359 // to register interface (read)
3360 .qs (aon_pin_out_value_flash_wp_l_qs_int)
3361 );
3362
3363
3364 // R[pin_in_value]: V(False)
3365 // F[pwrb_in]: 0:0
3366 prim_subreg #(
3367 .DW (1),
3368 .SwAccess(prim_subreg_pkg::SwAccessRO),
3369 .RESVAL (1'h0),
3370 .Mubi (1'b0)
3371 ) u_pin_in_value_pwrb_in (
3372 .clk_i (clk_i),
3373 .rst_ni (rst_ni),
3374
3375 // from register interface
3376 .we (1'b0),
3377 .wd ('0),
3378
3379 // from internal hardware
3380 .de (hw2reg.pin_in_value.pwrb_in.de),
3381 .d (hw2reg.pin_in_value.pwrb_in.d),
3382
3383 // to internal hardware
3384 .qe (),
3385 .q (),
3386 .ds (),
3387
3388 // to register interface (read)
3389 .qs (pin_in_value_pwrb_in_qs)
3390 );
3391
3392 // F[key0_in]: 1:1
3393 prim_subreg #(
3394 .DW (1),
3395 .SwAccess(prim_subreg_pkg::SwAccessRO),
3396 .RESVAL (1'h0),
3397 .Mubi (1'b0)
3398 ) u_pin_in_value_key0_in (
3399 .clk_i (clk_i),
3400 .rst_ni (rst_ni),
3401
3402 // from register interface
3403 .we (1'b0),
3404 .wd ('0),
3405
3406 // from internal hardware
3407 .de (hw2reg.pin_in_value.key0_in.de),
3408 .d (hw2reg.pin_in_value.key0_in.d),
3409
3410 // to internal hardware
3411 .qe (),
3412 .q (),
3413 .ds (),
3414
3415 // to register interface (read)
3416 .qs (pin_in_value_key0_in_qs)
3417 );
3418
3419 // F[key1_in]: 2:2
3420 prim_subreg #(
3421 .DW (1),
3422 .SwAccess(prim_subreg_pkg::SwAccessRO),
3423 .RESVAL (1'h0),
3424 .Mubi (1'b0)
3425 ) u_pin_in_value_key1_in (
3426 .clk_i (clk_i),
3427 .rst_ni (rst_ni),
3428
3429 // from register interface
3430 .we (1'b0),
3431 .wd ('0),
3432
3433 // from internal hardware
3434 .de (hw2reg.pin_in_value.key1_in.de),
3435 .d (hw2reg.pin_in_value.key1_in.d),
3436
3437 // to internal hardware
3438 .qe (),
3439 .q (),
3440 .ds (),
3441
3442 // to register interface (read)
3443 .qs (pin_in_value_key1_in_qs)
3444 );
3445
3446 // F[key2_in]: 3:3
3447 prim_subreg #(
3448 .DW (1),
3449 .SwAccess(prim_subreg_pkg::SwAccessRO),
3450 .RESVAL (1'h0),
3451 .Mubi (1'b0)
3452 ) u_pin_in_value_key2_in (
3453 .clk_i (clk_i),
3454 .rst_ni (rst_ni),
3455
3456 // from register interface
3457 .we (1'b0),
3458 .wd ('0),
3459
3460 // from internal hardware
3461 .de (hw2reg.pin_in_value.key2_in.de),
3462 .d (hw2reg.pin_in_value.key2_in.d),
3463
3464 // to internal hardware
3465 .qe (),
3466 .q (),
3467 .ds (),
3468
3469 // to register interface (read)
3470 .qs (pin_in_value_key2_in_qs)
3471 );
3472
3473 // F[lid_open]: 4:4
3474 prim_subreg #(
3475 .DW (1),
3476 .SwAccess(prim_subreg_pkg::SwAccessRO),
3477 .RESVAL (1'h0),
3478 .Mubi (1'b0)
3479 ) u_pin_in_value_lid_open (
3480 .clk_i (clk_i),
3481 .rst_ni (rst_ni),
3482
3483 // from register interface
3484 .we (1'b0),
3485 .wd ('0),
3486
3487 // from internal hardware
3488 .de (hw2reg.pin_in_value.lid_open.de),
3489 .d (hw2reg.pin_in_value.lid_open.d),
3490
3491 // to internal hardware
3492 .qe (),
3493 .q (),
3494 .ds (),
3495
3496 // to register interface (read)
3497 .qs (pin_in_value_lid_open_qs)
3498 );
3499
3500 // F[ac_present]: 5:5
3501 prim_subreg #(
3502 .DW (1),
3503 .SwAccess(prim_subreg_pkg::SwAccessRO),
3504 .RESVAL (1'h0),
3505 .Mubi (1'b0)
3506 ) u_pin_in_value_ac_present (
3507 .clk_i (clk_i),
3508 .rst_ni (rst_ni),
3509
3510 // from register interface
3511 .we (1'b0),
3512 .wd ('0),
3513
3514 // from internal hardware
3515 .de (hw2reg.pin_in_value.ac_present.de),
3516 .d (hw2reg.pin_in_value.ac_present.d),
3517
3518 // to internal hardware
3519 .qe (),
3520 .q (),
3521 .ds (),
3522
3523 // to register interface (read)
3524 .qs (pin_in_value_ac_present_qs)
3525 );
3526
3527 // F[ec_rst_l]: 6:6
3528 prim_subreg #(
3529 .DW (1),
3530 .SwAccess(prim_subreg_pkg::SwAccessRO),
3531 .RESVAL (1'h0),
3532 .Mubi (1'b0)
3533 ) u_pin_in_value_ec_rst_l (
3534 .clk_i (clk_i),
3535 .rst_ni (rst_ni),
3536
3537 // from register interface
3538 .we (1'b0),
3539 .wd ('0),
3540
3541 // from internal hardware
3542 .de (hw2reg.pin_in_value.ec_rst_l.de),
3543 .d (hw2reg.pin_in_value.ec_rst_l.d),
3544
3545 // to internal hardware
3546 .qe (),
3547 .q (),
3548 .ds (),
3549
3550 // to register interface (read)
3551 .qs (pin_in_value_ec_rst_l_qs)
3552 );
3553
3554 // F[flash_wp_l]: 7:7
3555 prim_subreg #(
3556 .DW (1),
3557 .SwAccess(prim_subreg_pkg::SwAccessRO),
3558 .RESVAL (1'h0),
3559 .Mubi (1'b0)
3560 ) u_pin_in_value_flash_wp_l (
3561 .clk_i (clk_i),
3562 .rst_ni (rst_ni),
3563
3564 // from register interface
3565 .we (1'b0),
3566 .wd ('0),
3567
3568 // from internal hardware
3569 .de (hw2reg.pin_in_value.flash_wp_l.de),
3570 .d (hw2reg.pin_in_value.flash_wp_l.d),
3571
3572 // to internal hardware
3573 .qe (),
3574 .q (),
3575 .ds (),
3576
3577 // to register interface (read)
3578 .qs (pin_in_value_flash_wp_l_qs)
3579 );
3580
3581
3582 // R[key_intr_ctl]: V(False)
3583 // Create REGWEN-gated WE signal
3584 logic aon_key_intr_ctl_gated_we;
3585 1/1 assign aon_key_intr_ctl_gated_we = aon_key_intr_ctl_we & aon_key_intr_ctl_regwen;
Tests: T3 T7 T11
3586 // F[pwrb_in_h2l]: 0:0
3587 prim_subreg #(
3588 .DW (1),
3589 .SwAccess(prim_subreg_pkg::SwAccessRW),
3590 .RESVAL (1'h0),
3591 .Mubi (1'b0)
3592 ) u_key_intr_ctl_pwrb_in_h2l (
3593 .clk_i (clk_aon_i),
3594 .rst_ni (rst_aon_ni),
3595
3596 // from register interface
3597 .we (aon_key_intr_ctl_gated_we),
3598 .wd (aon_key_intr_ctl_wdata[0]),
3599
3600 // from internal hardware
3601 .de (1'b0),
3602 .d ('0),
3603
3604 // to internal hardware
3605 .qe (),
3606 .q (reg2hw.key_intr_ctl.pwrb_in_h2l.q),
3607 .ds (),
3608
3609 // to register interface (read)
3610 .qs (aon_key_intr_ctl_pwrb_in_h2l_qs_int)
3611 );
3612
3613 // F[key0_in_h2l]: 1:1
3614 prim_subreg #(
3615 .DW (1),
3616 .SwAccess(prim_subreg_pkg::SwAccessRW),
3617 .RESVAL (1'h0),
3618 .Mubi (1'b0)
3619 ) u_key_intr_ctl_key0_in_h2l (
3620 .clk_i (clk_aon_i),
3621 .rst_ni (rst_aon_ni),
3622
3623 // from register interface
3624 .we (aon_key_intr_ctl_gated_we),
3625 .wd (aon_key_intr_ctl_wdata[1]),
3626
3627 // from internal hardware
3628 .de (1'b0),
3629 .d ('0),
3630
3631 // to internal hardware
3632 .qe (),
3633 .q (reg2hw.key_intr_ctl.key0_in_h2l.q),
3634 .ds (),
3635
3636 // to register interface (read)
3637 .qs (aon_key_intr_ctl_key0_in_h2l_qs_int)
3638 );
3639
3640 // F[key1_in_h2l]: 2:2
3641 prim_subreg #(
3642 .DW (1),
3643 .SwAccess(prim_subreg_pkg::SwAccessRW),
3644 .RESVAL (1'h0),
3645 .Mubi (1'b0)
3646 ) u_key_intr_ctl_key1_in_h2l (
3647 .clk_i (clk_aon_i),
3648 .rst_ni (rst_aon_ni),
3649
3650 // from register interface
3651 .we (aon_key_intr_ctl_gated_we),
3652 .wd (aon_key_intr_ctl_wdata[2]),
3653
3654 // from internal hardware
3655 .de (1'b0),
3656 .d ('0),
3657
3658 // to internal hardware
3659 .qe (),
3660 .q (reg2hw.key_intr_ctl.key1_in_h2l.q),
3661 .ds (),
3662
3663 // to register interface (read)
3664 .qs (aon_key_intr_ctl_key1_in_h2l_qs_int)
3665 );
3666
3667 // F[key2_in_h2l]: 3:3
3668 prim_subreg #(
3669 .DW (1),
3670 .SwAccess(prim_subreg_pkg::SwAccessRW),
3671 .RESVAL (1'h0),
3672 .Mubi (1'b0)
3673 ) u_key_intr_ctl_key2_in_h2l (
3674 .clk_i (clk_aon_i),
3675 .rst_ni (rst_aon_ni),
3676
3677 // from register interface
3678 .we (aon_key_intr_ctl_gated_we),
3679 .wd (aon_key_intr_ctl_wdata[3]),
3680
3681 // from internal hardware
3682 .de (1'b0),
3683 .d ('0),
3684
3685 // to internal hardware
3686 .qe (),
3687 .q (reg2hw.key_intr_ctl.key2_in_h2l.q),
3688 .ds (),
3689
3690 // to register interface (read)
3691 .qs (aon_key_intr_ctl_key2_in_h2l_qs_int)
3692 );
3693
3694 // F[ac_present_h2l]: 4:4
3695 prim_subreg #(
3696 .DW (1),
3697 .SwAccess(prim_subreg_pkg::SwAccessRW),
3698 .RESVAL (1'h0),
3699 .Mubi (1'b0)
3700 ) u_key_intr_ctl_ac_present_h2l (
3701 .clk_i (clk_aon_i),
3702 .rst_ni (rst_aon_ni),
3703
3704 // from register interface
3705 .we (aon_key_intr_ctl_gated_we),
3706 .wd (aon_key_intr_ctl_wdata[4]),
3707
3708 // from internal hardware
3709 .de (1'b0),
3710 .d ('0),
3711
3712 // to internal hardware
3713 .qe (),
3714 .q (reg2hw.key_intr_ctl.ac_present_h2l.q),
3715 .ds (),
3716
3717 // to register interface (read)
3718 .qs (aon_key_intr_ctl_ac_present_h2l_qs_int)
3719 );
3720
3721 // F[ec_rst_l_h2l]: 5:5
3722 prim_subreg #(
3723 .DW (1),
3724 .SwAccess(prim_subreg_pkg::SwAccessRW),
3725 .RESVAL (1'h0),
3726 .Mubi (1'b0)
3727 ) u_key_intr_ctl_ec_rst_l_h2l (
3728 .clk_i (clk_aon_i),
3729 .rst_ni (rst_aon_ni),
3730
3731 // from register interface
3732 .we (aon_key_intr_ctl_gated_we),
3733 .wd (aon_key_intr_ctl_wdata[5]),
3734
3735 // from internal hardware
3736 .de (1'b0),
3737 .d ('0),
3738
3739 // to internal hardware
3740 .qe (),
3741 .q (reg2hw.key_intr_ctl.ec_rst_l_h2l.q),
3742 .ds (),
3743
3744 // to register interface (read)
3745 .qs (aon_key_intr_ctl_ec_rst_l_h2l_qs_int)
3746 );
3747
3748 // F[flash_wp_l_h2l]: 6:6
3749 prim_subreg #(
3750 .DW (1),
3751 .SwAccess(prim_subreg_pkg::SwAccessRW),
3752 .RESVAL (1'h0),
3753 .Mubi (1'b0)
3754 ) u_key_intr_ctl_flash_wp_l_h2l (
3755 .clk_i (clk_aon_i),
3756 .rst_ni (rst_aon_ni),
3757
3758 // from register interface
3759 .we (aon_key_intr_ctl_gated_we),
3760 .wd (aon_key_intr_ctl_wdata[6]),
3761
3762 // from internal hardware
3763 .de (1'b0),
3764 .d ('0),
3765
3766 // to internal hardware
3767 .qe (),
3768 .q (reg2hw.key_intr_ctl.flash_wp_l_h2l.q),
3769 .ds (),
3770
3771 // to register interface (read)
3772 .qs (aon_key_intr_ctl_flash_wp_l_h2l_qs_int)
3773 );
3774
3775 // F[pwrb_in_l2h]: 7:7
3776 prim_subreg #(
3777 .DW (1),
3778 .SwAccess(prim_subreg_pkg::SwAccessRW),
3779 .RESVAL (1'h0),
3780 .Mubi (1'b0)
3781 ) u_key_intr_ctl_pwrb_in_l2h (
3782 .clk_i (clk_aon_i),
3783 .rst_ni (rst_aon_ni),
3784
3785 // from register interface
3786 .we (aon_key_intr_ctl_gated_we),
3787 .wd (aon_key_intr_ctl_wdata[7]),
3788
3789 // from internal hardware
3790 .de (1'b0),
3791 .d ('0),
3792
3793 // to internal hardware
3794 .qe (),
3795 .q (reg2hw.key_intr_ctl.pwrb_in_l2h.q),
3796 .ds (),
3797
3798 // to register interface (read)
3799 .qs (aon_key_intr_ctl_pwrb_in_l2h_qs_int)
3800 );
3801
3802 // F[key0_in_l2h]: 8:8
3803 prim_subreg #(
3804 .DW (1),
3805 .SwAccess(prim_subreg_pkg::SwAccessRW),
3806 .RESVAL (1'h0),
3807 .Mubi (1'b0)
3808 ) u_key_intr_ctl_key0_in_l2h (
3809 .clk_i (clk_aon_i),
3810 .rst_ni (rst_aon_ni),
3811
3812 // from register interface
3813 .we (aon_key_intr_ctl_gated_we),
3814 .wd (aon_key_intr_ctl_wdata[8]),
3815
3816 // from internal hardware
3817 .de (1'b0),
3818 .d ('0),
3819
3820 // to internal hardware
3821 .qe (),
3822 .q (reg2hw.key_intr_ctl.key0_in_l2h.q),
3823 .ds (),
3824
3825 // to register interface (read)
3826 .qs (aon_key_intr_ctl_key0_in_l2h_qs_int)
3827 );
3828
3829 // F[key1_in_l2h]: 9:9
3830 prim_subreg #(
3831 .DW (1),
3832 .SwAccess(prim_subreg_pkg::SwAccessRW),
3833 .RESVAL (1'h0),
3834 .Mubi (1'b0)
3835 ) u_key_intr_ctl_key1_in_l2h (
3836 .clk_i (clk_aon_i),
3837 .rst_ni (rst_aon_ni),
3838
3839 // from register interface
3840 .we (aon_key_intr_ctl_gated_we),
3841 .wd (aon_key_intr_ctl_wdata[9]),
3842
3843 // from internal hardware
3844 .de (1'b0),
3845 .d ('0),
3846
3847 // to internal hardware
3848 .qe (),
3849 .q (reg2hw.key_intr_ctl.key1_in_l2h.q),
3850 .ds (),
3851
3852 // to register interface (read)
3853 .qs (aon_key_intr_ctl_key1_in_l2h_qs_int)
3854 );
3855
3856 // F[key2_in_l2h]: 10:10
3857 prim_subreg #(
3858 .DW (1),
3859 .SwAccess(prim_subreg_pkg::SwAccessRW),
3860 .RESVAL (1'h0),
3861 .Mubi (1'b0)
3862 ) u_key_intr_ctl_key2_in_l2h (
3863 .clk_i (clk_aon_i),
3864 .rst_ni (rst_aon_ni),
3865
3866 // from register interface
3867 .we (aon_key_intr_ctl_gated_we),
3868 .wd (aon_key_intr_ctl_wdata[10]),
3869
3870 // from internal hardware
3871 .de (1'b0),
3872 .d ('0),
3873
3874 // to internal hardware
3875 .qe (),
3876 .q (reg2hw.key_intr_ctl.key2_in_l2h.q),
3877 .ds (),
3878
3879 // to register interface (read)
3880 .qs (aon_key_intr_ctl_key2_in_l2h_qs_int)
3881 );
3882
3883 // F[ac_present_l2h]: 11:11
3884 prim_subreg #(
3885 .DW (1),
3886 .SwAccess(prim_subreg_pkg::SwAccessRW),
3887 .RESVAL (1'h0),
3888 .Mubi (1'b0)
3889 ) u_key_intr_ctl_ac_present_l2h (
3890 .clk_i (clk_aon_i),
3891 .rst_ni (rst_aon_ni),
3892
3893 // from register interface
3894 .we (aon_key_intr_ctl_gated_we),
3895 .wd (aon_key_intr_ctl_wdata[11]),
3896
3897 // from internal hardware
3898 .de (1'b0),
3899 .d ('0),
3900
3901 // to internal hardware
3902 .qe (),
3903 .q (reg2hw.key_intr_ctl.ac_present_l2h.q),
3904 .ds (),
3905
3906 // to register interface (read)
3907 .qs (aon_key_intr_ctl_ac_present_l2h_qs_int)
3908 );
3909
3910 // F[ec_rst_l_l2h]: 12:12
3911 prim_subreg #(
3912 .DW (1),
3913 .SwAccess(prim_subreg_pkg::SwAccessRW),
3914 .RESVAL (1'h0),
3915 .Mubi (1'b0)
3916 ) u_key_intr_ctl_ec_rst_l_l2h (
3917 .clk_i (clk_aon_i),
3918 .rst_ni (rst_aon_ni),
3919
3920 // from register interface
3921 .we (aon_key_intr_ctl_gated_we),
3922 .wd (aon_key_intr_ctl_wdata[12]),
3923
3924 // from internal hardware
3925 .de (1'b0),
3926 .d ('0),
3927
3928 // to internal hardware
3929 .qe (),
3930 .q (reg2hw.key_intr_ctl.ec_rst_l_l2h.q),
3931 .ds (),
3932
3933 // to register interface (read)
3934 .qs (aon_key_intr_ctl_ec_rst_l_l2h_qs_int)
3935 );
3936
3937 // F[flash_wp_l_l2h]: 13:13
3938 prim_subreg #(
3939 .DW (1),
3940 .SwAccess(prim_subreg_pkg::SwAccessRW),
3941 .RESVAL (1'h0),
3942 .Mubi (1'b0)
3943 ) u_key_intr_ctl_flash_wp_l_l2h (
3944 .clk_i (clk_aon_i),
3945 .rst_ni (rst_aon_ni),
3946
3947 // from register interface
3948 .we (aon_key_intr_ctl_gated_we),
3949 .wd (aon_key_intr_ctl_wdata[13]),
3950
3951 // from internal hardware
3952 .de (1'b0),
3953 .d ('0),
3954
3955 // to internal hardware
3956 .qe (),
3957 .q (reg2hw.key_intr_ctl.flash_wp_l_l2h.q),
3958 .ds (),
3959
3960 // to register interface (read)
3961 .qs (aon_key_intr_ctl_flash_wp_l_l2h_qs_int)
3962 );
3963
3964
3965 // R[key_intr_debounce_ctl]: V(False)
3966 // Create REGWEN-gated WE signal
3967 logic aon_key_intr_debounce_ctl_gated_we;
3968 1/1 assign aon_key_intr_debounce_ctl_gated_we =
Tests: T1 T2 T3
3969 aon_key_intr_debounce_ctl_we & aon_key_intr_debounce_ctl_regwen;
3970 prim_subreg #(
3971 .DW (16),
3972 .SwAccess(prim_subreg_pkg::SwAccessRW),
3973 .RESVAL (16'h7d0),
3974 .Mubi (1'b0)
3975 ) u_key_intr_debounce_ctl (
3976 .clk_i (clk_aon_i),
3977 .rst_ni (rst_aon_ni),
3978
3979 // from register interface
3980 .we (aon_key_intr_debounce_ctl_gated_we),
3981 .wd (aon_key_intr_debounce_ctl_wdata[15:0]),
3982
3983 // from internal hardware
3984 .de (1'b0),
3985 .d ('0),
3986
3987 // to internal hardware
3988 .qe (),
3989 .q (reg2hw.key_intr_debounce_ctl.q),
3990 .ds (),
3991
3992 // to register interface (read)
3993 .qs (aon_key_intr_debounce_ctl_qs_int)
3994 );
3995
3996
3997 // R[auto_block_debounce_ctl]: V(False)
3998 // Create REGWEN-gated WE signal
3999 logic aon_auto_block_debounce_ctl_gated_we;
4000 1/1 assign aon_auto_block_debounce_ctl_gated_we =
Tests: T16 T27 T28
4001 aon_auto_block_debounce_ctl_we & aon_auto_block_debounce_ctl_regwen;
4002 // F[debounce_timer]: 15:0
4003 prim_subreg #(
4004 .DW (16),
4005 .SwAccess(prim_subreg_pkg::SwAccessRW),
4006 .RESVAL (16'h7d0),
4007 .Mubi (1'b0)
4008 ) u_auto_block_debounce_ctl_debounce_timer (
4009 .clk_i (clk_aon_i),
4010 .rst_ni (rst_aon_ni),
4011
4012 // from register interface
4013 .we (aon_auto_block_debounce_ctl_gated_we),
4014 .wd (aon_auto_block_debounce_ctl_wdata[15:0]),
4015
4016 // from internal hardware
4017 .de (1'b0),
4018 .d ('0),
4019
4020 // to internal hardware
4021 .qe (),
4022 .q (reg2hw.auto_block_debounce_ctl.debounce_timer.q),
4023 .ds (),
4024
4025 // to register interface (read)
4026 .qs (aon_auto_block_debounce_ctl_debounce_timer_qs_int)
4027 );
4028
4029 // F[auto_block_enable]: 16:16
4030 prim_subreg #(
4031 .DW (1),
4032 .SwAccess(prim_subreg_pkg::SwAccessRW),
4033 .RESVAL (1'h0),
4034 .Mubi (1'b0)
4035 ) u_auto_block_debounce_ctl_auto_block_enable (
4036 .clk_i (clk_aon_i),
4037 .rst_ni (rst_aon_ni),
4038
4039 // from register interface
4040 .we (aon_auto_block_debounce_ctl_gated_we),
4041 .wd (aon_auto_block_debounce_ctl_wdata[16]),
4042
4043 // from internal hardware
4044 .de (1'b0),
4045 .d ('0),
4046
4047 // to internal hardware
4048 .qe (),
4049 .q (reg2hw.auto_block_debounce_ctl.auto_block_enable.q),
4050 .ds (),
4051
4052 // to register interface (read)
4053 .qs (aon_auto_block_debounce_ctl_auto_block_enable_qs_int)
4054 );
4055
4056
4057 // R[auto_block_out_ctl]: V(False)
4058 // Create REGWEN-gated WE signal
4059 logic aon_auto_block_out_ctl_gated_we;
4060 1/1 assign aon_auto_block_out_ctl_gated_we =
Tests: T16 T27 T28
4061 aon_auto_block_out_ctl_we & aon_auto_block_out_ctl_regwen;
4062 // F[key0_out_sel]: 0:0
4063 prim_subreg #(
4064 .DW (1),
4065 .SwAccess(prim_subreg_pkg::SwAccessRW),
4066 .RESVAL (1'h0),
4067 .Mubi (1'b0)
4068 ) u_auto_block_out_ctl_key0_out_sel (
4069 .clk_i (clk_aon_i),
4070 .rst_ni (rst_aon_ni),
4071
4072 // from register interface
4073 .we (aon_auto_block_out_ctl_gated_we),
4074 .wd (aon_auto_block_out_ctl_wdata[0]),
4075
4076 // from internal hardware
4077 .de (1'b0),
4078 .d ('0),
4079
4080 // to internal hardware
4081 .qe (),
4082 .q (reg2hw.auto_block_out_ctl.key0_out_sel.q),
4083 .ds (),
4084
4085 // to register interface (read)
4086 .qs (aon_auto_block_out_ctl_key0_out_sel_qs_int)
4087 );
4088
4089 // F[key1_out_sel]: 1:1
4090 prim_subreg #(
4091 .DW (1),
4092 .SwAccess(prim_subreg_pkg::SwAccessRW),
4093 .RESVAL (1'h0),
4094 .Mubi (1'b0)
4095 ) u_auto_block_out_ctl_key1_out_sel (
4096 .clk_i (clk_aon_i),
4097 .rst_ni (rst_aon_ni),
4098
4099 // from register interface
4100 .we (aon_auto_block_out_ctl_gated_we),
4101 .wd (aon_auto_block_out_ctl_wdata[1]),
4102
4103 // from internal hardware
4104 .de (1'b0),
4105 .d ('0),
4106
4107 // to internal hardware
4108 .qe (),
4109 .q (reg2hw.auto_block_out_ctl.key1_out_sel.q),
4110 .ds (),
4111
4112 // to register interface (read)
4113 .qs (aon_auto_block_out_ctl_key1_out_sel_qs_int)
4114 );
4115
4116 // F[key2_out_sel]: 2:2
4117 prim_subreg #(
4118 .DW (1),
4119 .SwAccess(prim_subreg_pkg::SwAccessRW),
4120 .RESVAL (1'h0),
4121 .Mubi (1'b0)
4122 ) u_auto_block_out_ctl_key2_out_sel (
4123 .clk_i (clk_aon_i),
4124 .rst_ni (rst_aon_ni),
4125
4126 // from register interface
4127 .we (aon_auto_block_out_ctl_gated_we),
4128 .wd (aon_auto_block_out_ctl_wdata[2]),
4129
4130 // from internal hardware
4131 .de (1'b0),
4132 .d ('0),
4133
4134 // to internal hardware
4135 .qe (),
4136 .q (reg2hw.auto_block_out_ctl.key2_out_sel.q),
4137 .ds (),
4138
4139 // to register interface (read)
4140 .qs (aon_auto_block_out_ctl_key2_out_sel_qs_int)
4141 );
4142
4143 // F[key0_out_value]: 4:4
4144 prim_subreg #(
4145 .DW (1),
4146 .SwAccess(prim_subreg_pkg::SwAccessRW),
4147 .RESVAL (1'h0),
4148 .Mubi (1'b0)
4149 ) u_auto_block_out_ctl_key0_out_value (
4150 .clk_i (clk_aon_i),
4151 .rst_ni (rst_aon_ni),
4152
4153 // from register interface
4154 .we (aon_auto_block_out_ctl_gated_we),
4155 .wd (aon_auto_block_out_ctl_wdata[4]),
4156
4157 // from internal hardware
4158 .de (1'b0),
4159 .d ('0),
4160
4161 // to internal hardware
4162 .qe (),
4163 .q (reg2hw.auto_block_out_ctl.key0_out_value.q),
4164 .ds (),
4165
4166 // to register interface (read)
4167 .qs (aon_auto_block_out_ctl_key0_out_value_qs_int)
4168 );
4169
4170 // F[key1_out_value]: 5:5
4171 prim_subreg #(
4172 .DW (1),
4173 .SwAccess(prim_subreg_pkg::SwAccessRW),
4174 .RESVAL (1'h0),
4175 .Mubi (1'b0)
4176 ) u_auto_block_out_ctl_key1_out_value (
4177 .clk_i (clk_aon_i),
4178 .rst_ni (rst_aon_ni),
4179
4180 // from register interface
4181 .we (aon_auto_block_out_ctl_gated_we),
4182 .wd (aon_auto_block_out_ctl_wdata[5]),
4183
4184 // from internal hardware
4185 .de (1'b0),
4186 .d ('0),
4187
4188 // to internal hardware
4189 .qe (),
4190 .q (reg2hw.auto_block_out_ctl.key1_out_value.q),
4191 .ds (),
4192
4193 // to register interface (read)
4194 .qs (aon_auto_block_out_ctl_key1_out_value_qs_int)
4195 );
4196
4197 // F[key2_out_value]: 6:6
4198 prim_subreg #(
4199 .DW (1),
4200 .SwAccess(prim_subreg_pkg::SwAccessRW),
4201 .RESVAL (1'h0),
4202 .Mubi (1'b0)
4203 ) u_auto_block_out_ctl_key2_out_value (
4204 .clk_i (clk_aon_i),
4205 .rst_ni (rst_aon_ni),
4206
4207 // from register interface
4208 .we (aon_auto_block_out_ctl_gated_we),
4209 .wd (aon_auto_block_out_ctl_wdata[6]),
4210
4211 // from internal hardware
4212 .de (1'b0),
4213 .d ('0),
4214
4215 // to internal hardware
4216 .qe (),
4217 .q (reg2hw.auto_block_out_ctl.key2_out_value.q),
4218 .ds (),
4219
4220 // to register interface (read)
4221 .qs (aon_auto_block_out_ctl_key2_out_value_qs_int)
4222 );
4223
4224
4225 // Subregister 0 of Multireg com_pre_sel_ctl
4226 // R[com_pre_sel_ctl_0]: V(False)
4227 // Create REGWEN-gated WE signal
4228 logic aon_com_pre_sel_ctl_0_gated_we;
4229 1/1 assign aon_com_pre_sel_ctl_0_gated_we = aon_com_pre_sel_ctl_0_we & aon_com_pre_sel_ctl_0_regwen;
Tests: T1 T8 T29
4230 // F[key0_in_sel_0]: 0:0
4231 prim_subreg #(
4232 .DW (1),
4233 .SwAccess(prim_subreg_pkg::SwAccessRW),
4234 .RESVAL (1'h0),
4235 .Mubi (1'b0)
4236 ) u_com_pre_sel_ctl_0_key0_in_sel_0 (
4237 .clk_i (clk_aon_i),
4238 .rst_ni (rst_aon_ni),
4239
4240 // from register interface
4241 .we (aon_com_pre_sel_ctl_0_gated_we),
4242 .wd (aon_com_pre_sel_ctl_0_wdata[0]),
4243
4244 // from internal hardware
4245 .de (1'b0),
4246 .d ('0),
4247
4248 // to internal hardware
4249 .qe (),
4250 .q (reg2hw.com_pre_sel_ctl[0].key0_in_sel.q),
4251 .ds (),
4252
4253 // to register interface (read)
4254 .qs (aon_com_pre_sel_ctl_0_key0_in_sel_0_qs_int)
4255 );
4256
4257 // F[key1_in_sel_0]: 1:1
4258 prim_subreg #(
4259 .DW (1),
4260 .SwAccess(prim_subreg_pkg::SwAccessRW),
4261 .RESVAL (1'h0),
4262 .Mubi (1'b0)
4263 ) u_com_pre_sel_ctl_0_key1_in_sel_0 (
4264 .clk_i (clk_aon_i),
4265 .rst_ni (rst_aon_ni),
4266
4267 // from register interface
4268 .we (aon_com_pre_sel_ctl_0_gated_we),
4269 .wd (aon_com_pre_sel_ctl_0_wdata[1]),
4270
4271 // from internal hardware
4272 .de (1'b0),
4273 .d ('0),
4274
4275 // to internal hardware
4276 .qe (),
4277 .q (reg2hw.com_pre_sel_ctl[0].key1_in_sel.q),
4278 .ds (),
4279
4280 // to register interface (read)
4281 .qs (aon_com_pre_sel_ctl_0_key1_in_sel_0_qs_int)
4282 );
4283
4284 // F[key2_in_sel_0]: 2:2
4285 prim_subreg #(
4286 .DW (1),
4287 .SwAccess(prim_subreg_pkg::SwAccessRW),
4288 .RESVAL (1'h0),
4289 .Mubi (1'b0)
4290 ) u_com_pre_sel_ctl_0_key2_in_sel_0 (
4291 .clk_i (clk_aon_i),
4292 .rst_ni (rst_aon_ni),
4293
4294 // from register interface
4295 .we (aon_com_pre_sel_ctl_0_gated_we),
4296 .wd (aon_com_pre_sel_ctl_0_wdata[2]),
4297
4298 // from internal hardware
4299 .de (1'b0),
4300 .d ('0),
4301
4302 // to internal hardware
4303 .qe (),
4304 .q (reg2hw.com_pre_sel_ctl[0].key2_in_sel.q),
4305 .ds (),
4306
4307 // to register interface (read)
4308 .qs (aon_com_pre_sel_ctl_0_key2_in_sel_0_qs_int)
4309 );
4310
4311 // F[pwrb_in_sel_0]: 3:3
4312 prim_subreg #(
4313 .DW (1),
4314 .SwAccess(prim_subreg_pkg::SwAccessRW),
4315 .RESVAL (1'h0),
4316 .Mubi (1'b0)
4317 ) u_com_pre_sel_ctl_0_pwrb_in_sel_0 (
4318 .clk_i (clk_aon_i),
4319 .rst_ni (rst_aon_ni),
4320
4321 // from register interface
4322 .we (aon_com_pre_sel_ctl_0_gated_we),
4323 .wd (aon_com_pre_sel_ctl_0_wdata[3]),
4324
4325 // from internal hardware
4326 .de (1'b0),
4327 .d ('0),
4328
4329 // to internal hardware
4330 .qe (),
4331 .q (reg2hw.com_pre_sel_ctl[0].pwrb_in_sel.q),
4332 .ds (),
4333
4334 // to register interface (read)
4335 .qs (aon_com_pre_sel_ctl_0_pwrb_in_sel_0_qs_int)
4336 );
4337
4338 // F[ac_present_sel_0]: 4:4
4339 prim_subreg #(
4340 .DW (1),
4341 .SwAccess(prim_subreg_pkg::SwAccessRW),
4342 .RESVAL (1'h0),
4343 .Mubi (1'b0)
4344 ) u_com_pre_sel_ctl_0_ac_present_sel_0 (
4345 .clk_i (clk_aon_i),
4346 .rst_ni (rst_aon_ni),
4347
4348 // from register interface
4349 .we (aon_com_pre_sel_ctl_0_gated_we),
4350 .wd (aon_com_pre_sel_ctl_0_wdata[4]),
4351
4352 // from internal hardware
4353 .de (1'b0),
4354 .d ('0),
4355
4356 // to internal hardware
4357 .qe (),
4358 .q (reg2hw.com_pre_sel_ctl[0].ac_present_sel.q),
4359 .ds (),
4360
4361 // to register interface (read)
4362 .qs (aon_com_pre_sel_ctl_0_ac_present_sel_0_qs_int)
4363 );
4364
4365
4366 // Subregister 1 of Multireg com_pre_sel_ctl
4367 // R[com_pre_sel_ctl_1]: V(False)
4368 // Create REGWEN-gated WE signal
4369 logic aon_com_pre_sel_ctl_1_gated_we;
4370 1/1 assign aon_com_pre_sel_ctl_1_gated_we = aon_com_pre_sel_ctl_1_we & aon_com_pre_sel_ctl_1_regwen;
Tests: T12 T20 T30
4371 // F[key0_in_sel_1]: 0:0
4372 prim_subreg #(
4373 .DW (1),
4374 .SwAccess(prim_subreg_pkg::SwAccessRW),
4375 .RESVAL (1'h0),
4376 .Mubi (1'b0)
4377 ) u_com_pre_sel_ctl_1_key0_in_sel_1 (
4378 .clk_i (clk_aon_i),
4379 .rst_ni (rst_aon_ni),
4380
4381 // from register interface
4382 .we (aon_com_pre_sel_ctl_1_gated_we),
4383 .wd (aon_com_pre_sel_ctl_1_wdata[0]),
4384
4385 // from internal hardware
4386 .de (1'b0),
4387 .d ('0),
4388
4389 // to internal hardware
4390 .qe (),
4391 .q (reg2hw.com_pre_sel_ctl[1].key0_in_sel.q),
4392 .ds (),
4393
4394 // to register interface (read)
4395 .qs (aon_com_pre_sel_ctl_1_key0_in_sel_1_qs_int)
4396 );
4397
4398 // F[key1_in_sel_1]: 1:1
4399 prim_subreg #(
4400 .DW (1),
4401 .SwAccess(prim_subreg_pkg::SwAccessRW),
4402 .RESVAL (1'h0),
4403 .Mubi (1'b0)
4404 ) u_com_pre_sel_ctl_1_key1_in_sel_1 (
4405 .clk_i (clk_aon_i),
4406 .rst_ni (rst_aon_ni),
4407
4408 // from register interface
4409 .we (aon_com_pre_sel_ctl_1_gated_we),
4410 .wd (aon_com_pre_sel_ctl_1_wdata[1]),
4411
4412 // from internal hardware
4413 .de (1'b0),
4414 .d ('0),
4415
4416 // to internal hardware
4417 .qe (),
4418 .q (reg2hw.com_pre_sel_ctl[1].key1_in_sel.q),
4419 .ds (),
4420
4421 // to register interface (read)
4422 .qs (aon_com_pre_sel_ctl_1_key1_in_sel_1_qs_int)
4423 );
4424
4425 // F[key2_in_sel_1]: 2:2
4426 prim_subreg #(
4427 .DW (1),
4428 .SwAccess(prim_subreg_pkg::SwAccessRW),
4429 .RESVAL (1'h0),
4430 .Mubi (1'b0)
4431 ) u_com_pre_sel_ctl_1_key2_in_sel_1 (
4432 .clk_i (clk_aon_i),
4433 .rst_ni (rst_aon_ni),
4434
4435 // from register interface
4436 .we (aon_com_pre_sel_ctl_1_gated_we),
4437 .wd (aon_com_pre_sel_ctl_1_wdata[2]),
4438
4439 // from internal hardware
4440 .de (1'b0),
4441 .d ('0),
4442
4443 // to internal hardware
4444 .qe (),
4445 .q (reg2hw.com_pre_sel_ctl[1].key2_in_sel.q),
4446 .ds (),
4447
4448 // to register interface (read)
4449 .qs (aon_com_pre_sel_ctl_1_key2_in_sel_1_qs_int)
4450 );
4451
4452 // F[pwrb_in_sel_1]: 3:3
4453 prim_subreg #(
4454 .DW (1),
4455 .SwAccess(prim_subreg_pkg::SwAccessRW),
4456 .RESVAL (1'h0),
4457 .Mubi (1'b0)
4458 ) u_com_pre_sel_ctl_1_pwrb_in_sel_1 (
4459 .clk_i (clk_aon_i),
4460 .rst_ni (rst_aon_ni),
4461
4462 // from register interface
4463 .we (aon_com_pre_sel_ctl_1_gated_we),
4464 .wd (aon_com_pre_sel_ctl_1_wdata[3]),
4465
4466 // from internal hardware
4467 .de (1'b0),
4468 .d ('0),
4469
4470 // to internal hardware
4471 .qe (),
4472 .q (reg2hw.com_pre_sel_ctl[1].pwrb_in_sel.q),
4473 .ds (),
4474
4475 // to register interface (read)
4476 .qs (aon_com_pre_sel_ctl_1_pwrb_in_sel_1_qs_int)
4477 );
4478
4479 // F[ac_present_sel_1]: 4:4
4480 prim_subreg #(
4481 .DW (1),
4482 .SwAccess(prim_subreg_pkg::SwAccessRW),
4483 .RESVAL (1'h0),
4484 .Mubi (1'b0)
4485 ) u_com_pre_sel_ctl_1_ac_present_sel_1 (
4486 .clk_i (clk_aon_i),
4487 .rst_ni (rst_aon_ni),
4488
4489 // from register interface
4490 .we (aon_com_pre_sel_ctl_1_gated_we),
4491 .wd (aon_com_pre_sel_ctl_1_wdata[4]),
4492
4493 // from internal hardware
4494 .de (1'b0),
4495 .d ('0),
4496
4497 // to internal hardware
4498 .qe (),
4499 .q (reg2hw.com_pre_sel_ctl[1].ac_present_sel.q),
4500 .ds (),
4501
4502 // to register interface (read)
4503 .qs (aon_com_pre_sel_ctl_1_ac_present_sel_1_qs_int)
4504 );
4505
4506
4507 // Subregister 2 of Multireg com_pre_sel_ctl
4508 // R[com_pre_sel_ctl_2]: V(False)
4509 // Create REGWEN-gated WE signal
4510 logic aon_com_pre_sel_ctl_2_gated_we;
4511 1/1 assign aon_com_pre_sel_ctl_2_gated_we = aon_com_pre_sel_ctl_2_we & aon_com_pre_sel_ctl_2_regwen;
Tests: T12 T20 T30
4512 // F[key0_in_sel_2]: 0:0
4513 prim_subreg #(
4514 .DW (1),
4515 .SwAccess(prim_subreg_pkg::SwAccessRW),
4516 .RESVAL (1'h0),
4517 .Mubi (1'b0)
4518 ) u_com_pre_sel_ctl_2_key0_in_sel_2 (
4519 .clk_i (clk_aon_i),
4520 .rst_ni (rst_aon_ni),
4521
4522 // from register interface
4523 .we (aon_com_pre_sel_ctl_2_gated_we),
4524 .wd (aon_com_pre_sel_ctl_2_wdata[0]),
4525
4526 // from internal hardware
4527 .de (1'b0),
4528 .d ('0),
4529
4530 // to internal hardware
4531 .qe (),
4532 .q (reg2hw.com_pre_sel_ctl[2].key0_in_sel.q),
4533 .ds (),
4534
4535 // to register interface (read)
4536 .qs (aon_com_pre_sel_ctl_2_key0_in_sel_2_qs_int)
4537 );
4538
4539 // F[key1_in_sel_2]: 1:1
4540 prim_subreg #(
4541 .DW (1),
4542 .SwAccess(prim_subreg_pkg::SwAccessRW),
4543 .RESVAL (1'h0),
4544 .Mubi (1'b0)
4545 ) u_com_pre_sel_ctl_2_key1_in_sel_2 (
4546 .clk_i (clk_aon_i),
4547 .rst_ni (rst_aon_ni),
4548
4549 // from register interface
4550 .we (aon_com_pre_sel_ctl_2_gated_we),
4551 .wd (aon_com_pre_sel_ctl_2_wdata[1]),
4552
4553 // from internal hardware
4554 .de (1'b0),
4555 .d ('0),
4556
4557 // to internal hardware
4558 .qe (),
4559 .q (reg2hw.com_pre_sel_ctl[2].key1_in_sel.q),
4560 .ds (),
4561
4562 // to register interface (read)
4563 .qs (aon_com_pre_sel_ctl_2_key1_in_sel_2_qs_int)
4564 );
4565
4566 // F[key2_in_sel_2]: 2:2
4567 prim_subreg #(
4568 .DW (1),
4569 .SwAccess(prim_subreg_pkg::SwAccessRW),
4570 .RESVAL (1'h0),
4571 .Mubi (1'b0)
4572 ) u_com_pre_sel_ctl_2_key2_in_sel_2 (
4573 .clk_i (clk_aon_i),
4574 .rst_ni (rst_aon_ni),
4575
4576 // from register interface
4577 .we (aon_com_pre_sel_ctl_2_gated_we),
4578 .wd (aon_com_pre_sel_ctl_2_wdata[2]),
4579
4580 // from internal hardware
4581 .de (1'b0),
4582 .d ('0),
4583
4584 // to internal hardware
4585 .qe (),
4586 .q (reg2hw.com_pre_sel_ctl[2].key2_in_sel.q),
4587 .ds (),
4588
4589 // to register interface (read)
4590 .qs (aon_com_pre_sel_ctl_2_key2_in_sel_2_qs_int)
4591 );
4592
4593 // F[pwrb_in_sel_2]: 3:3
4594 prim_subreg #(
4595 .DW (1),
4596 .SwAccess(prim_subreg_pkg::SwAccessRW),
4597 .RESVAL (1'h0),
4598 .Mubi (1'b0)
4599 ) u_com_pre_sel_ctl_2_pwrb_in_sel_2 (
4600 .clk_i (clk_aon_i),
4601 .rst_ni (rst_aon_ni),
4602
4603 // from register interface
4604 .we (aon_com_pre_sel_ctl_2_gated_we),
4605 .wd (aon_com_pre_sel_ctl_2_wdata[3]),
4606
4607 // from internal hardware
4608 .de (1'b0),
4609 .d ('0),
4610
4611 // to internal hardware
4612 .qe (),
4613 .q (reg2hw.com_pre_sel_ctl[2].pwrb_in_sel.q),
4614 .ds (),
4615
4616 // to register interface (read)
4617 .qs (aon_com_pre_sel_ctl_2_pwrb_in_sel_2_qs_int)
4618 );
4619
4620 // F[ac_present_sel_2]: 4:4
4621 prim_subreg #(
4622 .DW (1),
4623 .SwAccess(prim_subreg_pkg::SwAccessRW),
4624 .RESVAL (1'h0),
4625 .Mubi (1'b0)
4626 ) u_com_pre_sel_ctl_2_ac_present_sel_2 (
4627 .clk_i (clk_aon_i),
4628 .rst_ni (rst_aon_ni),
4629
4630 // from register interface
4631 .we (aon_com_pre_sel_ctl_2_gated_we),
4632 .wd (aon_com_pre_sel_ctl_2_wdata[4]),
4633
4634 // from internal hardware
4635 .de (1'b0),
4636 .d ('0),
4637
4638 // to internal hardware
4639 .qe (),
4640 .q (reg2hw.com_pre_sel_ctl[2].ac_present_sel.q),
4641 .ds (),
4642
4643 // to register interface (read)
4644 .qs (aon_com_pre_sel_ctl_2_ac_present_sel_2_qs_int)
4645 );
4646
4647
4648 // Subregister 3 of Multireg com_pre_sel_ctl
4649 // R[com_pre_sel_ctl_3]: V(False)
4650 // Create REGWEN-gated WE signal
4651 logic aon_com_pre_sel_ctl_3_gated_we;
4652 1/1 assign aon_com_pre_sel_ctl_3_gated_we = aon_com_pre_sel_ctl_3_we & aon_com_pre_sel_ctl_3_regwen;
Tests: T12 T20 T30
4653 // F[key0_in_sel_3]: 0:0
4654 prim_subreg #(
4655 .DW (1),
4656 .SwAccess(prim_subreg_pkg::SwAccessRW),
4657 .RESVAL (1'h0),
4658 .Mubi (1'b0)
4659 ) u_com_pre_sel_ctl_3_key0_in_sel_3 (
4660 .clk_i (clk_aon_i),
4661 .rst_ni (rst_aon_ni),
4662
4663 // from register interface
4664 .we (aon_com_pre_sel_ctl_3_gated_we),
4665 .wd (aon_com_pre_sel_ctl_3_wdata[0]),
4666
4667 // from internal hardware
4668 .de (1'b0),
4669 .d ('0),
4670
4671 // to internal hardware
4672 .qe (),
4673 .q (reg2hw.com_pre_sel_ctl[3].key0_in_sel.q),
4674 .ds (),
4675
4676 // to register interface (read)
4677 .qs (aon_com_pre_sel_ctl_3_key0_in_sel_3_qs_int)
4678 );
4679
4680 // F[key1_in_sel_3]: 1:1
4681 prim_subreg #(
4682 .DW (1),
4683 .SwAccess(prim_subreg_pkg::SwAccessRW),
4684 .RESVAL (1'h0),
4685 .Mubi (1'b0)
4686 ) u_com_pre_sel_ctl_3_key1_in_sel_3 (
4687 .clk_i (clk_aon_i),
4688 .rst_ni (rst_aon_ni),
4689
4690 // from register interface
4691 .we (aon_com_pre_sel_ctl_3_gated_we),
4692 .wd (aon_com_pre_sel_ctl_3_wdata[1]),
4693
4694 // from internal hardware
4695 .de (1'b0),
4696 .d ('0),
4697
4698 // to internal hardware
4699 .qe (),
4700 .q (reg2hw.com_pre_sel_ctl[3].key1_in_sel.q),
4701 .ds (),
4702
4703 // to register interface (read)
4704 .qs (aon_com_pre_sel_ctl_3_key1_in_sel_3_qs_int)
4705 );
4706
4707 // F[key2_in_sel_3]: 2:2
4708 prim_subreg #(
4709 .DW (1),
4710 .SwAccess(prim_subreg_pkg::SwAccessRW),
4711 .RESVAL (1'h0),
4712 .Mubi (1'b0)
4713 ) u_com_pre_sel_ctl_3_key2_in_sel_3 (
4714 .clk_i (clk_aon_i),
4715 .rst_ni (rst_aon_ni),
4716
4717 // from register interface
4718 .we (aon_com_pre_sel_ctl_3_gated_we),
4719 .wd (aon_com_pre_sel_ctl_3_wdata[2]),
4720
4721 // from internal hardware
4722 .de (1'b0),
4723 .d ('0),
4724
4725 // to internal hardware
4726 .qe (),
4727 .q (reg2hw.com_pre_sel_ctl[3].key2_in_sel.q),
4728 .ds (),
4729
4730 // to register interface (read)
4731 .qs (aon_com_pre_sel_ctl_3_key2_in_sel_3_qs_int)
4732 );
4733
4734 // F[pwrb_in_sel_3]: 3:3
4735 prim_subreg #(
4736 .DW (1),
4737 .SwAccess(prim_subreg_pkg::SwAccessRW),
4738 .RESVAL (1'h0),
4739 .Mubi (1'b0)
4740 ) u_com_pre_sel_ctl_3_pwrb_in_sel_3 (
4741 .clk_i (clk_aon_i),
4742 .rst_ni (rst_aon_ni),
4743
4744 // from register interface
4745 .we (aon_com_pre_sel_ctl_3_gated_we),
4746 .wd (aon_com_pre_sel_ctl_3_wdata[3]),
4747
4748 // from internal hardware
4749 .de (1'b0),
4750 .d ('0),
4751
4752 // to internal hardware
4753 .qe (),
4754 .q (reg2hw.com_pre_sel_ctl[3].pwrb_in_sel.q),
4755 .ds (),
4756
4757 // to register interface (read)
4758 .qs (aon_com_pre_sel_ctl_3_pwrb_in_sel_3_qs_int)
4759 );
4760
4761 // F[ac_present_sel_3]: 4:4
4762 prim_subreg #(
4763 .DW (1),
4764 .SwAccess(prim_subreg_pkg::SwAccessRW),
4765 .RESVAL (1'h0),
4766 .Mubi (1'b0)
4767 ) u_com_pre_sel_ctl_3_ac_present_sel_3 (
4768 .clk_i (clk_aon_i),
4769 .rst_ni (rst_aon_ni),
4770
4771 // from register interface
4772 .we (aon_com_pre_sel_ctl_3_gated_we),
4773 .wd (aon_com_pre_sel_ctl_3_wdata[4]),
4774
4775 // from internal hardware
4776 .de (1'b0),
4777 .d ('0),
4778
4779 // to internal hardware
4780 .qe (),
4781 .q (reg2hw.com_pre_sel_ctl[3].ac_present_sel.q),
4782 .ds (),
4783
4784 // to register interface (read)
4785 .qs (aon_com_pre_sel_ctl_3_ac_present_sel_3_qs_int)
4786 );
4787
4788
4789 // Subregister 0 of Multireg com_pre_det_ctl
4790 // R[com_pre_det_ctl_0]: V(False)
4791 // Create REGWEN-gated WE signal
4792 logic aon_com_pre_det_ctl_0_gated_we;
4793 1/1 assign aon_com_pre_det_ctl_0_gated_we = aon_com_pre_det_ctl_0_we & aon_com_pre_det_ctl_0_regwen;
Tests: T1 T8 T29
4794 prim_subreg #(
4795 .DW (32),
4796 .SwAccess(prim_subreg_pkg::SwAccessRW),
4797 .RESVAL (32'h0),
4798 .Mubi (1'b0)
4799 ) u_com_pre_det_ctl_0 (
4800 .clk_i (clk_aon_i),
4801 .rst_ni (rst_aon_ni),
4802
4803 // from register interface
4804 .we (aon_com_pre_det_ctl_0_gated_we),
4805 .wd (aon_com_pre_det_ctl_0_wdata[31:0]),
4806
4807 // from internal hardware
4808 .de (1'b0),
4809 .d ('0),
4810
4811 // to internal hardware
4812 .qe (),
4813 .q (reg2hw.com_pre_det_ctl[0].q),
4814 .ds (),
4815
4816 // to register interface (read)
4817 .qs (aon_com_pre_det_ctl_0_qs_int)
4818 );
4819
4820
4821 // Subregister 1 of Multireg com_pre_det_ctl
4822 // R[com_pre_det_ctl_1]: V(False)
4823 // Create REGWEN-gated WE signal
4824 logic aon_com_pre_det_ctl_1_gated_we;
4825 1/1 assign aon_com_pre_det_ctl_1_gated_we = aon_com_pre_det_ctl_1_we & aon_com_pre_det_ctl_1_regwen;
Tests: T12 T20 T30
4826 prim_subreg #(
4827 .DW (32),
4828 .SwAccess(prim_subreg_pkg::SwAccessRW),
4829 .RESVAL (32'h0),
4830 .Mubi (1'b0)
4831 ) u_com_pre_det_ctl_1 (
4832 .clk_i (clk_aon_i),
4833 .rst_ni (rst_aon_ni),
4834
4835 // from register interface
4836 .we (aon_com_pre_det_ctl_1_gated_we),
4837 .wd (aon_com_pre_det_ctl_1_wdata[31:0]),
4838
4839 // from internal hardware
4840 .de (1'b0),
4841 .d ('0),
4842
4843 // to internal hardware
4844 .qe (),
4845 .q (reg2hw.com_pre_det_ctl[1].q),
4846 .ds (),
4847
4848 // to register interface (read)
4849 .qs (aon_com_pre_det_ctl_1_qs_int)
4850 );
4851
4852
4853 // Subregister 2 of Multireg com_pre_det_ctl
4854 // R[com_pre_det_ctl_2]: V(False)
4855 // Create REGWEN-gated WE signal
4856 logic aon_com_pre_det_ctl_2_gated_we;
4857 1/1 assign aon_com_pre_det_ctl_2_gated_we = aon_com_pre_det_ctl_2_we & aon_com_pre_det_ctl_2_regwen;
Tests: T12 T20 T30
4858 prim_subreg #(
4859 .DW (32),
4860 .SwAccess(prim_subreg_pkg::SwAccessRW),
4861 .RESVAL (32'h0),
4862 .Mubi (1'b0)
4863 ) u_com_pre_det_ctl_2 (
4864 .clk_i (clk_aon_i),
4865 .rst_ni (rst_aon_ni),
4866
4867 // from register interface
4868 .we (aon_com_pre_det_ctl_2_gated_we),
4869 .wd (aon_com_pre_det_ctl_2_wdata[31:0]),
4870
4871 // from internal hardware
4872 .de (1'b0),
4873 .d ('0),
4874
4875 // to internal hardware
4876 .qe (),
4877 .q (reg2hw.com_pre_det_ctl[2].q),
4878 .ds (),
4879
4880 // to register interface (read)
4881 .qs (aon_com_pre_det_ctl_2_qs_int)
4882 );
4883
4884
4885 // Subregister 3 of Multireg com_pre_det_ctl
4886 // R[com_pre_det_ctl_3]: V(False)
4887 // Create REGWEN-gated WE signal
4888 logic aon_com_pre_det_ctl_3_gated_we;
4889 1/1 assign aon_com_pre_det_ctl_3_gated_we = aon_com_pre_det_ctl_3_we & aon_com_pre_det_ctl_3_regwen;
Tests: T12 T20 T30
4890 prim_subreg #(
4891 .DW (32),
4892 .SwAccess(prim_subreg_pkg::SwAccessRW),
4893 .RESVAL (32'h0),
4894 .Mubi (1'b0)
4895 ) u_com_pre_det_ctl_3 (
4896 .clk_i (clk_aon_i),
4897 .rst_ni (rst_aon_ni),
4898
4899 // from register interface
4900 .we (aon_com_pre_det_ctl_3_gated_we),
4901 .wd (aon_com_pre_det_ctl_3_wdata[31:0]),
4902
4903 // from internal hardware
4904 .de (1'b0),
4905 .d ('0),
4906
4907 // to internal hardware
4908 .qe (),
4909 .q (reg2hw.com_pre_det_ctl[3].q),
4910 .ds (),
4911
4912 // to register interface (read)
4913 .qs (aon_com_pre_det_ctl_3_qs_int)
4914 );
4915
4916
4917 // Subregister 0 of Multireg com_sel_ctl
4918 // R[com_sel_ctl_0]: V(False)
4919 // Create REGWEN-gated WE signal
4920 logic aon_com_sel_ctl_0_gated_we;
4921 1/1 assign aon_com_sel_ctl_0_gated_we = aon_com_sel_ctl_0_we & aon_com_sel_ctl_0_regwen;
Tests: T1 T2 T8
4922 // F[key0_in_sel_0]: 0:0
4923 prim_subreg #(
4924 .DW (1),
4925 .SwAccess(prim_subreg_pkg::SwAccessRW),
4926 .RESVAL (1'h0),
4927 .Mubi (1'b0)
4928 ) u_com_sel_ctl_0_key0_in_sel_0 (
4929 .clk_i (clk_aon_i),
4930 .rst_ni (rst_aon_ni),
4931
4932 // from register interface
4933 .we (aon_com_sel_ctl_0_gated_we),
4934 .wd (aon_com_sel_ctl_0_wdata[0]),
4935
4936 // from internal hardware
4937 .de (1'b0),
4938 .d ('0),
4939
4940 // to internal hardware
4941 .qe (),
4942 .q (reg2hw.com_sel_ctl[0].key0_in_sel.q),
4943 .ds (),
4944
4945 // to register interface (read)
4946 .qs (aon_com_sel_ctl_0_key0_in_sel_0_qs_int)
4947 );
4948
4949 // F[key1_in_sel_0]: 1:1
4950 prim_subreg #(
4951 .DW (1),
4952 .SwAccess(prim_subreg_pkg::SwAccessRW),
4953 .RESVAL (1'h0),
4954 .Mubi (1'b0)
4955 ) u_com_sel_ctl_0_key1_in_sel_0 (
4956 .clk_i (clk_aon_i),
4957 .rst_ni (rst_aon_ni),
4958
4959 // from register interface
4960 .we (aon_com_sel_ctl_0_gated_we),
4961 .wd (aon_com_sel_ctl_0_wdata[1]),
4962
4963 // from internal hardware
4964 .de (1'b0),
4965 .d ('0),
4966
4967 // to internal hardware
4968 .qe (),
4969 .q (reg2hw.com_sel_ctl[0].key1_in_sel.q),
4970 .ds (),
4971
4972 // to register interface (read)
4973 .qs (aon_com_sel_ctl_0_key1_in_sel_0_qs_int)
4974 );
4975
4976 // F[key2_in_sel_0]: 2:2
4977 prim_subreg #(
4978 .DW (1),
4979 .SwAccess(prim_subreg_pkg::SwAccessRW),
4980 .RESVAL (1'h0),
4981 .Mubi (1'b0)
4982 ) u_com_sel_ctl_0_key2_in_sel_0 (
4983 .clk_i (clk_aon_i),
4984 .rst_ni (rst_aon_ni),
4985
4986 // from register interface
4987 .we (aon_com_sel_ctl_0_gated_we),
4988 .wd (aon_com_sel_ctl_0_wdata[2]),
4989
4990 // from internal hardware
4991 .de (1'b0),
4992 .d ('0),
4993
4994 // to internal hardware
4995 .qe (),
4996 .q (reg2hw.com_sel_ctl[0].key2_in_sel.q),
4997 .ds (),
4998
4999 // to register interface (read)
5000 .qs (aon_com_sel_ctl_0_key2_in_sel_0_qs_int)
5001 );
5002
5003 // F[pwrb_in_sel_0]: 3:3
5004 prim_subreg #(
5005 .DW (1),
5006 .SwAccess(prim_subreg_pkg::SwAccessRW),
5007 .RESVAL (1'h0),
5008 .Mubi (1'b0)
5009 ) u_com_sel_ctl_0_pwrb_in_sel_0 (
5010 .clk_i (clk_aon_i),
5011 .rst_ni (rst_aon_ni),
5012
5013 // from register interface
5014 .we (aon_com_sel_ctl_0_gated_we),
5015 .wd (aon_com_sel_ctl_0_wdata[3]),
5016
5017 // from internal hardware
5018 .de (1'b0),
5019 .d ('0),
5020
5021 // to internal hardware
5022 .qe (),
5023 .q (reg2hw.com_sel_ctl[0].pwrb_in_sel.q),
5024 .ds (),
5025
5026 // to register interface (read)
5027 .qs (aon_com_sel_ctl_0_pwrb_in_sel_0_qs_int)
5028 );
5029
5030 // F[ac_present_sel_0]: 4:4
5031 prim_subreg #(
5032 .DW (1),
5033 .SwAccess(prim_subreg_pkg::SwAccessRW),
5034 .RESVAL (1'h0),
5035 .Mubi (1'b0)
5036 ) u_com_sel_ctl_0_ac_present_sel_0 (
5037 .clk_i (clk_aon_i),
5038 .rst_ni (rst_aon_ni),
5039
5040 // from register interface
5041 .we (aon_com_sel_ctl_0_gated_we),
5042 .wd (aon_com_sel_ctl_0_wdata[4]),
5043
5044 // from internal hardware
5045 .de (1'b0),
5046 .d ('0),
5047
5048 // to internal hardware
5049 .qe (),
5050 .q (reg2hw.com_sel_ctl[0].ac_present_sel.q),
5051 .ds (),
5052
5053 // to register interface (read)
5054 .qs (aon_com_sel_ctl_0_ac_present_sel_0_qs_int)
5055 );
5056
5057
5058 // Subregister 1 of Multireg com_sel_ctl
5059 // R[com_sel_ctl_1]: V(False)
5060 // Create REGWEN-gated WE signal
5061 logic aon_com_sel_ctl_1_gated_we;
5062 1/1 assign aon_com_sel_ctl_1_gated_we = aon_com_sel_ctl_1_we & aon_com_sel_ctl_1_regwen;
Tests: T12 T20 T30
5063 // F[key0_in_sel_1]: 0:0
5064 prim_subreg #(
5065 .DW (1),
5066 .SwAccess(prim_subreg_pkg::SwAccessRW),
5067 .RESVAL (1'h0),
5068 .Mubi (1'b0)
5069 ) u_com_sel_ctl_1_key0_in_sel_1 (
5070 .clk_i (clk_aon_i),
5071 .rst_ni (rst_aon_ni),
5072
5073 // from register interface
5074 .we (aon_com_sel_ctl_1_gated_we),
5075 .wd (aon_com_sel_ctl_1_wdata[0]),
5076
5077 // from internal hardware
5078 .de (1'b0),
5079 .d ('0),
5080
5081 // to internal hardware
5082 .qe (),
5083 .q (reg2hw.com_sel_ctl[1].key0_in_sel.q),
5084 .ds (),
5085
5086 // to register interface (read)
5087 .qs (aon_com_sel_ctl_1_key0_in_sel_1_qs_int)
5088 );
5089
5090 // F[key1_in_sel_1]: 1:1
5091 prim_subreg #(
5092 .DW (1),
5093 .SwAccess(prim_subreg_pkg::SwAccessRW),
5094 .RESVAL (1'h0),
5095 .Mubi (1'b0)
5096 ) u_com_sel_ctl_1_key1_in_sel_1 (
5097 .clk_i (clk_aon_i),
5098 .rst_ni (rst_aon_ni),
5099
5100 // from register interface
5101 .we (aon_com_sel_ctl_1_gated_we),
5102 .wd (aon_com_sel_ctl_1_wdata[1]),
5103
5104 // from internal hardware
5105 .de (1'b0),
5106 .d ('0),
5107
5108 // to internal hardware
5109 .qe (),
5110 .q (reg2hw.com_sel_ctl[1].key1_in_sel.q),
5111 .ds (),
5112
5113 // to register interface (read)
5114 .qs (aon_com_sel_ctl_1_key1_in_sel_1_qs_int)
5115 );
5116
5117 // F[key2_in_sel_1]: 2:2
5118 prim_subreg #(
5119 .DW (1),
5120 .SwAccess(prim_subreg_pkg::SwAccessRW),
5121 .RESVAL (1'h0),
5122 .Mubi (1'b0)
5123 ) u_com_sel_ctl_1_key2_in_sel_1 (
5124 .clk_i (clk_aon_i),
5125 .rst_ni (rst_aon_ni),
5126
5127 // from register interface
5128 .we (aon_com_sel_ctl_1_gated_we),
5129 .wd (aon_com_sel_ctl_1_wdata[2]),
5130
5131 // from internal hardware
5132 .de (1'b0),
5133 .d ('0),
5134
5135 // to internal hardware
5136 .qe (),
5137 .q (reg2hw.com_sel_ctl[1].key2_in_sel.q),
5138 .ds (),
5139
5140 // to register interface (read)
5141 .qs (aon_com_sel_ctl_1_key2_in_sel_1_qs_int)
5142 );
5143
5144 // F[pwrb_in_sel_1]: 3:3
5145 prim_subreg #(
5146 .DW (1),
5147 .SwAccess(prim_subreg_pkg::SwAccessRW),
5148 .RESVAL (1'h0),
5149 .Mubi (1'b0)
5150 ) u_com_sel_ctl_1_pwrb_in_sel_1 (
5151 .clk_i (clk_aon_i),
5152 .rst_ni (rst_aon_ni),
5153
5154 // from register interface
5155 .we (aon_com_sel_ctl_1_gated_we),
5156 .wd (aon_com_sel_ctl_1_wdata[3]),
5157
5158 // from internal hardware
5159 .de (1'b0),
5160 .d ('0),
5161
5162 // to internal hardware
5163 .qe (),
5164 .q (reg2hw.com_sel_ctl[1].pwrb_in_sel.q),
5165 .ds (),
5166
5167 // to register interface (read)
5168 .qs (aon_com_sel_ctl_1_pwrb_in_sel_1_qs_int)
5169 );
5170
5171 // F[ac_present_sel_1]: 4:4
5172 prim_subreg #(
5173 .DW (1),
5174 .SwAccess(prim_subreg_pkg::SwAccessRW),
5175 .RESVAL (1'h0),
5176 .Mubi (1'b0)
5177 ) u_com_sel_ctl_1_ac_present_sel_1 (
5178 .clk_i (clk_aon_i),
5179 .rst_ni (rst_aon_ni),
5180
5181 // from register interface
5182 .we (aon_com_sel_ctl_1_gated_we),
5183 .wd (aon_com_sel_ctl_1_wdata[4]),
5184
5185 // from internal hardware
5186 .de (1'b0),
5187 .d ('0),
5188
5189 // to internal hardware
5190 .qe (),
5191 .q (reg2hw.com_sel_ctl[1].ac_present_sel.q),
5192 .ds (),
5193
5194 // to register interface (read)
5195 .qs (aon_com_sel_ctl_1_ac_present_sel_1_qs_int)
5196 );
5197
5198
5199 // Subregister 2 of Multireg com_sel_ctl
5200 // R[com_sel_ctl_2]: V(False)
5201 // Create REGWEN-gated WE signal
5202 logic aon_com_sel_ctl_2_gated_we;
5203 1/1 assign aon_com_sel_ctl_2_gated_we = aon_com_sel_ctl_2_we & aon_com_sel_ctl_2_regwen;
Tests: T12 T20 T30
5204 // F[key0_in_sel_2]: 0:0
5205 prim_subreg #(
5206 .DW (1),
5207 .SwAccess(prim_subreg_pkg::SwAccessRW),
5208 .RESVAL (1'h0),
5209 .Mubi (1'b0)
5210 ) u_com_sel_ctl_2_key0_in_sel_2 (
5211 .clk_i (clk_aon_i),
5212 .rst_ni (rst_aon_ni),
5213
5214 // from register interface
5215 .we (aon_com_sel_ctl_2_gated_we),
5216 .wd (aon_com_sel_ctl_2_wdata[0]),
5217
5218 // from internal hardware
5219 .de (1'b0),
5220 .d ('0),
5221
5222 // to internal hardware
5223 .qe (),
5224 .q (reg2hw.com_sel_ctl[2].key0_in_sel.q),
5225 .ds (),
5226
5227 // to register interface (read)
5228 .qs (aon_com_sel_ctl_2_key0_in_sel_2_qs_int)
5229 );
5230
5231 // F[key1_in_sel_2]: 1:1
5232 prim_subreg #(
5233 .DW (1),
5234 .SwAccess(prim_subreg_pkg::SwAccessRW),
5235 .RESVAL (1'h0),
5236 .Mubi (1'b0)
5237 ) u_com_sel_ctl_2_key1_in_sel_2 (
5238 .clk_i (clk_aon_i),
5239 .rst_ni (rst_aon_ni),
5240
5241 // from register interface
5242 .we (aon_com_sel_ctl_2_gated_we),
5243 .wd (aon_com_sel_ctl_2_wdata[1]),
5244
5245 // from internal hardware
5246 .de (1'b0),
5247 .d ('0),
5248
5249 // to internal hardware
5250 .qe (),
5251 .q (reg2hw.com_sel_ctl[2].key1_in_sel.q),
5252 .ds (),
5253
5254 // to register interface (read)
5255 .qs (aon_com_sel_ctl_2_key1_in_sel_2_qs_int)
5256 );
5257
5258 // F[key2_in_sel_2]: 2:2
5259 prim_subreg #(
5260 .DW (1),
5261 .SwAccess(prim_subreg_pkg::SwAccessRW),
5262 .RESVAL (1'h0),
5263 .Mubi (1'b0)
5264 ) u_com_sel_ctl_2_key2_in_sel_2 (
5265 .clk_i (clk_aon_i),
5266 .rst_ni (rst_aon_ni),
5267
5268 // from register interface
5269 .we (aon_com_sel_ctl_2_gated_we),
5270 .wd (aon_com_sel_ctl_2_wdata[2]),
5271
5272 // from internal hardware
5273 .de (1'b0),
5274 .d ('0),
5275
5276 // to internal hardware
5277 .qe (),
5278 .q (reg2hw.com_sel_ctl[2].key2_in_sel.q),
5279 .ds (),
5280
5281 // to register interface (read)
5282 .qs (aon_com_sel_ctl_2_key2_in_sel_2_qs_int)
5283 );
5284
5285 // F[pwrb_in_sel_2]: 3:3
5286 prim_subreg #(
5287 .DW (1),
5288 .SwAccess(prim_subreg_pkg::SwAccessRW),
5289 .RESVAL (1'h0),
5290 .Mubi (1'b0)
5291 ) u_com_sel_ctl_2_pwrb_in_sel_2 (
5292 .clk_i (clk_aon_i),
5293 .rst_ni (rst_aon_ni),
5294
5295 // from register interface
5296 .we (aon_com_sel_ctl_2_gated_we),
5297 .wd (aon_com_sel_ctl_2_wdata[3]),
5298
5299 // from internal hardware
5300 .de (1'b0),
5301 .d ('0),
5302
5303 // to internal hardware
5304 .qe (),
5305 .q (reg2hw.com_sel_ctl[2].pwrb_in_sel.q),
5306 .ds (),
5307
5308 // to register interface (read)
5309 .qs (aon_com_sel_ctl_2_pwrb_in_sel_2_qs_int)
5310 );
5311
5312 // F[ac_present_sel_2]: 4:4
5313 prim_subreg #(
5314 .DW (1),
5315 .SwAccess(prim_subreg_pkg::SwAccessRW),
5316 .RESVAL (1'h0),
5317 .Mubi (1'b0)
5318 ) u_com_sel_ctl_2_ac_present_sel_2 (
5319 .clk_i (clk_aon_i),
5320 .rst_ni (rst_aon_ni),
5321
5322 // from register interface
5323 .we (aon_com_sel_ctl_2_gated_we),
5324 .wd (aon_com_sel_ctl_2_wdata[4]),
5325
5326 // from internal hardware
5327 .de (1'b0),
5328 .d ('0),
5329
5330 // to internal hardware
5331 .qe (),
5332 .q (reg2hw.com_sel_ctl[2].ac_present_sel.q),
5333 .ds (),
5334
5335 // to register interface (read)
5336 .qs (aon_com_sel_ctl_2_ac_present_sel_2_qs_int)
5337 );
5338
5339
5340 // Subregister 3 of Multireg com_sel_ctl
5341 // R[com_sel_ctl_3]: V(False)
5342 // Create REGWEN-gated WE signal
5343 logic aon_com_sel_ctl_3_gated_we;
5344 1/1 assign aon_com_sel_ctl_3_gated_we = aon_com_sel_ctl_3_we & aon_com_sel_ctl_3_regwen;
Tests: T12 T20 T30
5345 // F[key0_in_sel_3]: 0:0
5346 prim_subreg #(
5347 .DW (1),
5348 .SwAccess(prim_subreg_pkg::SwAccessRW),
5349 .RESVAL (1'h0),
5350 .Mubi (1'b0)
5351 ) u_com_sel_ctl_3_key0_in_sel_3 (
5352 .clk_i (clk_aon_i),
5353 .rst_ni (rst_aon_ni),
5354
5355 // from register interface
5356 .we (aon_com_sel_ctl_3_gated_we),
5357 .wd (aon_com_sel_ctl_3_wdata[0]),
5358
5359 // from internal hardware
5360 .de (1'b0),
5361 .d ('0),
5362
5363 // to internal hardware
5364 .qe (),
5365 .q (reg2hw.com_sel_ctl[3].key0_in_sel.q),
5366 .ds (),
5367
5368 // to register interface (read)
5369 .qs (aon_com_sel_ctl_3_key0_in_sel_3_qs_int)
5370 );
5371
5372 // F[key1_in_sel_3]: 1:1
5373 prim_subreg #(
5374 .DW (1),
5375 .SwAccess(prim_subreg_pkg::SwAccessRW),
5376 .RESVAL (1'h0),
5377 .Mubi (1'b0)
5378 ) u_com_sel_ctl_3_key1_in_sel_3 (
5379 .clk_i (clk_aon_i),
5380 .rst_ni (rst_aon_ni),
5381
5382 // from register interface
5383 .we (aon_com_sel_ctl_3_gated_we),
5384 .wd (aon_com_sel_ctl_3_wdata[1]),
5385
5386 // from internal hardware
5387 .de (1'b0),
5388 .d ('0),
5389
5390 // to internal hardware
5391 .qe (),
5392 .q (reg2hw.com_sel_ctl[3].key1_in_sel.q),
5393 .ds (),
5394
5395 // to register interface (read)
5396 .qs (aon_com_sel_ctl_3_key1_in_sel_3_qs_int)
5397 );
5398
5399 // F[key2_in_sel_3]: 2:2
5400 prim_subreg #(
5401 .DW (1),
5402 .SwAccess(prim_subreg_pkg::SwAccessRW),
5403 .RESVAL (1'h0),
5404 .Mubi (1'b0)
5405 ) u_com_sel_ctl_3_key2_in_sel_3 (
5406 .clk_i (clk_aon_i),
5407 .rst_ni (rst_aon_ni),
5408
5409 // from register interface
5410 .we (aon_com_sel_ctl_3_gated_we),
5411 .wd (aon_com_sel_ctl_3_wdata[2]),
5412
5413 // from internal hardware
5414 .de (1'b0),
5415 .d ('0),
5416
5417 // to internal hardware
5418 .qe (),
5419 .q (reg2hw.com_sel_ctl[3].key2_in_sel.q),
5420 .ds (),
5421
5422 // to register interface (read)
5423 .qs (aon_com_sel_ctl_3_key2_in_sel_3_qs_int)
5424 );
5425
5426 // F[pwrb_in_sel_3]: 3:3
5427 prim_subreg #(
5428 .DW (1),
5429 .SwAccess(prim_subreg_pkg::SwAccessRW),
5430 .RESVAL (1'h0),
5431 .Mubi (1'b0)
5432 ) u_com_sel_ctl_3_pwrb_in_sel_3 (
5433 .clk_i (clk_aon_i),
5434 .rst_ni (rst_aon_ni),
5435
5436 // from register interface
5437 .we (aon_com_sel_ctl_3_gated_we),
5438 .wd (aon_com_sel_ctl_3_wdata[3]),
5439
5440 // from internal hardware
5441 .de (1'b0),
5442 .d ('0),
5443
5444 // to internal hardware
5445 .qe (),
5446 .q (reg2hw.com_sel_ctl[3].pwrb_in_sel.q),
5447 .ds (),
5448
5449 // to register interface (read)
5450 .qs (aon_com_sel_ctl_3_pwrb_in_sel_3_qs_int)
5451 );
5452
5453 // F[ac_present_sel_3]: 4:4
5454 prim_subreg #(
5455 .DW (1),
5456 .SwAccess(prim_subreg_pkg::SwAccessRW),
5457 .RESVAL (1'h0),
5458 .Mubi (1'b0)
5459 ) u_com_sel_ctl_3_ac_present_sel_3 (
5460 .clk_i (clk_aon_i),
5461 .rst_ni (rst_aon_ni),
5462
5463 // from register interface
5464 .we (aon_com_sel_ctl_3_gated_we),
5465 .wd (aon_com_sel_ctl_3_wdata[4]),
5466
5467 // from internal hardware
5468 .de (1'b0),
5469 .d ('0),
5470
5471 // to internal hardware
5472 .qe (),
5473 .q (reg2hw.com_sel_ctl[3].ac_present_sel.q),
5474 .ds (),
5475
5476 // to register interface (read)
5477 .qs (aon_com_sel_ctl_3_ac_present_sel_3_qs_int)
5478 );
5479
5480
5481 // Subregister 0 of Multireg com_det_ctl
5482 // R[com_det_ctl_0]: V(False)
5483 // Create REGWEN-gated WE signal
5484 logic aon_com_det_ctl_0_gated_we;
5485 1/1 assign aon_com_det_ctl_0_gated_we = aon_com_det_ctl_0_we & aon_com_det_ctl_0_regwen;
Tests: T1 T2 T8
5486 prim_subreg #(
5487 .DW (32),
5488 .SwAccess(prim_subreg_pkg::SwAccessRW),
5489 .RESVAL (32'h0),
5490 .Mubi (1'b0)
5491 ) u_com_det_ctl_0 (
5492 .clk_i (clk_aon_i),
5493 .rst_ni (rst_aon_ni),
5494
5495 // from register interface
5496 .we (aon_com_det_ctl_0_gated_we),
5497 .wd (aon_com_det_ctl_0_wdata[31:0]),
5498
5499 // from internal hardware
5500 .de (1'b0),
5501 .d ('0),
5502
5503 // to internal hardware
5504 .qe (),
5505 .q (reg2hw.com_det_ctl[0].q),
5506 .ds (),
5507
5508 // to register interface (read)
5509 .qs (aon_com_det_ctl_0_qs_int)
5510 );
5511
5512
5513 // Subregister 1 of Multireg com_det_ctl
5514 // R[com_det_ctl_1]: V(False)
5515 // Create REGWEN-gated WE signal
5516 logic aon_com_det_ctl_1_gated_we;
5517 1/1 assign aon_com_det_ctl_1_gated_we = aon_com_det_ctl_1_we & aon_com_det_ctl_1_regwen;
Tests: T12 T20 T30
5518 prim_subreg #(
5519 .DW (32),
5520 .SwAccess(prim_subreg_pkg::SwAccessRW),
5521 .RESVAL (32'h0),
5522 .Mubi (1'b0)
5523 ) u_com_det_ctl_1 (
5524 .clk_i (clk_aon_i),
5525 .rst_ni (rst_aon_ni),
5526
5527 // from register interface
5528 .we (aon_com_det_ctl_1_gated_we),
5529 .wd (aon_com_det_ctl_1_wdata[31:0]),
5530
5531 // from internal hardware
5532 .de (1'b0),
5533 .d ('0),
5534
5535 // to internal hardware
5536 .qe (),
5537 .q (reg2hw.com_det_ctl[1].q),
5538 .ds (),
5539
5540 // to register interface (read)
5541 .qs (aon_com_det_ctl_1_qs_int)
5542 );
5543
5544
5545 // Subregister 2 of Multireg com_det_ctl
5546 // R[com_det_ctl_2]: V(False)
5547 // Create REGWEN-gated WE signal
5548 logic aon_com_det_ctl_2_gated_we;
5549 1/1 assign aon_com_det_ctl_2_gated_we = aon_com_det_ctl_2_we & aon_com_det_ctl_2_regwen;
Tests: T12 T20 T30
5550 prim_subreg #(
5551 .DW (32),
5552 .SwAccess(prim_subreg_pkg::SwAccessRW),
5553 .RESVAL (32'h0),
5554 .Mubi (1'b0)
5555 ) u_com_det_ctl_2 (
5556 .clk_i (clk_aon_i),
5557 .rst_ni (rst_aon_ni),
5558
5559 // from register interface
5560 .we (aon_com_det_ctl_2_gated_we),
5561 .wd (aon_com_det_ctl_2_wdata[31:0]),
5562
5563 // from internal hardware
5564 .de (1'b0),
5565 .d ('0),
5566
5567 // to internal hardware
5568 .qe (),
5569 .q (reg2hw.com_det_ctl[2].q),
5570 .ds (),
5571
5572 // to register interface (read)
5573 .qs (aon_com_det_ctl_2_qs_int)
5574 );
5575
5576
5577 // Subregister 3 of Multireg com_det_ctl
5578 // R[com_det_ctl_3]: V(False)
5579 // Create REGWEN-gated WE signal
5580 logic aon_com_det_ctl_3_gated_we;
5581 1/1 assign aon_com_det_ctl_3_gated_we = aon_com_det_ctl_3_we & aon_com_det_ctl_3_regwen;
Tests: T12 T20 T30
5582 prim_subreg #(
5583 .DW (32),
5584 .SwAccess(prim_subreg_pkg::SwAccessRW),
5585 .RESVAL (32'h0),
5586 .Mubi (1'b0)
5587 ) u_com_det_ctl_3 (
5588 .clk_i (clk_aon_i),
5589 .rst_ni (rst_aon_ni),
5590
5591 // from register interface
5592 .we (aon_com_det_ctl_3_gated_we),
5593 .wd (aon_com_det_ctl_3_wdata[31:0]),
5594
5595 // from internal hardware
5596 .de (1'b0),
5597 .d ('0),
5598
5599 // to internal hardware
5600 .qe (),
5601 .q (reg2hw.com_det_ctl[3].q),
5602 .ds (),
5603
5604 // to register interface (read)
5605 .qs (aon_com_det_ctl_3_qs_int)
5606 );
5607
5608
5609 // Subregister 0 of Multireg com_out_ctl
5610 // R[com_out_ctl_0]: V(False)
5611 // Create REGWEN-gated WE signal
5612 logic aon_com_out_ctl_0_gated_we;
5613 1/1 assign aon_com_out_ctl_0_gated_we = aon_com_out_ctl_0_we & aon_com_out_ctl_0_regwen;
Tests: T1 T2 T8
5614 // F[bat_disable_0]: 0:0
5615 prim_subreg #(
5616 .DW (1),
5617 .SwAccess(prim_subreg_pkg::SwAccessRW),
5618 .RESVAL (1'h0),
5619 .Mubi (1'b0)
5620 ) u_com_out_ctl_0_bat_disable_0 (
5621 .clk_i (clk_aon_i),
5622 .rst_ni (rst_aon_ni),
5623
5624 // from register interface
5625 .we (aon_com_out_ctl_0_gated_we),
5626 .wd (aon_com_out_ctl_0_wdata[0]),
5627
5628 // from internal hardware
5629 .de (1'b0),
5630 .d ('0),
5631
5632 // to internal hardware
5633 .qe (),
5634 .q (reg2hw.com_out_ctl[0].bat_disable.q),
5635 .ds (),
5636
5637 // to register interface (read)
5638 .qs (aon_com_out_ctl_0_bat_disable_0_qs_int)
5639 );
5640
5641 // F[interrupt_0]: 1:1
5642 prim_subreg #(
5643 .DW (1),
5644 .SwAccess(prim_subreg_pkg::SwAccessRW),
5645 .RESVAL (1'h0),
5646 .Mubi (1'b0)
5647 ) u_com_out_ctl_0_interrupt_0 (
5648 .clk_i (clk_aon_i),
5649 .rst_ni (rst_aon_ni),
5650
5651 // from register interface
5652 .we (aon_com_out_ctl_0_gated_we),
5653 .wd (aon_com_out_ctl_0_wdata[1]),
5654
5655 // from internal hardware
5656 .de (1'b0),
5657 .d ('0),
5658
5659 // to internal hardware
5660 .qe (),
5661 .q (reg2hw.com_out_ctl[0].interrupt.q),
5662 .ds (),
5663
5664 // to register interface (read)
5665 .qs (aon_com_out_ctl_0_interrupt_0_qs_int)
5666 );
5667
5668 // F[ec_rst_0]: 2:2
5669 prim_subreg #(
5670 .DW (1),
5671 .SwAccess(prim_subreg_pkg::SwAccessRW),
5672 .RESVAL (1'h0),
5673 .Mubi (1'b0)
5674 ) u_com_out_ctl_0_ec_rst_0 (
5675 .clk_i (clk_aon_i),
5676 .rst_ni (rst_aon_ni),
5677
5678 // from register interface
5679 .we (aon_com_out_ctl_0_gated_we),
5680 .wd (aon_com_out_ctl_0_wdata[2]),
5681
5682 // from internal hardware
5683 .de (1'b0),
5684 .d ('0),
5685
5686 // to internal hardware
5687 .qe (),
5688 .q (reg2hw.com_out_ctl[0].ec_rst.q),
5689 .ds (),
5690
5691 // to register interface (read)
5692 .qs (aon_com_out_ctl_0_ec_rst_0_qs_int)
5693 );
5694
5695 // F[rst_req_0]: 3:3
5696 prim_subreg #(
5697 .DW (1),
5698 .SwAccess(prim_subreg_pkg::SwAccessRW),
5699 .RESVAL (1'h0),
5700 .Mubi (1'b0)
5701 ) u_com_out_ctl_0_rst_req_0 (
5702 .clk_i (clk_aon_i),
5703 .rst_ni (rst_aon_ni),
5704
5705 // from register interface
5706 .we (aon_com_out_ctl_0_gated_we),
5707 .wd (aon_com_out_ctl_0_wdata[3]),
5708
5709 // from internal hardware
5710 .de (1'b0),
5711 .d ('0),
5712
5713 // to internal hardware
5714 .qe (),
5715 .q (reg2hw.com_out_ctl[0].rst_req.q),
5716 .ds (),
5717
5718 // to register interface (read)
5719 .qs (aon_com_out_ctl_0_rst_req_0_qs_int)
5720 );
5721
5722
5723 // Subregister 1 of Multireg com_out_ctl
5724 // R[com_out_ctl_1]: V(False)
5725 // Create REGWEN-gated WE signal
5726 logic aon_com_out_ctl_1_gated_we;
5727 1/1 assign aon_com_out_ctl_1_gated_we = aon_com_out_ctl_1_we & aon_com_out_ctl_1_regwen;
Tests: T12 T20 T30
5728 // F[bat_disable_1]: 0:0
5729 prim_subreg #(
5730 .DW (1),
5731 .SwAccess(prim_subreg_pkg::SwAccessRW),
5732 .RESVAL (1'h0),
5733 .Mubi (1'b0)
5734 ) u_com_out_ctl_1_bat_disable_1 (
5735 .clk_i (clk_aon_i),
5736 .rst_ni (rst_aon_ni),
5737
5738 // from register interface
5739 .we (aon_com_out_ctl_1_gated_we),
5740 .wd (aon_com_out_ctl_1_wdata[0]),
5741
5742 // from internal hardware
5743 .de (1'b0),
5744 .d ('0),
5745
5746 // to internal hardware
5747 .qe (),
5748 .q (reg2hw.com_out_ctl[1].bat_disable.q),
5749 .ds (),
5750
5751 // to register interface (read)
5752 .qs (aon_com_out_ctl_1_bat_disable_1_qs_int)
5753 );
5754
5755 // F[interrupt_1]: 1:1
5756 prim_subreg #(
5757 .DW (1),
5758 .SwAccess(prim_subreg_pkg::SwAccessRW),
5759 .RESVAL (1'h0),
5760 .Mubi (1'b0)
5761 ) u_com_out_ctl_1_interrupt_1 (
5762 .clk_i (clk_aon_i),
5763 .rst_ni (rst_aon_ni),
5764
5765 // from register interface
5766 .we (aon_com_out_ctl_1_gated_we),
5767 .wd (aon_com_out_ctl_1_wdata[1]),
5768
5769 // from internal hardware
5770 .de (1'b0),
5771 .d ('0),
5772
5773 // to internal hardware
5774 .qe (),
5775 .q (reg2hw.com_out_ctl[1].interrupt.q),
5776 .ds (),
5777
5778 // to register interface (read)
5779 .qs (aon_com_out_ctl_1_interrupt_1_qs_int)
5780 );
5781
5782 // F[ec_rst_1]: 2:2
5783 prim_subreg #(
5784 .DW (1),
5785 .SwAccess(prim_subreg_pkg::SwAccessRW),
5786 .RESVAL (1'h0),
5787 .Mubi (1'b0)
5788 ) u_com_out_ctl_1_ec_rst_1 (
5789 .clk_i (clk_aon_i),
5790 .rst_ni (rst_aon_ni),
5791
5792 // from register interface
5793 .we (aon_com_out_ctl_1_gated_we),
5794 .wd (aon_com_out_ctl_1_wdata[2]),
5795
5796 // from internal hardware
5797 .de (1'b0),
5798 .d ('0),
5799
5800 // to internal hardware
5801 .qe (),
5802 .q (reg2hw.com_out_ctl[1].ec_rst.q),
5803 .ds (),
5804
5805 // to register interface (read)
5806 .qs (aon_com_out_ctl_1_ec_rst_1_qs_int)
5807 );
5808
5809 // F[rst_req_1]: 3:3
5810 prim_subreg #(
5811 .DW (1),
5812 .SwAccess(prim_subreg_pkg::SwAccessRW),
5813 .RESVAL (1'h0),
5814 .Mubi (1'b0)
5815 ) u_com_out_ctl_1_rst_req_1 (
5816 .clk_i (clk_aon_i),
5817 .rst_ni (rst_aon_ni),
5818
5819 // from register interface
5820 .we (aon_com_out_ctl_1_gated_we),
5821 .wd (aon_com_out_ctl_1_wdata[3]),
5822
5823 // from internal hardware
5824 .de (1'b0),
5825 .d ('0),
5826
5827 // to internal hardware
5828 .qe (),
5829 .q (reg2hw.com_out_ctl[1].rst_req.q),
5830 .ds (),
5831
5832 // to register interface (read)
5833 .qs (aon_com_out_ctl_1_rst_req_1_qs_int)
5834 );
5835
5836
5837 // Subregister 2 of Multireg com_out_ctl
5838 // R[com_out_ctl_2]: V(False)
5839 // Create REGWEN-gated WE signal
5840 logic aon_com_out_ctl_2_gated_we;
5841 1/1 assign aon_com_out_ctl_2_gated_we = aon_com_out_ctl_2_we & aon_com_out_ctl_2_regwen;
Tests: T12 T20 T30
5842 // F[bat_disable_2]: 0:0
5843 prim_subreg #(
5844 .DW (1),
5845 .SwAccess(prim_subreg_pkg::SwAccessRW),
5846 .RESVAL (1'h0),
5847 .Mubi (1'b0)
5848 ) u_com_out_ctl_2_bat_disable_2 (
5849 .clk_i (clk_aon_i),
5850 .rst_ni (rst_aon_ni),
5851
5852 // from register interface
5853 .we (aon_com_out_ctl_2_gated_we),
5854 .wd (aon_com_out_ctl_2_wdata[0]),
5855
5856 // from internal hardware
5857 .de (1'b0),
5858 .d ('0),
5859
5860 // to internal hardware
5861 .qe (),
5862 .q (reg2hw.com_out_ctl[2].bat_disable.q),
5863 .ds (),
5864
5865 // to register interface (read)
5866 .qs (aon_com_out_ctl_2_bat_disable_2_qs_int)
5867 );
5868
5869 // F[interrupt_2]: 1:1
5870 prim_subreg #(
5871 .DW (1),
5872 .SwAccess(prim_subreg_pkg::SwAccessRW),
5873 .RESVAL (1'h0),
5874 .Mubi (1'b0)
5875 ) u_com_out_ctl_2_interrupt_2 (
5876 .clk_i (clk_aon_i),
5877 .rst_ni (rst_aon_ni),
5878
5879 // from register interface
5880 .we (aon_com_out_ctl_2_gated_we),
5881 .wd (aon_com_out_ctl_2_wdata[1]),
5882
5883 // from internal hardware
5884 .de (1'b0),
5885 .d ('0),
5886
5887 // to internal hardware
5888 .qe (),
5889 .q (reg2hw.com_out_ctl[2].interrupt.q),
5890 .ds (),
5891
5892 // to register interface (read)
5893 .qs (aon_com_out_ctl_2_interrupt_2_qs_int)
5894 );
5895
5896 // F[ec_rst_2]: 2:2
5897 prim_subreg #(
5898 .DW (1),
5899 .SwAccess(prim_subreg_pkg::SwAccessRW),
5900 .RESVAL (1'h0),
5901 .Mubi (1'b0)
5902 ) u_com_out_ctl_2_ec_rst_2 (
5903 .clk_i (clk_aon_i),
5904 .rst_ni (rst_aon_ni),
5905
5906 // from register interface
5907 .we (aon_com_out_ctl_2_gated_we),
5908 .wd (aon_com_out_ctl_2_wdata[2]),
5909
5910 // from internal hardware
5911 .de (1'b0),
5912 .d ('0),
5913
5914 // to internal hardware
5915 .qe (),
5916 .q (reg2hw.com_out_ctl[2].ec_rst.q),
5917 .ds (),
5918
5919 // to register interface (read)
5920 .qs (aon_com_out_ctl_2_ec_rst_2_qs_int)
5921 );
5922
5923 // F[rst_req_2]: 3:3
5924 prim_subreg #(
5925 .DW (1),
5926 .SwAccess(prim_subreg_pkg::SwAccessRW),
5927 .RESVAL (1'h0),
5928 .Mubi (1'b0)
5929 ) u_com_out_ctl_2_rst_req_2 (
5930 .clk_i (clk_aon_i),
5931 .rst_ni (rst_aon_ni),
5932
5933 // from register interface
5934 .we (aon_com_out_ctl_2_gated_we),
5935 .wd (aon_com_out_ctl_2_wdata[3]),
5936
5937 // from internal hardware
5938 .de (1'b0),
5939 .d ('0),
5940
5941 // to internal hardware
5942 .qe (),
5943 .q (reg2hw.com_out_ctl[2].rst_req.q),
5944 .ds (),
5945
5946 // to register interface (read)
5947 .qs (aon_com_out_ctl_2_rst_req_2_qs_int)
5948 );
5949
5950
5951 // Subregister 3 of Multireg com_out_ctl
5952 // R[com_out_ctl_3]: V(False)
5953 // Create REGWEN-gated WE signal
5954 logic aon_com_out_ctl_3_gated_we;
5955 1/1 assign aon_com_out_ctl_3_gated_we = aon_com_out_ctl_3_we & aon_com_out_ctl_3_regwen;
Tests: T12 T20 T30
5956 // F[bat_disable_3]: 0:0
5957 prim_subreg #(
5958 .DW (1),
5959 .SwAccess(prim_subreg_pkg::SwAccessRW),
5960 .RESVAL (1'h0),
5961 .Mubi (1'b0)
5962 ) u_com_out_ctl_3_bat_disable_3 (
5963 .clk_i (clk_aon_i),
5964 .rst_ni (rst_aon_ni),
5965
5966 // from register interface
5967 .we (aon_com_out_ctl_3_gated_we),
5968 .wd (aon_com_out_ctl_3_wdata[0]),
5969
5970 // from internal hardware
5971 .de (1'b0),
5972 .d ('0),
5973
5974 // to internal hardware
5975 .qe (),
5976 .q (reg2hw.com_out_ctl[3].bat_disable.q),
5977 .ds (),
5978
5979 // to register interface (read)
5980 .qs (aon_com_out_ctl_3_bat_disable_3_qs_int)
5981 );
5982
5983 // F[interrupt_3]: 1:1
5984 prim_subreg #(
5985 .DW (1),
5986 .SwAccess(prim_subreg_pkg::SwAccessRW),
5987 .RESVAL (1'h0),
5988 .Mubi (1'b0)
5989 ) u_com_out_ctl_3_interrupt_3 (
5990 .clk_i (clk_aon_i),
5991 .rst_ni (rst_aon_ni),
5992
5993 // from register interface
5994 .we (aon_com_out_ctl_3_gated_we),
5995 .wd (aon_com_out_ctl_3_wdata[1]),
5996
5997 // from internal hardware
5998 .de (1'b0),
5999 .d ('0),
6000
6001 // to internal hardware
6002 .qe (),
6003 .q (reg2hw.com_out_ctl[3].interrupt.q),
6004 .ds (),
6005
6006 // to register interface (read)
6007 .qs (aon_com_out_ctl_3_interrupt_3_qs_int)
6008 );
6009
6010 // F[ec_rst_3]: 2:2
6011 prim_subreg #(
6012 .DW (1),
6013 .SwAccess(prim_subreg_pkg::SwAccessRW),
6014 .RESVAL (1'h0),
6015 .Mubi (1'b0)
6016 ) u_com_out_ctl_3_ec_rst_3 (
6017 .clk_i (clk_aon_i),
6018 .rst_ni (rst_aon_ni),
6019
6020 // from register interface
6021 .we (aon_com_out_ctl_3_gated_we),
6022 .wd (aon_com_out_ctl_3_wdata[2]),
6023
6024 // from internal hardware
6025 .de (1'b0),
6026 .d ('0),
6027
6028 // to internal hardware
6029 .qe (),
6030 .q (reg2hw.com_out_ctl[3].ec_rst.q),
6031 .ds (),
6032
6033 // to register interface (read)
6034 .qs (aon_com_out_ctl_3_ec_rst_3_qs_int)
6035 );
6036
6037 // F[rst_req_3]: 3:3
6038 prim_subreg #(
6039 .DW (1),
6040 .SwAccess(prim_subreg_pkg::SwAccessRW),
6041 .RESVAL (1'h0),
6042 .Mubi (1'b0)
6043 ) u_com_out_ctl_3_rst_req_3 (
6044 .clk_i (clk_aon_i),
6045 .rst_ni (rst_aon_ni),
6046
6047 // from register interface
6048 .we (aon_com_out_ctl_3_gated_we),
6049 .wd (aon_com_out_ctl_3_wdata[3]),
6050
6051 // from internal hardware
6052 .de (1'b0),
6053 .d ('0),
6054
6055 // to internal hardware
6056 .qe (),
6057 .q (reg2hw.com_out_ctl[3].rst_req.q),
6058 .ds (),
6059
6060 // to register interface (read)
6061 .qs (aon_com_out_ctl_3_rst_req_3_qs_int)
6062 );
6063
6064
6065 // R[combo_intr_status]: V(False)
6066 // F[combo0_h2l]: 0:0
6067 prim_subreg #(
6068 .DW (1),
6069 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6070 .RESVAL (1'h0),
6071 .Mubi (1'b0)
6072 ) u_combo_intr_status_combo0_h2l (
6073 .clk_i (clk_i),
6074 .rst_ni (rst_ni),
6075
6076 // from register interface
6077 .we (combo_intr_status_we),
6078 .wd (combo_intr_status_combo0_h2l_wd),
6079
6080 // from internal hardware
6081 .de (hw2reg.combo_intr_status.combo0_h2l.de),
6082 .d (hw2reg.combo_intr_status.combo0_h2l.d),
6083
6084 // to internal hardware
6085 .qe (),
6086 .q (reg2hw.combo_intr_status.combo0_h2l.q),
6087 .ds (),
6088
6089 // to register interface (read)
6090 .qs (combo_intr_status_combo0_h2l_qs)
6091 );
6092
6093 // F[combo1_h2l]: 1:1
6094 prim_subreg #(
6095 .DW (1),
6096 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6097 .RESVAL (1'h0),
6098 .Mubi (1'b0)
6099 ) u_combo_intr_status_combo1_h2l (
6100 .clk_i (clk_i),
6101 .rst_ni (rst_ni),
6102
6103 // from register interface
6104 .we (combo_intr_status_we),
6105 .wd (combo_intr_status_combo1_h2l_wd),
6106
6107 // from internal hardware
6108 .de (hw2reg.combo_intr_status.combo1_h2l.de),
6109 .d (hw2reg.combo_intr_status.combo1_h2l.d),
6110
6111 // to internal hardware
6112 .qe (),
6113 .q (reg2hw.combo_intr_status.combo1_h2l.q),
6114 .ds (),
6115
6116 // to register interface (read)
6117 .qs (combo_intr_status_combo1_h2l_qs)
6118 );
6119
6120 // F[combo2_h2l]: 2:2
6121 prim_subreg #(
6122 .DW (1),
6123 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6124 .RESVAL (1'h0),
6125 .Mubi (1'b0)
6126 ) u_combo_intr_status_combo2_h2l (
6127 .clk_i (clk_i),
6128 .rst_ni (rst_ni),
6129
6130 // from register interface
6131 .we (combo_intr_status_we),
6132 .wd (combo_intr_status_combo2_h2l_wd),
6133
6134 // from internal hardware
6135 .de (hw2reg.combo_intr_status.combo2_h2l.de),
6136 .d (hw2reg.combo_intr_status.combo2_h2l.d),
6137
6138 // to internal hardware
6139 .qe (),
6140 .q (reg2hw.combo_intr_status.combo2_h2l.q),
6141 .ds (),
6142
6143 // to register interface (read)
6144 .qs (combo_intr_status_combo2_h2l_qs)
6145 );
6146
6147 // F[combo3_h2l]: 3:3
6148 prim_subreg #(
6149 .DW (1),
6150 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6151 .RESVAL (1'h0),
6152 .Mubi (1'b0)
6153 ) u_combo_intr_status_combo3_h2l (
6154 .clk_i (clk_i),
6155 .rst_ni (rst_ni),
6156
6157 // from register interface
6158 .we (combo_intr_status_we),
6159 .wd (combo_intr_status_combo3_h2l_wd),
6160
6161 // from internal hardware
6162 .de (hw2reg.combo_intr_status.combo3_h2l.de),
6163 .d (hw2reg.combo_intr_status.combo3_h2l.d),
6164
6165 // to internal hardware
6166 .qe (),
6167 .q (reg2hw.combo_intr_status.combo3_h2l.q),
6168 .ds (),
6169
6170 // to register interface (read)
6171 .qs (combo_intr_status_combo3_h2l_qs)
6172 );
6173
6174
6175 // R[key_intr_status]: V(False)
6176 // F[pwrb_h2l]: 0:0
6177 prim_subreg #(
6178 .DW (1),
6179 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6180 .RESVAL (1'h0),
6181 .Mubi (1'b0)
6182 ) u_key_intr_status_pwrb_h2l (
6183 .clk_i (clk_i),
6184 .rst_ni (rst_ni),
6185
6186 // from register interface
6187 .we (key_intr_status_we),
6188 .wd (key_intr_status_pwrb_h2l_wd),
6189
6190 // from internal hardware
6191 .de (hw2reg.key_intr_status.pwrb_h2l.de),
6192 .d (hw2reg.key_intr_status.pwrb_h2l.d),
6193
6194 // to internal hardware
6195 .qe (),
6196 .q (reg2hw.key_intr_status.pwrb_h2l.q),
6197 .ds (),
6198
6199 // to register interface (read)
6200 .qs (key_intr_status_pwrb_h2l_qs)
6201 );
6202
6203 // F[key0_in_h2l]: 1:1
6204 prim_subreg #(
6205 .DW (1),
6206 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6207 .RESVAL (1'h0),
6208 .Mubi (1'b0)
6209 ) u_key_intr_status_key0_in_h2l (
6210 .clk_i (clk_i),
6211 .rst_ni (rst_ni),
6212
6213 // from register interface
6214 .we (key_intr_status_we),
6215 .wd (key_intr_status_key0_in_h2l_wd),
6216
6217 // from internal hardware
6218 .de (hw2reg.key_intr_status.key0_in_h2l.de),
6219 .d (hw2reg.key_intr_status.key0_in_h2l.d),
6220
6221 // to internal hardware
6222 .qe (),
6223 .q (reg2hw.key_intr_status.key0_in_h2l.q),
6224 .ds (),
6225
6226 // to register interface (read)
6227 .qs (key_intr_status_key0_in_h2l_qs)
6228 );
6229
6230 // F[key1_in_h2l]: 2:2
6231 prim_subreg #(
6232 .DW (1),
6233 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6234 .RESVAL (1'h0),
6235 .Mubi (1'b0)
6236 ) u_key_intr_status_key1_in_h2l (
6237 .clk_i (clk_i),
6238 .rst_ni (rst_ni),
6239
6240 // from register interface
6241 .we (key_intr_status_we),
6242 .wd (key_intr_status_key1_in_h2l_wd),
6243
6244 // from internal hardware
6245 .de (hw2reg.key_intr_status.key1_in_h2l.de),
6246 .d (hw2reg.key_intr_status.key1_in_h2l.d),
6247
6248 // to internal hardware
6249 .qe (),
6250 .q (reg2hw.key_intr_status.key1_in_h2l.q),
6251 .ds (),
6252
6253 // to register interface (read)
6254 .qs (key_intr_status_key1_in_h2l_qs)
6255 );
6256
6257 // F[key2_in_h2l]: 3:3
6258 prim_subreg #(
6259 .DW (1),
6260 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6261 .RESVAL (1'h0),
6262 .Mubi (1'b0)
6263 ) u_key_intr_status_key2_in_h2l (
6264 .clk_i (clk_i),
6265 .rst_ni (rst_ni),
6266
6267 // from register interface
6268 .we (key_intr_status_we),
6269 .wd (key_intr_status_key2_in_h2l_wd),
6270
6271 // from internal hardware
6272 .de (hw2reg.key_intr_status.key2_in_h2l.de),
6273 .d (hw2reg.key_intr_status.key2_in_h2l.d),
6274
6275 // to internal hardware
6276 .qe (),
6277 .q (reg2hw.key_intr_status.key2_in_h2l.q),
6278 .ds (),
6279
6280 // to register interface (read)
6281 .qs (key_intr_status_key2_in_h2l_qs)
6282 );
6283
6284 // F[ac_present_h2l]: 4:4
6285 prim_subreg #(
6286 .DW (1),
6287 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6288 .RESVAL (1'h0),
6289 .Mubi (1'b0)
6290 ) u_key_intr_status_ac_present_h2l (
6291 .clk_i (clk_i),
6292 .rst_ni (rst_ni),
6293
6294 // from register interface
6295 .we (key_intr_status_we),
6296 .wd (key_intr_status_ac_present_h2l_wd),
6297
6298 // from internal hardware
6299 .de (hw2reg.key_intr_status.ac_present_h2l.de),
6300 .d (hw2reg.key_intr_status.ac_present_h2l.d),
6301
6302 // to internal hardware
6303 .qe (),
6304 .q (reg2hw.key_intr_status.ac_present_h2l.q),
6305 .ds (),
6306
6307 // to register interface (read)
6308 .qs (key_intr_status_ac_present_h2l_qs)
6309 );
6310
6311 // F[ec_rst_l_h2l]: 5:5
6312 prim_subreg #(
6313 .DW (1),
6314 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6315 .RESVAL (1'h0),
6316 .Mubi (1'b0)
6317 ) u_key_intr_status_ec_rst_l_h2l (
6318 .clk_i (clk_i),
6319 .rst_ni (rst_ni),
6320
6321 // from register interface
6322 .we (key_intr_status_we),
6323 .wd (key_intr_status_ec_rst_l_h2l_wd),
6324
6325 // from internal hardware
6326 .de (hw2reg.key_intr_status.ec_rst_l_h2l.de),
6327 .d (hw2reg.key_intr_status.ec_rst_l_h2l.d),
6328
6329 // to internal hardware
6330 .qe (),
6331 .q (reg2hw.key_intr_status.ec_rst_l_h2l.q),
6332 .ds (),
6333
6334 // to register interface (read)
6335 .qs (key_intr_status_ec_rst_l_h2l_qs)
6336 );
6337
6338 // F[flash_wp_l_h2l]: 6:6
6339 prim_subreg #(
6340 .DW (1),
6341 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6342 .RESVAL (1'h0),
6343 .Mubi (1'b0)
6344 ) u_key_intr_status_flash_wp_l_h2l (
6345 .clk_i (clk_i),
6346 .rst_ni (rst_ni),
6347
6348 // from register interface
6349 .we (key_intr_status_we),
6350 .wd (key_intr_status_flash_wp_l_h2l_wd),
6351
6352 // from internal hardware
6353 .de (hw2reg.key_intr_status.flash_wp_l_h2l.de),
6354 .d (hw2reg.key_intr_status.flash_wp_l_h2l.d),
6355
6356 // to internal hardware
6357 .qe (),
6358 .q (reg2hw.key_intr_status.flash_wp_l_h2l.q),
6359 .ds (),
6360
6361 // to register interface (read)
6362 .qs (key_intr_status_flash_wp_l_h2l_qs)
6363 );
6364
6365 // F[pwrb_l2h]: 7:7
6366 prim_subreg #(
6367 .DW (1),
6368 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6369 .RESVAL (1'h0),
6370 .Mubi (1'b0)
6371 ) u_key_intr_status_pwrb_l2h (
6372 .clk_i (clk_i),
6373 .rst_ni (rst_ni),
6374
6375 // from register interface
6376 .we (key_intr_status_we),
6377 .wd (key_intr_status_pwrb_l2h_wd),
6378
6379 // from internal hardware
6380 .de (hw2reg.key_intr_status.pwrb_l2h.de),
6381 .d (hw2reg.key_intr_status.pwrb_l2h.d),
6382
6383 // to internal hardware
6384 .qe (),
6385 .q (reg2hw.key_intr_status.pwrb_l2h.q),
6386 .ds (),
6387
6388 // to register interface (read)
6389 .qs (key_intr_status_pwrb_l2h_qs)
6390 );
6391
6392 // F[key0_in_l2h]: 8:8
6393 prim_subreg #(
6394 .DW (1),
6395 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6396 .RESVAL (1'h0),
6397 .Mubi (1'b0)
6398 ) u_key_intr_status_key0_in_l2h (
6399 .clk_i (clk_i),
6400 .rst_ni (rst_ni),
6401
6402 // from register interface
6403 .we (key_intr_status_we),
6404 .wd (key_intr_status_key0_in_l2h_wd),
6405
6406 // from internal hardware
6407 .de (hw2reg.key_intr_status.key0_in_l2h.de),
6408 .d (hw2reg.key_intr_status.key0_in_l2h.d),
6409
6410 // to internal hardware
6411 .qe (),
6412 .q (reg2hw.key_intr_status.key0_in_l2h.q),
6413 .ds (),
6414
6415 // to register interface (read)
6416 .qs (key_intr_status_key0_in_l2h_qs)
6417 );
6418
6419 // F[key1_in_l2h]: 9:9
6420 prim_subreg #(
6421 .DW (1),
6422 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6423 .RESVAL (1'h0),
6424 .Mubi (1'b0)
6425 ) u_key_intr_status_key1_in_l2h (
6426 .clk_i (clk_i),
6427 .rst_ni (rst_ni),
6428
6429 // from register interface
6430 .we (key_intr_status_we),
6431 .wd (key_intr_status_key1_in_l2h_wd),
6432
6433 // from internal hardware
6434 .de (hw2reg.key_intr_status.key1_in_l2h.de),
6435 .d (hw2reg.key_intr_status.key1_in_l2h.d),
6436
6437 // to internal hardware
6438 .qe (),
6439 .q (reg2hw.key_intr_status.key1_in_l2h.q),
6440 .ds (),
6441
6442 // to register interface (read)
6443 .qs (key_intr_status_key1_in_l2h_qs)
6444 );
6445
6446 // F[key2_in_l2h]: 10:10
6447 prim_subreg #(
6448 .DW (1),
6449 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6450 .RESVAL (1'h0),
6451 .Mubi (1'b0)
6452 ) u_key_intr_status_key2_in_l2h (
6453 .clk_i (clk_i),
6454 .rst_ni (rst_ni),
6455
6456 // from register interface
6457 .we (key_intr_status_we),
6458 .wd (key_intr_status_key2_in_l2h_wd),
6459
6460 // from internal hardware
6461 .de (hw2reg.key_intr_status.key2_in_l2h.de),
6462 .d (hw2reg.key_intr_status.key2_in_l2h.d),
6463
6464 // to internal hardware
6465 .qe (),
6466 .q (reg2hw.key_intr_status.key2_in_l2h.q),
6467 .ds (),
6468
6469 // to register interface (read)
6470 .qs (key_intr_status_key2_in_l2h_qs)
6471 );
6472
6473 // F[ac_present_l2h]: 11:11
6474 prim_subreg #(
6475 .DW (1),
6476 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6477 .RESVAL (1'h0),
6478 .Mubi (1'b0)
6479 ) u_key_intr_status_ac_present_l2h (
6480 .clk_i (clk_i),
6481 .rst_ni (rst_ni),
6482
6483 // from register interface
6484 .we (key_intr_status_we),
6485 .wd (key_intr_status_ac_present_l2h_wd),
6486
6487 // from internal hardware
6488 .de (hw2reg.key_intr_status.ac_present_l2h.de),
6489 .d (hw2reg.key_intr_status.ac_present_l2h.d),
6490
6491 // to internal hardware
6492 .qe (),
6493 .q (reg2hw.key_intr_status.ac_present_l2h.q),
6494 .ds (),
6495
6496 // to register interface (read)
6497 .qs (key_intr_status_ac_present_l2h_qs)
6498 );
6499
6500 // F[ec_rst_l_l2h]: 12:12
6501 prim_subreg #(
6502 .DW (1),
6503 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6504 .RESVAL (1'h0),
6505 .Mubi (1'b0)
6506 ) u_key_intr_status_ec_rst_l_l2h (
6507 .clk_i (clk_i),
6508 .rst_ni (rst_ni),
6509
6510 // from register interface
6511 .we (key_intr_status_we),
6512 .wd (key_intr_status_ec_rst_l_l2h_wd),
6513
6514 // from internal hardware
6515 .de (hw2reg.key_intr_status.ec_rst_l_l2h.de),
6516 .d (hw2reg.key_intr_status.ec_rst_l_l2h.d),
6517
6518 // to internal hardware
6519 .qe (),
6520 .q (reg2hw.key_intr_status.ec_rst_l_l2h.q),
6521 .ds (),
6522
6523 // to register interface (read)
6524 .qs (key_intr_status_ec_rst_l_l2h_qs)
6525 );
6526
6527 // F[flash_wp_l_l2h]: 13:13
6528 prim_subreg #(
6529 .DW (1),
6530 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6531 .RESVAL (1'h0),
6532 .Mubi (1'b0)
6533 ) u_key_intr_status_flash_wp_l_l2h (
6534 .clk_i (clk_i),
6535 .rst_ni (rst_ni),
6536
6537 // from register interface
6538 .we (key_intr_status_we),
6539 .wd (key_intr_status_flash_wp_l_l2h_wd),
6540
6541 // from internal hardware
6542 .de (hw2reg.key_intr_status.flash_wp_l_l2h.de),
6543 .d (hw2reg.key_intr_status.flash_wp_l_l2h.d),
6544
6545 // to internal hardware
6546 .qe (),
6547 .q (reg2hw.key_intr_status.flash_wp_l_l2h.q),
6548 .ds (),
6549
6550 // to register interface (read)
6551 .qs (key_intr_status_flash_wp_l_l2h_qs)
6552 );
6553
6554
6555
6556 logic [42:0] addr_hit;
6557 always_comb begin
6558 1/1 addr_hit = '0;
Tests: T1 T4 T5
6559 1/1 addr_hit[ 0] = (reg_addr == SYSRST_CTRL_INTR_STATE_OFFSET);
Tests: T1 T4 T5
6560 1/1 addr_hit[ 1] = (reg_addr == SYSRST_CTRL_INTR_ENABLE_OFFSET);
Tests: T1 T4 T5
6561 1/1 addr_hit[ 2] = (reg_addr == SYSRST_CTRL_INTR_TEST_OFFSET);
Tests: T1 T4 T5
6562 1/1 addr_hit[ 3] = (reg_addr == SYSRST_CTRL_ALERT_TEST_OFFSET);
Tests: T1 T4 T5
6563 1/1 addr_hit[ 4] = (reg_addr == SYSRST_CTRL_REGWEN_OFFSET);
Tests: T1 T4 T5
6564 1/1 addr_hit[ 5] = (reg_addr == SYSRST_CTRL_EC_RST_CTL_OFFSET);
Tests: T1 T4 T5
6565 1/1 addr_hit[ 6] = (reg_addr == SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_OFFSET);
Tests: T1 T4 T5
6566 1/1 addr_hit[ 7] = (reg_addr == SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_OFFSET);
Tests: T1 T4 T5
6567 1/1 addr_hit[ 8] = (reg_addr == SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_OFFSET);
Tests: T1 T4 T5
6568 1/1 addr_hit[ 9] = (reg_addr == SYSRST_CTRL_ULP_CTL_OFFSET);
Tests: T1 T4 T5
6569 1/1 addr_hit[10] = (reg_addr == SYSRST_CTRL_ULP_STATUS_OFFSET);
Tests: T1 T4 T5
6570 1/1 addr_hit[11] = (reg_addr == SYSRST_CTRL_WKUP_STATUS_OFFSET);
Tests: T1 T4 T5
6571 1/1 addr_hit[12] = (reg_addr == SYSRST_CTRL_KEY_INVERT_CTL_OFFSET);
Tests: T1 T4 T5
6572 1/1 addr_hit[13] = (reg_addr == SYSRST_CTRL_PIN_ALLOWED_CTL_OFFSET);
Tests: T1 T4 T5
6573 1/1 addr_hit[14] = (reg_addr == SYSRST_CTRL_PIN_OUT_CTL_OFFSET);
Tests: T1 T4 T5
6574 1/1 addr_hit[15] = (reg_addr == SYSRST_CTRL_PIN_OUT_VALUE_OFFSET);
Tests: T1 T4 T5
6575 1/1 addr_hit[16] = (reg_addr == SYSRST_CTRL_PIN_IN_VALUE_OFFSET);
Tests: T1 T4 T5
6576 1/1 addr_hit[17] = (reg_addr == SYSRST_CTRL_KEY_INTR_CTL_OFFSET);
Tests: T1 T4 T5
6577 1/1 addr_hit[18] = (reg_addr == SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_OFFSET);
Tests: T1 T4 T5
6578 1/1 addr_hit[19] = (reg_addr == SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_OFFSET);
Tests: T1 T4 T5
6579 1/1 addr_hit[20] = (reg_addr == SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_OFFSET);
Tests: T1 T4 T5
6580 1/1 addr_hit[21] = (reg_addr == SYSRST_CTRL_COM_PRE_SEL_CTL_0_OFFSET);
Tests: T1 T4 T5
6581 1/1 addr_hit[22] = (reg_addr == SYSRST_CTRL_COM_PRE_SEL_CTL_1_OFFSET);
Tests: T1 T4 T5
6582 1/1 addr_hit[23] = (reg_addr == SYSRST_CTRL_COM_PRE_SEL_CTL_2_OFFSET);
Tests: T1 T4 T5
6583 1/1 addr_hit[24] = (reg_addr == SYSRST_CTRL_COM_PRE_SEL_CTL_3_OFFSET);
Tests: T1 T4 T5
6584 1/1 addr_hit[25] = (reg_addr == SYSRST_CTRL_COM_PRE_DET_CTL_0_OFFSET);
Tests: T1 T4 T5
6585 1/1 addr_hit[26] = (reg_addr == SYSRST_CTRL_COM_PRE_DET_CTL_1_OFFSET);
Tests: T1 T4 T5
6586 1/1 addr_hit[27] = (reg_addr == SYSRST_CTRL_COM_PRE_DET_CTL_2_OFFSET);
Tests: T1 T4 T5
6587 1/1 addr_hit[28] = (reg_addr == SYSRST_CTRL_COM_PRE_DET_CTL_3_OFFSET);
Tests: T1 T4 T5
6588 1/1 addr_hit[29] = (reg_addr == SYSRST_CTRL_COM_SEL_CTL_0_OFFSET);
Tests: T1 T4 T5
6589 1/1 addr_hit[30] = (reg_addr == SYSRST_CTRL_COM_SEL_CTL_1_OFFSET);
Tests: T1 T4 T5
6590 1/1 addr_hit[31] = (reg_addr == SYSRST_CTRL_COM_SEL_CTL_2_OFFSET);
Tests: T1 T4 T5
6591 1/1 addr_hit[32] = (reg_addr == SYSRST_CTRL_COM_SEL_CTL_3_OFFSET);
Tests: T1 T4 T5
6592 1/1 addr_hit[33] = (reg_addr == SYSRST_CTRL_COM_DET_CTL_0_OFFSET);
Tests: T1 T4 T5
6593 1/1 addr_hit[34] = (reg_addr == SYSRST_CTRL_COM_DET_CTL_1_OFFSET);
Tests: T1 T4 T5
6594 1/1 addr_hit[35] = (reg_addr == SYSRST_CTRL_COM_DET_CTL_2_OFFSET);
Tests: T1 T4 T5
6595 1/1 addr_hit[36] = (reg_addr == SYSRST_CTRL_COM_DET_CTL_3_OFFSET);
Tests: T1 T4 T5
6596 1/1 addr_hit[37] = (reg_addr == SYSRST_CTRL_COM_OUT_CTL_0_OFFSET);
Tests: T1 T4 T5
6597 1/1 addr_hit[38] = (reg_addr == SYSRST_CTRL_COM_OUT_CTL_1_OFFSET);
Tests: T1 T4 T5
6598 1/1 addr_hit[39] = (reg_addr == SYSRST_CTRL_COM_OUT_CTL_2_OFFSET);
Tests: T1 T4 T5
6599 1/1 addr_hit[40] = (reg_addr == SYSRST_CTRL_COM_OUT_CTL_3_OFFSET);
Tests: T1 T4 T5
6600 1/1 addr_hit[41] = (reg_addr == SYSRST_CTRL_COMBO_INTR_STATUS_OFFSET);
Tests: T1 T4 T5
6601 1/1 addr_hit[42] = (reg_addr == SYSRST_CTRL_KEY_INTR_STATUS_OFFSET);
Tests: T1 T4 T5
6602 end
6603
6604 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T4 T5
6605
6606 // Check sub-word write is permitted
6607 always_comb begin
6608 1/1 wr_err = (reg_we &
Tests: T1 T4 T5
6609 ((addr_hit[ 0] & (|(SYSRST_CTRL_PERMIT[ 0] & ~reg_be))) |
6610 (addr_hit[ 1] & (|(SYSRST_CTRL_PERMIT[ 1] & ~reg_be))) |
6611 (addr_hit[ 2] & (|(SYSRST_CTRL_PERMIT[ 2] & ~reg_be))) |
6612 (addr_hit[ 3] & (|(SYSRST_CTRL_PERMIT[ 3] & ~reg_be))) |
6613 (addr_hit[ 4] & (|(SYSRST_CTRL_PERMIT[ 4] & ~reg_be))) |
6614 (addr_hit[ 5] & (|(SYSRST_CTRL_PERMIT[ 5] & ~reg_be))) |
6615 (addr_hit[ 6] & (|(SYSRST_CTRL_PERMIT[ 6] & ~reg_be))) |
6616 (addr_hit[ 7] & (|(SYSRST_CTRL_PERMIT[ 7] & ~reg_be))) |
6617 (addr_hit[ 8] & (|(SYSRST_CTRL_PERMIT[ 8] & ~reg_be))) |
6618 (addr_hit[ 9] & (|(SYSRST_CTRL_PERMIT[ 9] & ~reg_be))) |
6619 (addr_hit[10] & (|(SYSRST_CTRL_PERMIT[10] & ~reg_be))) |
6620 (addr_hit[11] & (|(SYSRST_CTRL_PERMIT[11] & ~reg_be))) |
6621 (addr_hit[12] & (|(SYSRST_CTRL_PERMIT[12] & ~reg_be))) |
6622 (addr_hit[13] & (|(SYSRST_CTRL_PERMIT[13] & ~reg_be))) |
6623 (addr_hit[14] & (|(SYSRST_CTRL_PERMIT[14] & ~reg_be))) |
6624 (addr_hit[15] & (|(SYSRST_CTRL_PERMIT[15] & ~reg_be))) |
6625 (addr_hit[16] & (|(SYSRST_CTRL_PERMIT[16] & ~reg_be))) |
6626 (addr_hit[17] & (|(SYSRST_CTRL_PERMIT[17] & ~reg_be))) |
6627 (addr_hit[18] & (|(SYSRST_CTRL_PERMIT[18] & ~reg_be))) |
6628 (addr_hit[19] & (|(SYSRST_CTRL_PERMIT[19] & ~reg_be))) |
6629 (addr_hit[20] & (|(SYSRST_CTRL_PERMIT[20] & ~reg_be))) |
6630 (addr_hit[21] & (|(SYSRST_CTRL_PERMIT[21] & ~reg_be))) |
6631 (addr_hit[22] & (|(SYSRST_CTRL_PERMIT[22] & ~reg_be))) |
6632 (addr_hit[23] & (|(SYSRST_CTRL_PERMIT[23] & ~reg_be))) |
6633 (addr_hit[24] & (|(SYSRST_CTRL_PERMIT[24] & ~reg_be))) |
6634 (addr_hit[25] & (|(SYSRST_CTRL_PERMIT[25] & ~reg_be))) |
6635 (addr_hit[26] & (|(SYSRST_CTRL_PERMIT[26] & ~reg_be))) |
6636 (addr_hit[27] & (|(SYSRST_CTRL_PERMIT[27] & ~reg_be))) |
6637 (addr_hit[28] & (|(SYSRST_CTRL_PERMIT[28] & ~reg_be))) |
6638 (addr_hit[29] & (|(SYSRST_CTRL_PERMIT[29] & ~reg_be))) |
6639 (addr_hit[30] & (|(SYSRST_CTRL_PERMIT[30] & ~reg_be))) |
6640 (addr_hit[31] & (|(SYSRST_CTRL_PERMIT[31] & ~reg_be))) |
6641 (addr_hit[32] & (|(SYSRST_CTRL_PERMIT[32] & ~reg_be))) |
6642 (addr_hit[33] & (|(SYSRST_CTRL_PERMIT[33] & ~reg_be))) |
6643 (addr_hit[34] & (|(SYSRST_CTRL_PERMIT[34] & ~reg_be))) |
6644 (addr_hit[35] & (|(SYSRST_CTRL_PERMIT[35] & ~reg_be))) |
6645 (addr_hit[36] & (|(SYSRST_CTRL_PERMIT[36] & ~reg_be))) |
6646 (addr_hit[37] & (|(SYSRST_CTRL_PERMIT[37] & ~reg_be))) |
6647 (addr_hit[38] & (|(SYSRST_CTRL_PERMIT[38] & ~reg_be))) |
6648 (addr_hit[39] & (|(SYSRST_CTRL_PERMIT[39] & ~reg_be))) |
6649 (addr_hit[40] & (|(SYSRST_CTRL_PERMIT[40] & ~reg_be))) |
6650 (addr_hit[41] & (|(SYSRST_CTRL_PERMIT[41] & ~reg_be))) |
6651 (addr_hit[42] & (|(SYSRST_CTRL_PERMIT[42] & ~reg_be)))));
6652 end
6653
6654 // Generate write-enables
6655 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T4 T5
6656
6657 1/1 assign intr_enable_wd = reg_wdata[0];
Tests: T1 T4 T5
6658 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T4 T5
6659
6660 1/1 assign intr_test_wd = reg_wdata[0];
Tests: T1 T4 T5
6661 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T4 T5
6662
6663 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T4 T5
6664 1/1 assign regwen_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T4 T5
6665
6666 1/1 assign regwen_wd = reg_wdata[0];
Tests: T1 T4 T5
6667 1/1 assign ec_rst_ctl_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T4 T5
6668
6669 1/1 assign ulp_ac_debounce_ctl_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T4 T5
6670
6671 1/1 assign ulp_lid_debounce_ctl_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T4 T5
6672
6673 1/1 assign ulp_pwrb_debounce_ctl_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T4 T5
6674
6675 1/1 assign ulp_ctl_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T4 T5
6676
6677 1/1 assign ulp_status_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T4 T5
6678
6679 1/1 assign ulp_status_wd = reg_wdata[0];
Tests: T1 T4 T5
6680 1/1 assign wkup_status_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T4 T5
6681
6682 1/1 assign key_invert_ctl_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T4 T5
6683
6684
6685
6686
6687
6688
6689
6690
6691
6692
6693
6694
6695 1/1 assign pin_allowed_ctl_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T4 T5
6696
6697
6698
6699
6700
6701
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712 1/1 assign pin_out_ctl_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T4 T5
6713
6714
6715
6716
6717
6718
6719
6720
6721 1/1 assign pin_out_value_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T4 T5
6722
6723
6724
6725
6726
6727
6728
6729
6730 1/1 assign key_intr_ctl_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T4 T5
6731
6732
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745 1/1 assign key_intr_debounce_ctl_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T4 T5
6746
6747 1/1 assign auto_block_debounce_ctl_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T4 T5
6748
6749
6750 1/1 assign auto_block_out_ctl_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T4 T5
6751
6752
6753
6754
6755
6756
6757 1/1 assign com_pre_sel_ctl_0_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T4 T5
6758
6759
6760
6761
6762
6763 1/1 assign com_pre_sel_ctl_1_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T4 T5
6764
6765
6766
6767
6768
6769 1/1 assign com_pre_sel_ctl_2_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T4 T5
6770
6771
6772
6773
6774
6775 1/1 assign com_pre_sel_ctl_3_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T4 T5
6776
6777
6778
6779
6780
6781 1/1 assign com_pre_det_ctl_0_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T4 T5
6782
6783 1/1 assign com_pre_det_ctl_1_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T4 T5
6784
6785 1/1 assign com_pre_det_ctl_2_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T4 T5
6786
6787 1/1 assign com_pre_det_ctl_3_we = addr_hit[28] & reg_we & !reg_error;
Tests: T1 T4 T5
6788
6789 1/1 assign com_sel_ctl_0_we = addr_hit[29] & reg_we & !reg_error;
Tests: T1 T4 T5
6790
6791
6792
6793
6794
6795 1/1 assign com_sel_ctl_1_we = addr_hit[30] & reg_we & !reg_error;
Tests: T1 T4 T5
6796
6797
6798
6799
6800
6801 1/1 assign com_sel_ctl_2_we = addr_hit[31] & reg_we & !reg_error;
Tests: T1 T4 T5
6802
6803
6804
6805
6806
6807 1/1 assign com_sel_ctl_3_we = addr_hit[32] & reg_we & !reg_error;
Tests: T1 T4 T5
6808
6809
6810
6811
6812
6813 1/1 assign com_det_ctl_0_we = addr_hit[33] & reg_we & !reg_error;
Tests: T1 T4 T5
6814
6815 1/1 assign com_det_ctl_1_we = addr_hit[34] & reg_we & !reg_error;
Tests: T1 T4 T5
6816
6817 1/1 assign com_det_ctl_2_we = addr_hit[35] & reg_we & !reg_error;
Tests: T1 T4 T5
6818
6819 1/1 assign com_det_ctl_3_we = addr_hit[36] & reg_we & !reg_error;
Tests: T1 T4 T5
6820
6821 1/1 assign com_out_ctl_0_we = addr_hit[37] & reg_we & !reg_error;
Tests: T1 T4 T5
6822
6823
6824
6825
6826 1/1 assign com_out_ctl_1_we = addr_hit[38] & reg_we & !reg_error;
Tests: T1 T4 T5
6827
6828
6829
6830
6831 1/1 assign com_out_ctl_2_we = addr_hit[39] & reg_we & !reg_error;
Tests: T1 T4 T5
6832
6833
6834
6835
6836 1/1 assign com_out_ctl_3_we = addr_hit[40] & reg_we & !reg_error;
Tests: T1 T4 T5
6837
6838
6839
6840
6841 1/1 assign combo_intr_status_we = addr_hit[41] & reg_we & !reg_error;
Tests: T1 T4 T5
6842
6843 1/1 assign combo_intr_status_combo0_h2l_wd = reg_wdata[0];
Tests: T1 T4 T5
6844
6845 1/1 assign combo_intr_status_combo1_h2l_wd = reg_wdata[1];
Tests: T1 T4 T5
6846
6847 1/1 assign combo_intr_status_combo2_h2l_wd = reg_wdata[2];
Tests: T1 T4 T5
6848
6849 1/1 assign combo_intr_status_combo3_h2l_wd = reg_wdata[3];
Tests: T1 T4 T5
6850 1/1 assign key_intr_status_we = addr_hit[42] & reg_we & !reg_error;
Tests: T1 T4 T5
6851
6852 1/1 assign key_intr_status_pwrb_h2l_wd = reg_wdata[0];
Tests: T1 T4 T5
6853
6854 1/1 assign key_intr_status_key0_in_h2l_wd = reg_wdata[1];
Tests: T1 T4 T5
6855
6856 1/1 assign key_intr_status_key1_in_h2l_wd = reg_wdata[2];
Tests: T1 T4 T5
6857
6858 1/1 assign key_intr_status_key2_in_h2l_wd = reg_wdata[3];
Tests: T1 T4 T5
6859
6860 1/1 assign key_intr_status_ac_present_h2l_wd = reg_wdata[4];
Tests: T1 T4 T5
6861
6862 1/1 assign key_intr_status_ec_rst_l_h2l_wd = reg_wdata[5];
Tests: T1 T4 T5
6863
6864 1/1 assign key_intr_status_flash_wp_l_h2l_wd = reg_wdata[6];
Tests: T1 T4 T5
6865
6866 1/1 assign key_intr_status_pwrb_l2h_wd = reg_wdata[7];
Tests: T1 T4 T5
6867
6868 1/1 assign key_intr_status_key0_in_l2h_wd = reg_wdata[8];
Tests: T1 T4 T5
6869
6870 1/1 assign key_intr_status_key1_in_l2h_wd = reg_wdata[9];
Tests: T1 T4 T5
6871
6872 1/1 assign key_intr_status_key2_in_l2h_wd = reg_wdata[10];
Tests: T1 T4 T5
6873
6874 1/1 assign key_intr_status_ac_present_l2h_wd = reg_wdata[11];
Tests: T1 T4 T5
6875
6876 1/1 assign key_intr_status_ec_rst_l_l2h_wd = reg_wdata[12];
Tests: T1 T4 T5
6877
6878 1/1 assign key_intr_status_flash_wp_l_l2h_wd = reg_wdata[13];
Tests: T1 T4 T5
6879
6880 // Assign write-enables to checker logic vector.
6881 always_comb begin
6882 1/1 reg_we_check = '0;
Tests: T1 T4 T5
6883 1/1 reg_we_check[0] = 1'b0;
Tests: T1 T4 T5
6884 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T4 T5
6885 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T4 T5
6886 1/1 reg_we_check[3] = alert_test_we;
Tests: T1 T4 T5
6887 1/1 reg_we_check[4] = regwen_we;
Tests: T1 T4 T5
6888 1/1 reg_we_check[5] = ec_rst_ctl_we;
Tests: T1 T4 T5
6889 1/1 reg_we_check[6] = ulp_ac_debounce_ctl_we;
Tests: T1 T4 T5
6890 1/1 reg_we_check[7] = ulp_lid_debounce_ctl_we;
Tests: T1 T4 T5
6891 1/1 reg_we_check[8] = ulp_pwrb_debounce_ctl_we;
Tests: T1 T4 T5
6892 1/1 reg_we_check[9] = ulp_ctl_we;
Tests: T1 T4 T5
6893 1/1 reg_we_check[10] = ulp_status_we;
Tests: T1 T4 T5
6894 1/1 reg_we_check[11] = wkup_status_we;
Tests: T1 T4 T5
6895 1/1 reg_we_check[12] = key_invert_ctl_we;
Tests: T1 T4 T5
6896 1/1 reg_we_check[13] = pin_allowed_ctl_we;
Tests: T1 T4 T5
6897 1/1 reg_we_check[14] = pin_out_ctl_we;
Tests: T1 T4 T5
6898 1/1 reg_we_check[15] = pin_out_value_we;
Tests: T1 T4 T5
6899 1/1 reg_we_check[16] = 1'b0;
Tests: T1 T4 T5
6900 1/1 reg_we_check[17] = key_intr_ctl_we;
Tests: T1 T4 T5
6901 1/1 reg_we_check[18] = key_intr_debounce_ctl_we;
Tests: T1 T4 T5
6902 1/1 reg_we_check[19] = auto_block_debounce_ctl_we;
Tests: T1 T4 T5
6903 1/1 reg_we_check[20] = auto_block_out_ctl_we;
Tests: T1 T4 T5
6904 1/1 reg_we_check[21] = com_pre_sel_ctl_0_we;
Tests: T1 T4 T5
6905 1/1 reg_we_check[22] = com_pre_sel_ctl_1_we;
Tests: T1 T4 T5
6906 1/1 reg_we_check[23] = com_pre_sel_ctl_2_we;
Tests: T1 T4 T5
6907 1/1 reg_we_check[24] = com_pre_sel_ctl_3_we;
Tests: T1 T4 T5
6908 1/1 reg_we_check[25] = com_pre_det_ctl_0_we;
Tests: T1 T4 T5
6909 1/1 reg_we_check[26] = com_pre_det_ctl_1_we;
Tests: T1 T4 T5
6910 1/1 reg_we_check[27] = com_pre_det_ctl_2_we;
Tests: T1 T4 T5
6911 1/1 reg_we_check[28] = com_pre_det_ctl_3_we;
Tests: T1 T4 T5
6912 1/1 reg_we_check[29] = com_sel_ctl_0_we;
Tests: T1 T4 T5
6913 1/1 reg_we_check[30] = com_sel_ctl_1_we;
Tests: T1 T4 T5
6914 1/1 reg_we_check[31] = com_sel_ctl_2_we;
Tests: T1 T4 T5
6915 1/1 reg_we_check[32] = com_sel_ctl_3_we;
Tests: T1 T4 T5
6916 1/1 reg_we_check[33] = com_det_ctl_0_we;
Tests: T1 T4 T5
6917 1/1 reg_we_check[34] = com_det_ctl_1_we;
Tests: T1 T4 T5
6918 1/1 reg_we_check[35] = com_det_ctl_2_we;
Tests: T1 T4 T5
6919 1/1 reg_we_check[36] = com_det_ctl_3_we;
Tests: T1 T4 T5
6920 1/1 reg_we_check[37] = com_out_ctl_0_we;
Tests: T1 T4 T5
6921 1/1 reg_we_check[38] = com_out_ctl_1_we;
Tests: T1 T4 T5
6922 1/1 reg_we_check[39] = com_out_ctl_2_we;
Tests: T1 T4 T5
6923 1/1 reg_we_check[40] = com_out_ctl_3_we;
Tests: T1 T4 T5
6924 1/1 reg_we_check[41] = combo_intr_status_we;
Tests: T1 T4 T5
6925 1/1 reg_we_check[42] = key_intr_status_we;
Tests: T1 T4 T5
6926 end
6927
6928 // Read data return
6929 always_comb begin
6930 1/1 reg_rdata_next = '0;
Tests: T1 T4 T5
6931 1/1 unique case (1'b1)
Tests: T1 T4 T5
6932 addr_hit[0]: begin
6933 1/1 reg_rdata_next[0] = intr_state_qs;
Tests: T1 T4 T5
6934 end
6935
6936 addr_hit[1]: begin
6937 1/1 reg_rdata_next[0] = intr_enable_qs;
Tests: T1 T4 T5
6938 end
6939
6940 addr_hit[2]: begin
6941 1/1 reg_rdata_next[0] = '0;
Tests: T4 T5 T2
6942 end
6943
6944 addr_hit[3]: begin
6945 1/1 reg_rdata_next[0] = '0;
Tests: T4 T5 T2
6946 end
6947
6948 addr_hit[4]: begin
6949 1/1 reg_rdata_next[0] = regwen_qs;
Tests: T1 T4 T5
6950 end
6951
6952 addr_hit[5]: begin
6953 1/1 reg_rdata_next = DW'(ec_rst_ctl_qs);
Tests: T1 T4 T5
6954 end
6955 addr_hit[6]: begin
6956 1/1 reg_rdata_next = DW'(ulp_ac_debounce_ctl_qs);
Tests: T4 T5 T2
6957 end
6958 addr_hit[7]: begin
6959 1/1 reg_rdata_next = DW'(ulp_lid_debounce_ctl_qs);
Tests: T4 T5 T2
6960 end
6961 addr_hit[8]: begin
6962 1/1 reg_rdata_next = DW'(ulp_pwrb_debounce_ctl_qs);
Tests: T1 T4 T5
6963 end
6964 addr_hit[9]: begin
6965 1/1 reg_rdata_next = DW'(ulp_ctl_qs);
Tests: T1 T4 T5
6966 end
6967 addr_hit[10]: begin
6968 1/1 reg_rdata_next[0] = ulp_status_qs;
Tests: T4 T5 T2
6969 end
6970
6971 addr_hit[11]: begin
6972 1/1 reg_rdata_next = DW'(wkup_status_qs);
Tests: T4 T5 T2
6973 end
6974 addr_hit[12]: begin
6975 1/1 reg_rdata_next = DW'(key_invert_ctl_qs);
Tests: T4 T5 T2
6976 end
6977 addr_hit[13]: begin
6978 1/1 reg_rdata_next = DW'(pin_allowed_ctl_qs);
Tests: T1 T4 T5
6979 end
6980 addr_hit[14]: begin
6981 1/1 reg_rdata_next = DW'(pin_out_ctl_qs);
Tests: T1 T4 T5
6982 end
6983 addr_hit[15]: begin
6984 1/1 reg_rdata_next = DW'(pin_out_value_qs);
Tests: T4 T5 T2
6985 end
6986 addr_hit[16]: begin
6987 1/1 reg_rdata_next[0] = pin_in_value_pwrb_in_qs;
Tests: T1 T4 T5
6988 1/1 reg_rdata_next[1] = pin_in_value_key0_in_qs;
Tests: T1 T4 T5
6989 1/1 reg_rdata_next[2] = pin_in_value_key1_in_qs;
Tests: T1 T4 T5
6990 1/1 reg_rdata_next[3] = pin_in_value_key2_in_qs;
Tests: T1 T4 T5
6991 1/1 reg_rdata_next[4] = pin_in_value_lid_open_qs;
Tests: T1 T4 T5
6992 1/1 reg_rdata_next[5] = pin_in_value_ac_present_qs;
Tests: T1 T4 T5
6993 1/1 reg_rdata_next[6] = pin_in_value_ec_rst_l_qs;
Tests: T1 T4 T5
6994 1/1 reg_rdata_next[7] = pin_in_value_flash_wp_l_qs;
Tests: T1 T4 T5
6995 end
6996
6997 addr_hit[17]: begin
6998 1/1 reg_rdata_next = DW'(key_intr_ctl_qs);
Tests: T4 T5 T2
6999 end
7000 addr_hit[18]: begin
7001 1/1 reg_rdata_next = DW'(key_intr_debounce_ctl_qs);
Tests: T1 T4 T5
7002 end
7003 addr_hit[19]: begin
7004 1/1 reg_rdata_next = DW'(auto_block_debounce_ctl_qs);
Tests: T4 T5 T2
7005 end
7006 addr_hit[20]: begin
7007 1/1 reg_rdata_next = DW'(auto_block_out_ctl_qs);
Tests: T4 T5 T2
7008 end
7009 addr_hit[21]: begin
7010 1/1 reg_rdata_next = DW'(com_pre_sel_ctl_0_qs);
Tests: T1 T4 T5
7011 end
7012 addr_hit[22]: begin
7013 1/1 reg_rdata_next = DW'(com_pre_sel_ctl_1_qs);
Tests: T4 T5 T2
7014 end
7015 addr_hit[23]: begin
7016 1/1 reg_rdata_next = DW'(com_pre_sel_ctl_2_qs);
Tests: T4 T5 T2
7017 end
7018 addr_hit[24]: begin
7019 1/1 reg_rdata_next = DW'(com_pre_sel_ctl_3_qs);
Tests: T4 T5 T2
7020 end
7021 addr_hit[25]: begin
7022 1/1 reg_rdata_next = DW'(com_pre_det_ctl_0_qs);
Tests: T1 T4 T5
7023 end
7024 addr_hit[26]: begin
7025 1/1 reg_rdata_next = DW'(com_pre_det_ctl_1_qs);
Tests: T1 T4 T5
7026 end
7027 addr_hit[27]: begin
7028 1/1 reg_rdata_next = DW'(com_pre_det_ctl_2_qs);
Tests: T4 T5 T2
7029 end
7030 addr_hit[28]: begin
7031 1/1 reg_rdata_next = DW'(com_pre_det_ctl_3_qs);
Tests: T4 T5 T2
7032 end
7033 addr_hit[29]: begin
7034 1/1 reg_rdata_next = DW'(com_sel_ctl_0_qs);
Tests: T1 T4 T5
7035 end
7036 addr_hit[30]: begin
7037 1/1 reg_rdata_next = DW'(com_sel_ctl_1_qs);
Tests: T4 T5 T2
7038 end
7039 addr_hit[31]: begin
7040 1/1 reg_rdata_next = DW'(com_sel_ctl_2_qs);
Tests: T4 T5 T2
7041 end
7042 addr_hit[32]: begin
7043 1/1 reg_rdata_next = DW'(com_sel_ctl_3_qs);
Tests: T4 T5 T2
7044 end
7045 addr_hit[33]: begin
7046 1/1 reg_rdata_next = DW'(com_det_ctl_0_qs);
Tests: T1 T4 T5
7047 end
7048 addr_hit[34]: begin
7049 1/1 reg_rdata_next = DW'(com_det_ctl_1_qs);
Tests: T4 T5 T2
7050 end
7051 addr_hit[35]: begin
7052 1/1 reg_rdata_next = DW'(com_det_ctl_2_qs);
Tests: T4 T5 T2
7053 end
7054 addr_hit[36]: begin
7055 1/1 reg_rdata_next = DW'(com_det_ctl_3_qs);
Tests: T4 T5 T2
7056 end
7057 addr_hit[37]: begin
7058 1/1 reg_rdata_next = DW'(com_out_ctl_0_qs);
Tests: T1 T4 T5
7059 end
7060 addr_hit[38]: begin
7061 1/1 reg_rdata_next = DW'(com_out_ctl_1_qs);
Tests: T4 T5 T2
7062 end
7063 addr_hit[39]: begin
7064 1/1 reg_rdata_next = DW'(com_out_ctl_2_qs);
Tests: T4 T5 T2
7065 end
7066 addr_hit[40]: begin
7067 1/1 reg_rdata_next = DW'(com_out_ctl_3_qs);
Tests: T1 T4 T5
7068 end
7069 addr_hit[41]: begin
7070 1/1 reg_rdata_next[0] = combo_intr_status_combo0_h2l_qs;
Tests: T1 T4 T5
7071 1/1 reg_rdata_next[1] = combo_intr_status_combo1_h2l_qs;
Tests: T1 T4 T5
7072 1/1 reg_rdata_next[2] = combo_intr_status_combo2_h2l_qs;
Tests: T1 T4 T5
7073 1/1 reg_rdata_next[3] = combo_intr_status_combo3_h2l_qs;
Tests: T1 T4 T5
7074 end
7075
7076 addr_hit[42]: begin
7077 1/1 reg_rdata_next[0] = key_intr_status_pwrb_h2l_qs;
Tests: T4 T5 T2
7078 1/1 reg_rdata_next[1] = key_intr_status_key0_in_h2l_qs;
Tests: T4 T5 T2
7079 1/1 reg_rdata_next[2] = key_intr_status_key1_in_h2l_qs;
Tests: T4 T5 T2
7080 1/1 reg_rdata_next[3] = key_intr_status_key2_in_h2l_qs;
Tests: T4 T5 T2
7081 1/1 reg_rdata_next[4] = key_intr_status_ac_present_h2l_qs;
Tests: T4 T5 T2
7082 1/1 reg_rdata_next[5] = key_intr_status_ec_rst_l_h2l_qs;
Tests: T4 T5 T2
7083 1/1 reg_rdata_next[6] = key_intr_status_flash_wp_l_h2l_qs;
Tests: T4 T5 T2
7084 1/1 reg_rdata_next[7] = key_intr_status_pwrb_l2h_qs;
Tests: T4 T5 T2
7085 1/1 reg_rdata_next[8] = key_intr_status_key0_in_l2h_qs;
Tests: T4 T5 T2
7086 1/1 reg_rdata_next[9] = key_intr_status_key1_in_l2h_qs;
Tests: T4 T5 T2
7087 1/1 reg_rdata_next[10] = key_intr_status_key2_in_l2h_qs;
Tests: T4 T5 T2
7088 1/1 reg_rdata_next[11] = key_intr_status_ac_present_l2h_qs;
Tests: T4 T5 T2
7089 1/1 reg_rdata_next[12] = key_intr_status_ec_rst_l_l2h_qs;
Tests: T4 T5 T2
7090 1/1 reg_rdata_next[13] = key_intr_status_flash_wp_l_l2h_qs;
Tests: T4 T5 T2
7091 end
7092
7093 default: begin
7094 reg_rdata_next = '1;
7095 end
7096 endcase
7097 end
7098
7099 // shadow busy
7100 logic shadow_busy;
7101 assign shadow_busy = 1'b0;
7102
7103 // register busy
7104 logic reg_busy_sel;
7105 1/1 assign reg_busy = reg_busy_sel | shadow_busy;
Tests: T1 T4 T5
7106 always_comb begin
7107 1/1 reg_busy_sel = '0;
Tests: T1 T4 T5
7108 1/1 unique case (1'b1)
Tests: T1 T4 T5
7109 addr_hit[5]: begin
7110 1/1 reg_busy_sel = ec_rst_ctl_busy;
Tests: T1 T4 T5
7111 end
7112 addr_hit[6]: begin
7113 1/1 reg_busy_sel = ulp_ac_debounce_ctl_busy;
Tests: T4 T5 T2
7114 end
7115 addr_hit[7]: begin
7116 1/1 reg_busy_sel = ulp_lid_debounce_ctl_busy;
Tests: T4 T5 T2
7117 end
7118 addr_hit[8]: begin
7119 1/1 reg_busy_sel = ulp_pwrb_debounce_ctl_busy;
Tests: T1 T4 T5
7120 end
7121 addr_hit[9]: begin
7122 1/1 reg_busy_sel = ulp_ctl_busy;
Tests: T1 T4 T5
7123 end
7124 addr_hit[11]: begin
7125 1/1 reg_busy_sel = wkup_status_busy;
Tests: T4 T5 T2
7126 end
7127 addr_hit[12]: begin
7128 1/1 reg_busy_sel = key_invert_ctl_busy;
Tests: T4 T5 T2
7129 end
7130 addr_hit[13]: begin
7131 1/1 reg_busy_sel = pin_allowed_ctl_busy;
Tests: T1 T4 T5
7132 end
7133 addr_hit[14]: begin
7134 1/1 reg_busy_sel = pin_out_ctl_busy;
Tests: T1 T4 T5
7135 end
7136 addr_hit[15]: begin
7137 1/1 reg_busy_sel = pin_out_value_busy;
Tests: T4 T5 T2
7138 end
7139 addr_hit[17]: begin
7140 1/1 reg_busy_sel = key_intr_ctl_busy;
Tests: T4 T5 T2
7141 end
7142 addr_hit[18]: begin
7143 1/1 reg_busy_sel = key_intr_debounce_ctl_busy;
Tests: T1 T4 T5
7144 end
7145 addr_hit[19]: begin
7146 1/1 reg_busy_sel = auto_block_debounce_ctl_busy;
Tests: T4 T5 T2
7147 end
7148 addr_hit[20]: begin
7149 1/1 reg_busy_sel = auto_block_out_ctl_busy;
Tests: T4 T5 T2
7150 end
7151 addr_hit[21]: begin
7152 1/1 reg_busy_sel = com_pre_sel_ctl_0_busy;
Tests: T1 T4 T5
7153 end
7154 addr_hit[22]: begin
7155 1/1 reg_busy_sel = com_pre_sel_ctl_1_busy;
Tests: T4 T5 T2
7156 end
7157 addr_hit[23]: begin
7158 1/1 reg_busy_sel = com_pre_sel_ctl_2_busy;
Tests: T4 T5 T2
7159 end
7160 addr_hit[24]: begin
7161 1/1 reg_busy_sel = com_pre_sel_ctl_3_busy;
Tests: T4 T5 T2
7162 end
7163 addr_hit[25]: begin
7164 1/1 reg_busy_sel = com_pre_det_ctl_0_busy;
Tests: T1 T4 T5
7165 end
7166 addr_hit[26]: begin
7167 1/1 reg_busy_sel = com_pre_det_ctl_1_busy;
Tests: T1 T4 T5
7168 end
7169 addr_hit[27]: begin
7170 1/1 reg_busy_sel = com_pre_det_ctl_2_busy;
Tests: T4 T5 T2
7171 end
7172 addr_hit[28]: begin
7173 1/1 reg_busy_sel = com_pre_det_ctl_3_busy;
Tests: T4 T5 T2
7174 end
7175 addr_hit[29]: begin
7176 1/1 reg_busy_sel = com_sel_ctl_0_busy;
Tests: T1 T4 T5
7177 end
7178 addr_hit[30]: begin
7179 1/1 reg_busy_sel = com_sel_ctl_1_busy;
Tests: T4 T5 T2
7180 end
7181 addr_hit[31]: begin
7182 1/1 reg_busy_sel = com_sel_ctl_2_busy;
Tests: T4 T5 T2
7183 end
7184 addr_hit[32]: begin
7185 1/1 reg_busy_sel = com_sel_ctl_3_busy;
Tests: T4 T5 T2
7186 end
7187 addr_hit[33]: begin
7188 1/1 reg_busy_sel = com_det_ctl_0_busy;
Tests: T1 T4 T5
7189 end
7190 addr_hit[34]: begin
7191 1/1 reg_busy_sel = com_det_ctl_1_busy;
Tests: T4 T5 T2
7192 end
7193 addr_hit[35]: begin
7194 1/1 reg_busy_sel = com_det_ctl_2_busy;
Tests: T4 T5 T2
7195 end
7196 addr_hit[36]: begin
7197 1/1 reg_busy_sel = com_det_ctl_3_busy;
Tests: T4 T5 T2
7198 end
7199 addr_hit[37]: begin
7200 1/1 reg_busy_sel = com_out_ctl_0_busy;
Tests: T1 T4 T5
7201 end
7202 addr_hit[38]: begin
7203 1/1 reg_busy_sel = com_out_ctl_1_busy;
Tests: T4 T5 T2
7204 end
7205 addr_hit[39]: begin
7206 1/1 reg_busy_sel = com_out_ctl_2_busy;
Tests: T4 T5 T2
7207 end
7208 addr_hit[40]: begin
7209 1/1 reg_busy_sel = com_out_ctl_3_busy;
Tests: T1 T4 T5
7210 end
7211 default: begin
7212 reg_busy_sel = '0;
7213 end
7214 endcase
7215 end
7216
7217
7218 // Unused signal tieoff
7219
7220 // wdata / byte enable are not always fully used
7221 // add a blanket unused statement to handle lint waivers
7222 logic unused_wdata;
7223 logic unused_be;
7224 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T4 T5
7225 1/1 assign unused_be = ^reg_be;
Tests: T1 T4 T5