Module Definition
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Module : sysrst_ctrl_autoblock
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_autoblock 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sysrst_ctrl_autoblock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.64 96.15 90.91 100.00 96.15 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sysrst_ctrl_detect 95.67 95.83 87.50 100.00 95.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_autoblock
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN5011100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
50 1 1
51 1 1
53 1 1
55 1 1


Cond Coverage for Module : sysrst_ctrl_autoblock
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (((aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q)) ? aon_auto_block_out_ctl_i.key0_out_value.q : key0_int_i)
             ------------------------------1------------------------------
-1-StatusTests
0CoveredT8,T47,T42
1CoveredT21,T23,T27

 LINE       53
 EXPRESSION (((aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q)) ? aon_auto_block_out_ctl_i.key1_out_value.q : key1_int_i)
             ------------------------------1------------------------------
-1-StatusTests
0CoveredT8,T47,T42
1CoveredT18,T21,T25

 LINE       55
 EXPRESSION (((aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q)) ? aon_auto_block_out_ctl_i.key2_out_value.q : key2_int_i)
             ------------------------------1------------------------------
-1-StatusTests
0CoveredT8,T47,T42
1CoveredT8,T16,T19

Branch Coverage for Module : sysrst_ctrl_autoblock
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 51 2 2 100.00
TERNARY 53 2 2 100.00
TERNARY 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q)) ?

Branches:
-1-StatusTests
1 Covered T21,T23,T27
0 Covered T8,T47,T42


LineNo. Expression -1-: 53 ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q)) ?

Branches:
-1-StatusTests
1 Covered T18,T21,T25
0 Covered T8,T47,T42


LineNo. Expression -1-: 55 ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q)) ?

Branches:
-1-StatusTests
1 Covered T8,T16,T19
0 Covered T8,T47,T42

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