Module Definition
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Module : prim_reg_cdc_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.13 100.00 68.75 95.65

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb 78.98 91.84 62.50 82.61
tb.dut.u_reg.u_ulp_status_cdc.u_arb 81.07 91.84 68.75 82.61
tb.dut.u_reg.u_wkup_status_cdc.u_arb 81.07 91.84 68.75 82.61
tb.dut.u_reg.u_key_intr_status_cdc.u_arb 86.05 100.00 62.50 95.65
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb 100.00 100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=15,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal=0,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN24900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
233 1 1
234 1 1
249 unreachable


Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal=0,DstWrReq=1 + DataWidth=14,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :
SCORELINE
81.07 91.84
tb.dut.u_reg.u_ulp_status_cdc.u_arb

SCORELINE
81.07 91.84
tb.dut.u_reg.u_wkup_status_cdc.u_arb

SCORELINE
78.98 91.84
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb

SCORELINE
86.05 100.00
tb.dut.u_reg.u_key_intr_status_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL4949100.00
ALWAYS10533100.00
ALWAYS11566100.00
CONT_ASSIGN12911100.00
ALWAYS13366100.00
ALWAYS1491010100.00
CONT_ASSIGN16411100.00
ALWAYS1681919100.00
CONT_ASSIGN20911100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
106 1 1
108 1 1
115 1 1
116 1 1
117 1 1
122 1 1
123 1 1
126 1 1
MISSING_ELSE
129 1 1
133 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
MISSING_ELSE
149 1 1
150 1 1
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
164 1 1
168 1 1
169 1 1
173 1 1
174 1 1
176 1 1
178 1 1
180 1 1
181 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
191 1 1
192 1 1
MISSING_ELSE
197 1 1
198 1 1
199 1 1
MISSING_ELSE
209 1 1
224 1 1
225 1 1


Cond Coverage for Module : prim_reg_cdc_arb
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       117
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       123
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T4,T5

 LINE       151
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       153
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11CoveredT1,T2,T3

 LINE       155
 EXPRESSION (dst_update_i && gen_wr_req.dst_lat_d)
             ------1-----    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T6
11CoveredT2,T3,T4

Branch Coverage for Module : prim_reg_cdc_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 105 2 2 100.00
IF 115 4 4 100.00
IF 133 4 4 100.00
IF 149 6 6 100.00
CASE 178 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 105 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T7,T8
0 Covered T1,T7,T8


LineNo. Expression -1-: 115 if ((!rst_dst_ni)) -2-: 117 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 123 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T7,T8
0 1 - Covered T1,T4,T5
0 0 1 Covered T1,T4,T5
0 0 0 Covered T1,T7,T8


LineNo. Expression -1-: 133 if ((!rst_dst_ni)) -2-: 135 if (gen_wr_req.dst_lat_d) -3-: 137 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T7,T8
0 1 - Covered T1,T2,T3
0 0 1 Covered T9
0 0 0 Covered T1,T7,T8


LineNo. Expression -1-: 149 if ((!rst_dst_ni)) -2-: 151 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 153 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 155 if ((dst_update_i && gen_wr_req.dst_lat_d)) -5-: 157 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T7,T8
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T2,T3,T4
0 0 0 0 1 Covered T9
0 0 0 0 0 Covered T1,T7,T8


LineNo. Expression -1-: 178 case (gen_wr_req.state_q) -2-: 181 if (gen_wr_req.dst_req) -3-: 185 if (dst_update_i) -4-: 188 if ((dst_qs_o != dst_qs_i)) -5-: 198 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Covered T2,T3,T4
StIdle 0 0 1 - Covered T9
StIdle 0 0 0 - Covered T1,T7,T8
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered

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