UART Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	37.890s	10.544ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.590s	48.924us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	16.801us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.560s	249.627us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.760s	50.849us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.100s	21.682us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	16.801us	20	20	100.00
		uart_csr_aliasing	0.760s	50.849us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.222m	98.009ms	50	50	100.00
V2	parity	uart_smoke	37.890s	10.544ms	50	50	100.00
		uart_tx_rx	3.222m	98.009ms	50	50	100.00
V2	parity_error	uart_intr	54.692m	2.417s	50	50	100.00
		uart_rx_parity_err	9.572m	280.382ms	50	50	100.00
V2	watermark	uart_tx_rx	3.222m	98.009ms	50	50	100.00
		uart_intr	54.692m	2.417s	50	50	100.00
V2	fifo_full	uart_fifo_full	10.201m	261.360ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.318m	128.893ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.412m	319.980ms	300	300	100.00
V2	rx_frame_err	uart_intr	54.692m	2.417s	50	50	100.00
V2	rx_break_err	uart_intr	54.692m	2.417s	50	50	100.00
V2	rx_timeout	uart_intr	54.692m	2.417s	50	50	100.00
V2	perf	uart_perf	27.307m	50.183ms	50	50	100.00
V2	sys_loopback	uart_loopback	20.750s	10.938ms	50	50	100.00
V2	line_loopback	uart_loopback	20.750s	10.938ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.519m	129.092ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.259m	48.444ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	33.460s	12.041ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	32.150s	2.839ms	43	50	86.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	25.134m	227.071ms	50	50	100.00
V2	stress_all	uart_stress_all	1.194h	2.713s	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	33.934m	362.926ms	100	100	100.00
V2	alert_test	uart_alert_test	0.660s	30.867us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	51.819us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.530s	117.191us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.530s	117.191us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.590s	48.924us	5	5	100.00
		uart_csr_rw	0.650s	16.801us	20	20	100.00
		uart_csr_aliasing	0.760s	50.849us	5	5	100.00
		uart_same_csr_outstanding	0.760s	35.515us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.590s	48.924us	5	5	100.00
		uart_csr_rw	0.650s	16.801us	20	20	100.00
		uart_csr_aliasing	0.760s	50.849us	5	5	100.00
		uart_same_csr_outstanding	0.760s	35.515us	20	20	100.00
V2		TOTAL			1183	1190	99.41
V2S	tl_intg_err	uart_sec_cm	0.810s	62.171us	5	5	100.00
		uart_tl_intg_err	1.400s	490.066us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.400s	490.066us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1313	1320	99.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	18	94.74
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.80	98.45	100.00	--	99.76	100.00	97.57

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: *

has 7 failures:

Test uart_rx_oversample has 7 failures.

7.uart_rx_oversample.1993393479
Line 221, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_rx_oversample/latest/run.log

  UVM_ERROR @ 870126393 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (59651 [0xe903] vs 55815 [0xda07]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_ERROR @ 878840670 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (40424 [0x9de8] vs 6865 [0x1ad1]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 887126509 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 7/8
  UVM_ERROR @ 887554947 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (40641 [0x9ec1] vs 7827 [0x1e93]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 905622496 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 8/8

27.uart_rx_oversample.2211478991
Line 215, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/27.uart_rx_oversample/latest/run.log

  UVM_ERROR @  17415652 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (45433 [0xb179] vs 25331 [0x62f3]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @  25954201 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 1/14
  UVM_INFO @ 234445895 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 2/14
  UVM_INFO @ 631646850 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 3/14
  UVM_ERROR @ 647418802 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (21885 [0x557d] vs 43770 [0xaafa]) Regname: uart_reg_block.val.rx reset value: 0x0

... and 5 more failures.