748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 24.920s | 5.491ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | uart_csr_hw_reset | 0.670s | 12.703us | 5 | 5 | 100.00 |
| V1 | csr_rw | uart_csr_rw | 0.660s | 54.765us | 19 | 20 | 95.00 |
| V1 | csr_bit_bash | uart_csr_bit_bash | 2.390s | 1.008ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | uart_csr_aliasing | 0.820s | 29.363us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 1.560s | 32.310us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0.660s | 54.765us | 19 | 20 | 95.00 |
| uart_csr_aliasing | 0.820s | 29.363us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 104 | 105 | 99.05 | |||
| V2 | base_random_seq | uart_tx_rx | 7.977m | 112.869ms | 50 | 50 | 100.00 |
| V2 | parity | uart_smoke | 24.920s | 5.491ms | 50 | 50 | 100.00 |
| uart_tx_rx | 7.977m | 112.869ms | 50 | 50 | 100.00 | ||
| V2 | parity_error | uart_intr | 50.886m | 2.198s | 47 | 50 | 94.00 |
| uart_rx_parity_err | 6.650m | 210.443ms | 50 | 50 | 100.00 | ||
| V2 | watermark | uart_tx_rx | 7.977m | 112.869ms | 50 | 50 | 100.00 |
| uart_intr | 50.886m | 2.198s | 47 | 50 | 94.00 | ||
| V2 | fifo_full | uart_fifo_full | 8.672m | 157.596ms | 49 | 50 | 98.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 8.349m | 249.071ms | 50 | 50 | 100.00 |
| V2 | fifo_reset | uart_fifo_reset | 8.633m | 203.842ms | 300 | 300 | 100.00 |
| V2 | rx_frame_err | uart_intr | 50.886m | 2.198s | 47 | 50 | 94.00 |
| V2 | rx_break_err | uart_intr | 50.886m | 2.198s | 47 | 50 | 94.00 |
| V2 | rx_timeout | uart_intr | 50.886m | 2.198s | 47 | 50 | 94.00 |
| V2 | perf | uart_perf | 25.755m | 25.609ms | 50 | 50 | 100.00 |
| V2 | sys_loopback | uart_loopback | 23.900s | 13.784ms | 45 | 50 | 90.00 |
| V2 | line_loopback | uart_loopback | 23.900s | 13.784ms | 45 | 50 | 90.00 |
| V2 | rx_noise_filter | uart_noise_filter | 3.766m | 149.694ms | 50 | 50 | 100.00 |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 1.056m | 40.433ms | 50 | 50 | 100.00 |
| V2 | tx_overide | uart_tx_ovrd | 39.840s | 5.956ms | 50 | 50 | 100.00 |
| V2 | rx_oversample | uart_rx_oversample | 30.940s | 4.039ms | 41 | 50 | 82.00 |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 22.297m | 189.643ms | 50 | 50 | 100.00 |
| V2 | stress_all | uart_stress_all | 55.625m | 2.012s | 47 | 50 | 94.00 |
| V2 | stress_all_with_reset | uart_stress_all_with_rand_reset | 31.055m | 128.323ms | 95 | 100 | 95.00 |
| V2 | alert_test | uart_alert_test | 0.620s | 23.653us | 50 | 50 | 100.00 |
| V2 | intr_test | uart_intr_test | 0.700s | 12.943us | 48 | 50 | 96.00 |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 2.370s | 1.182ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | uart_tl_errors | 2.370s | 1.182ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0.670s | 12.703us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.660s | 54.765us | 19 | 20 | 95.00 | ||
| uart_csr_aliasing | 0.820s | 29.363us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.750s | 14.129us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 0.670s | 12.703us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.660s | 54.765us | 19 | 20 | 95.00 | ||
| uart_csr_aliasing | 0.820s | 29.363us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.750s | 14.129us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1162 | 1190 | 97.65 | |||
| V2S | tl_intg_err | uart_sec_cm | 0.870s | 495.492us | 5 | 5 | 100.00 |
| uart_tl_intg_err | 1.380s | 1.011ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 1.380s | 1.011ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 1291 | 1320 | 97.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 19 | 19 | 12 | 63.16 |
| V2S | 2 | 2 | 2 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.26 | 99.79 | 98.45 | 100.00 | -- | 99.76 | 100.00 | 97.54 |
UVM_ERROR (uart_scoreboard.sv:529) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: uart_reg_block.rdata has 10 failures:
8.uart_loopback.68039237360203979116536143322070174049296227075651115350054970968823455260556
Line 255, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_loopback/latest/run.log
UVM_ERROR @ 4886790415 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60 [0x3c] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 4886790415 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 60 [0x3c]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 4887030415 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 8/19
UVM_INFO @ 5332310415 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/19
UVM_INFO @ 5426190415 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/19
15.uart_loopback.11949038842080918920047163056721180205695924035829671140090135607045404356208
Line 259, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_loopback/latest/run.log
UVM_ERROR @ 5833511581 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (246 [0xf6] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 5833511581 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 246 [0xf6]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 5833636579 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 12/15
UVM_INFO @ 6212130523 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 13/15
UVM_INFO @ 6253588193 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 14/15
... and 2 more failures.
10.uart_stress_all.90450100123820606787050493531653382977441104180191829111345194736330855050813
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_stress_all/latest/run.log
UVM_ERROR @ 4432322390 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (231 [0xe7] vs 157 [0x9d]) reg name: uart_reg_block.rdata
UVM_ERROR @ 4432322390 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (157 [0x9d] vs 231 [0xe7]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 4432472390 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 9/15
UVM_INFO @ 5427947390 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 10/15
UVM_INFO @ 5963847390 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 11/15
27.uart_stress_all.79914840893058495851715312035269846164198580574956344716073324950646846752575
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/27.uart_stress_all/latest/run.log
UVM_ERROR @ 3207004472 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (69 [0x45] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 3207004472 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 69 [0x45]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 3207222429 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 4/13
UVM_INFO @ 3304405609 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 5/13
UVM_INFO @ 4342739936 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/13
... and 1 more failures.
47.uart_stress_all_with_rand_reset.22556720528020946069308952460371700066774410903759277414386294473052237041201
Line 507, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26171525524 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (36 [0x24] vs 0 [0x0]) reg name: uart_reg_block.rdata
UVM_ERROR @ 26171525524 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 36 [0x24]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 26171643172 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 6/13
UVM_INFO @ 26179074604 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 7/13
UVM_INFO @ 26215584700 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 31/228
84.uart_stress_all_with_rand_reset.90867978480409161845771639206239197455000467574471496129809708387922327097300
Line 350, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5023038106 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (114 [0x72] vs 185 [0xb9]) reg name: uart_reg_block.rdata
UVM_ERROR @ 5023038106 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (185 [0xb9] vs 114 [0x72]) Regname: uart_reg_block.rdata reset value: 0x0
UVM_INFO @ 5023099330 ps: (uart_loopback_vseq.sv:30) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_loopback_vseq] finished run 3/8
UVM_INFO @ 5059496998 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 36/455
UVM_INFO @ 5114425130 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 37/455
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 9 failures:
3.uart_rx_oversample.99565974166486878372962239751143366678335841573186228374481652832905680895956
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_rx_oversample/latest/run.log
UVM_ERROR @ 89324994 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (28913 [0x70f1] vs 14577 [0x38f1]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 125275986 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/13
UVM_INFO @ 445262360 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/13
UVM_INFO @ 464683740 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/13
UVM_INFO @ 779108180 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 7/13
4.uart_rx_oversample.172392021252505367774322079269934343395229700680471885589328145087909967946
Line 257, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_rx_oversample/latest/run.log
UVM_ERROR @ 520444959 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (58663 [0xe527] vs 29331 [0x7293]) Regname: uart_reg_block.val.rx reset value: 0x0
UVM_INFO @ 545689821 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 10/18
UVM_INFO @ 757966844 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 11/18
UVM_INFO @ 1181343575 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 12/18
UVM_INFO @ 1216875681 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 13/18
... and 7 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:
Test uart_csr_rw has 1 failures.
17.uart_csr_rw.46497492231332531824151541351816516885244765215604759852969714267743021174766
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_csr_rw/latest/run.log
[make]: simulate
cd /workspace/17.uart_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448087534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1448087534
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test uart_intr_test has 2 failures.
19.uart_intr_test.6604300950964767865025466393538520992009318694827689441985411284161753695475
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_intr_test/latest/run.log
[make]: simulate
cd /workspace/19.uart_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118201587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.4118201587
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
20.uart_intr_test.97889446670236732008887164110182534866702601217203507709747628267294475246445
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_intr_test/latest/run.log
[make]: simulate
cd /workspace/20.uart_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753387373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2753387373
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test uart_fifo_full has 1 failures.
34.uart_fifo_full.77177989526197388941339424461267872105050783914529232075129195553841249978229
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/34.uart_fifo_full/latest/run.log
[make]: simulate
cd /workspace/34.uart_fifo_full/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477038453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.477038453
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:
15.uart_stress_all_with_rand_reset.288891927906294280527837333188550287820696760927437882041547601775102150620
Line 397, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 37155328012 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 37155328012 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 37534828012 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 26/114
UVM_INFO @ 37860578012 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 27/114
UVM_INFO @ 38353428012 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 28/114
52.uart_stress_all_with_rand_reset.77641049013196829316454174336876958087618461191673475256749977149077889180864
Line 536, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 59468492786 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 59468492786 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_INFO @ 59669012786 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 142/330
UVM_INFO @ 59722212786 ps: (uart_tx_rx_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 1/10
UVM_INFO @ 60139052786 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 143/330
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark has 1 failures:
18.uart_loopback.11539318667489549786013012925548678934413723225234965468373347977976152158097
Line 265, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_loopback/latest/run.log
UVM_ERROR @ 8760470681 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 8760470681 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
UVM_INFO @ 8765557637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job uart-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
26.uart_intr.56934249912950992695248143929575267408764534762681262033282247046349330599644
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/26.uart_intr/latest/run.log
Job ID: smart:e0b4e451-4f7a-4d7b-899b-6241db4cef9c
UVM_ERROR (uart_intr_vseq.sv:252) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:
43.uart_intr.64449922023531660307256013972039364101064297266504750546137367259852983639509
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/43.uart_intr/latest/run.log
UVM_ERROR @ 499333989 ps: (uart_intr_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 499333989 ps: (uart_intr_vseq.sv:254) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (0 [0x0] vs 1 [0x1]) uart_intr name/val: TxWatermark/0, en_intr: a3
UVM_INFO @ 733001123 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
Testing RxTimeout
UVM_INFO @ 22704545066 ps: (uart_intr_vseq.sv:32) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
49.uart_intr.87007627115822088548353755610316524542832703554948601809277440528749806351512
Line 318, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/49.uart_intr/latest/run.log
UVM_FATAL @ 3000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 3000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---