UART Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	36.640s	11.109ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	17.892us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	49.094us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.450s	262.560us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.790s	26.231us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.130s	84.020us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	49.094us	20	20	100.00
		uart_csr_aliasing	0.790s	26.231us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.854m	103.147ms	50	50	100.00
V2	parity	uart_smoke	36.640s	11.109ms	50	50	100.00
		uart_tx_rx	3.854m	103.147ms	50	50	100.00
V2	parity_error	uart_intr	6.981m	309.923ms	50	50	100.00
		uart_rx_parity_err	4.941m	86.618ms	50	50	100.00
V2	watermark	uart_tx_rx	3.854m	103.147ms	50	50	100.00
		uart_intr	6.981m	309.923ms	50	50	100.00
V2	fifo_full	uart_fifo_full	8.694m	138.905ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.832m	225.596ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	13.444m	98.464ms	300	300	100.00
V2	rx_frame_err	uart_intr	6.981m	309.923ms	50	50	100.00
V2	rx_break_err	uart_intr	6.981m	309.923ms	50	50	100.00
V2	rx_timeout	uart_intr	6.981m	309.923ms	50	50	100.00
V2	perf	uart_perf	15.508m	19.985ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.760s	8.616ms	50	50	100.00
V2	line_loopback	uart_loopback	21.760s	8.616ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	1.553m	48.487ms	7	50	14.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	57.690s	33.544ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	43.140s	13.105ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.095m	7.506ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	26.998m	171.456ms	48	50	96.00
V2	stress_all	uart_stress_all	23.622m	133.192ms	37	50	74.00
V2	alert_test	uart_alert_test	0.610s	40.149us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	22.484us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.280s	113.249us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.280s	113.249us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	17.892us	5	5	100.00
		uart_csr_rw	0.680s	49.094us	20	20	100.00
		uart_csr_aliasing	0.790s	26.231us	5	5	100.00
		uart_same_csr_outstanding	0.770s	31.819us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	17.892us	5	5	100.00
		uart_csr_rw	0.680s	49.094us	20	20	100.00
		uart_csr_aliasing	0.790s	26.231us	5	5	100.00
		uart_same_csr_outstanding	0.770s	31.819us	20	20	100.00
V2		TOTAL			1032	1090	94.68
V2S	tl_intg_err	uart_sec_cm	0.830s	220.165us	5	5	100.00
		uart_tl_intg_err	1.360s	90.069us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.360s	90.069us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	31.014m	91.060ms	60	100	60.00
V3		TOTAL			60	100	60.00
		TOTAL			1222	1320	92.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.55

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 49 failures:

Test uart_noise_filter has 20 failures.

1.uart_noise_filter.114738889478490748864196320669822114391488840409993553451730707584749920213469
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_noise_filter/latest/run.log

  UVM_ERROR @  23701499 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  29181499 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  29541499 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  29821499 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  30101499 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

4.uart_noise_filter.115616530418611762711445179141726627206373536005234652957013097654498208855319
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_noise_filter/latest/run.log

  UVM_ERROR @  24853991 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  27353971 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  30675373 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 245673653 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 252423599 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 18 more failures.

Test uart_stress_all has 7 failures.

2.uart_stress_all.36667197658498830472971513135195798863120956928898499342211210487987657861550
Line 269, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all/latest/run.log

  UVM_ERROR @ 31618585329 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 31618689499 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 31618793669 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 31618897839 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 31619002009 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

4.uart_stress_all.16070937503542999901816851446229577396183349456941898845387681660822686193590
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_stress_all/latest/run.log

  UVM_ERROR @ 5038774040 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 5038774040 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 6550164040 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 6550164040 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 7702184040 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1

... and 5 more failures.

Test uart_stress_all_with_rand_reset has 22 failures.

3.uart_stress_all_with_rand_reset.67375193519068949137339869561875344998574153681666894324299488236553285556859
Line 351, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17463518175 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 17463518175 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_INFO @ 17509258175 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 59/689
  UVM_ERROR @ 17524718175 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 17524718175 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

9.uart_stress_all_with_rand_reset.43325135291430523661421836048645601886020201402752326519686982724394748910134
Line 839, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 763630601688 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 763637173110 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 763644030246 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 763650887382 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 763658601660 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 20 more failures.

UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 26 failures:

Test uart_noise_filter has 13 failures.

0.uart_noise_filter.58858692471924936859064575705187392036100848119503918903623998174235756027428
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_noise_filter/latest/run.log

  UVM_ERROR @ 57999746763 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 57999794382 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 58000175334 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 59289174045 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 59289221664 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

3.uart_noise_filter.112944035839383153535498543832051642572447556185623958345234177478299688497087
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_noise_filter/latest/run.log

  UVM_ERROR @ 2337281643 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 2337291643 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 2337301643 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 2429751643 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 2429751643 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1

... and 11 more failures.

Test uart_stress_all_with_rand_reset has 10 failures.

2.uart_stress_all_with_rand_reset.95886250231266572504506065656134814688574453551208123789549141525714740314465
Line 1142, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 284954909433 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 57,                                 clk_pulses: 0
  UVM_ERROR @ 284954957052 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 284955004671 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 284955052290 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 284955099909 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata

28.uart_stress_all_with_rand_reset.29423205328377253255576934288770091888103605652691432583527888801024627089710
Line 788, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 44681837432 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 44681847533 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 44681948543 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 44688382880 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 44688382880 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1

... and 8 more failures.

Test uart_stress_all has 2 failures.

7.uart_stress_all.12505573080310819504350783253778734241402424226452633817722006703416574890586
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_stress_all/latest/run.log

  UVM_ERROR @ 352807925 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
  UVM_ERROR @ 352827925 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 352847925 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 536847925 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 536847925 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

32.uart_stress_all.101016679857129152074979405357881587575192905324216256432373421454251163236972
Line 334, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/32.uart_stress_all/latest/run.log

  UVM_ERROR @ 188926448433 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 188926488433 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 188926528433 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (208 [0xd0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 188927208433 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 188927248433 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

Test uart_long_xfer_wo_dly has 1 failures.

44.uart_long_xfer_wo_dly.115474727198358070671685355726274446862260924092466188978452851720307900080366
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 94730413832 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 98259324416 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 102542535152 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 7/10
  UVM_INFO @ 103854369176 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 8/10
  UVM_INFO @ 114386453432 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 9/10

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 14 failures:

Test uart_noise_filter has 6 failures.

14.uart_noise_filter.17107362817660165712701181015640556752316460916756249631884588556731955999989
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_noise_filter/latest/run.log

  UVM_ERROR @  98569573 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @  98569573 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  98569573 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 141847697 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 243737401 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0

19.uart_noise_filter.102199619637084064099134831597634467531033831859049577984104749744067548465042
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_noise_filter/latest/run.log

  UVM_ERROR @ 3917700929 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 4474747052 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 2 (+/-1), act: 9,                                 clk_pulses: 0
  UVM_ERROR @ 4474830386 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (110 [0x6e] vs 159 [0x9f]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 4474913720 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (131 [0x83] vs 223 [0xdf]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 4474955387 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

... and 4 more failures.

Test uart_stress_all has 3 failures.

26.uart_stress_all.96547145773528839390934827521027752915748313734348344084457472378295508883304
Line 276, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/26.uart_stress_all/latest/run.log

  UVM_ERROR @ 196306627356 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 196306627356 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 196306627356 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 196308203112 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 11
  UVM_ERROR @ 196308233415 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

46.uart_stress_all.19262673666540436283998997700269430779806962751829143488492336997370780775426
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/46.uart_stress_all/latest/run.log

  UVM_ERROR @ 892553045 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 892553045 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 892553045 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 1027259981 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 1027280183 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (24 [0x18] vs 253 [0xfd]) reg name: uart_reg_block.rdata

... and 1 more failures.

Test uart_stress_all_with_rand_reset has 5 failures.

44.uart_stress_all_with_rand_reset.32949226239671845274536713235897480263652399776775193101263705226828093861047
Line 664, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 43736257887 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 43736257887 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 43736257887 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_INFO @ 43747277887 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/607
  UVM_ERROR @ 43770677887 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 11,                                 clk_pulses: 0

52.uart_stress_all_with_rand_reset.16568789750554094826064312332577918593979408551925087238442763656835662817537
Line 319, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 23230394485 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 23230394485 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 23230394485 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_INFO @ 23500954485 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 31/973
  UVM_ERROR @ 23713194485 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 3 more failures.

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr has 3 failures:

Test uart_noise_filter has 2 failures.

2.uart_noise_filter.80814243507381412291991269399996966672424099039170947831108221862540097335129
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_noise_filter/latest/run.log

  UVM_ERROR @ 327933568 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 328944064 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 329765092 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 330375600 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 369774418 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

35.uart_noise_filter.103437402494524624863813531464149724277369304014856495272769883904016368419926
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/35.uart_noise_filter/latest/run.log

  UVM_ERROR @ 2299659812 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 2459992985 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 3406769816 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 3406769816 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 3406769816 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark

Test uart_stress_all_with_rand_reset has 1 failures.

8.uart_stress_all_with_rand_reset.25128595601864176865606611978343930067020326877035531389280227559189694184546
Line 554, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 134040456664 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 134040456664 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 134040456664 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
  UVM_INFO @ 134047509352 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 41/133
  UVM_ERROR @ 134071351648 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark has 2 failures:

Test uart_noise_filter has 1 failures.

7.uart_noise_filter.52059423989852081974957464838116911465131755727762220666993130389167298494085
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_noise_filter/latest/run.log

  UVM_ERROR @  61724283 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @  63578509 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0
  UVM_ERROR @  63588926 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @  63599343 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 326222330 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0

Test uart_stress_all_with_rand_reset has 1 failures.

7.uart_stress_all_with_rand_reset.77461334619534698307892127814544605670407908694063873594319346544340092959347
Line 335, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15413145955 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 15413145955 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
  UVM_INFO @ 15665147971 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/397
  UVM_ERROR @ 15719898409 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
  UVM_ERROR @ 15719898409 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 2 failures:

Test uart_long_xfer_wo_dly has 1 failures.

12.uart_long_xfer_wo_dly.1701874737704098473415409235650630587953194861736780069984064288062683135751
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @   8188447 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 33011345441 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/5
  UVM_INFO @ 70595474715 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/5
  UVM_INFO @ 91187511008 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/5
  UVM_INFO @ 114788895681 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/5

Test uart_stress_all has 1 failures.

27.uart_stress_all.14477697327578436139432974785843014212366714485680676379230412255293791919118
Line 272, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/27.uart_stress_all/latest/run.log

  UVM_ERROR @ 58574287457 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 59721004964 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr
  UVM_INFO @ 60868847480 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:

Test uart_noise_filter has 1 failures.

27.uart_noise_filter.59370277723787241013426046197700407756223847866232198374299278413299177194474
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/27.uart_noise_filter/latest/run.log

  UVM_ERROR @ 223643653 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 223643653 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @ 223643653 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 769768653 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 903393653 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0

Test uart_stress_all_with_rand_reset has 1 failures.

65.uart_stress_all_with_rand_reset.30783677318214626506005118842288360267710816777708597546910045338782266036327
Line 538, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 497842168409 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 497842168409 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @ 498294168409 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 498294168409 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 498294168409 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1