a182fcef27
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | uart_smoke | 1.048m | 11.063ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | uart_csr_hw_reset | 0.640s | 18.372us | 5 | 5 | 100.00 |
V1 | csr_rw | uart_csr_rw | 0.660s | 11.166us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | uart_csr_bit_bash | 2.230s | 650.938us | 5 | 5 | 100.00 |
V1 | csr_aliasing | uart_csr_aliasing | 0.740s | 15.231us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 1.530s | 108.938us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0.660s | 11.166us | 20 | 20 | 100.00 |
uart_csr_aliasing | 0.740s | 15.231us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | base_random_seq | uart_tx_rx | 4.454m | 116.001ms | 50 | 50 | 100.00 |
V2 | parity | uart_smoke | 1.048m | 11.063ms | 50 | 50 | 100.00 |
uart_tx_rx | 4.454m | 116.001ms | 50 | 50 | 100.00 | ||
V2 | parity_error | uart_intr | 20.382m | 394.270ms | 49 | 50 | 98.00 |
uart_rx_parity_err | 5.104m | 155.863ms | 50 | 50 | 100.00 | ||
V2 | watermark | uart_tx_rx | 4.454m | 116.001ms | 50 | 50 | 100.00 |
uart_intr | 20.382m | 394.270ms | 49 | 50 | 98.00 | ||
V2 | fifo_full | uart_fifo_full | 12.012m | 240.055ms | 50 | 50 | 100.00 |
V2 | fifo_overflow | uart_fifo_overflow | 4.155m | 107.271ms | 50 | 50 | 100.00 |
V2 | fifo_reset | uart_fifo_reset | 8.433m | 108.070ms | 300 | 300 | 100.00 |
V2 | rx_frame_err | uart_intr | 20.382m | 394.270ms | 49 | 50 | 98.00 |
V2 | rx_break_err | uart_intr | 20.382m | 394.270ms | 49 | 50 | 98.00 |
V2 | rx_timeout | uart_intr | 20.382m | 394.270ms | 49 | 50 | 98.00 |
V2 | perf | uart_perf | 23.614m | 27.245ms | 50 | 50 | 100.00 |
V2 | sys_loopback | uart_loopback | 24.320s | 12.692ms | 50 | 50 | 100.00 |
V2 | line_loopback | uart_loopback | 24.320s | 12.692ms | 50 | 50 | 100.00 |
V2 | rx_noise_filter | uart_noise_filter | 7.142m | 151.757ms | 50 | 50 | 100.00 |
V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 1.282m | 49.113ms | 50 | 50 | 100.00 |
V2 | tx_overide | uart_tx_ovrd | 24.990s | 6.740ms | 50 | 50 | 100.00 |
V2 | rx_oversample | uart_rx_oversample | 59.820s | 6.875ms | 50 | 50 | 100.00 |
V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 22.972m | 162.213ms | 50 | 50 | 100.00 |
V2 | stress_all | uart_stress_all | 32.279m | 417.181ms | 49 | 50 | 98.00 |
V2 | alert_test | uart_alert_test | 0.620s | 34.258us | 50 | 50 | 100.00 |
V2 | intr_test | uart_intr_test | 0.650s | 13.509us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | uart_tl_errors | 2.520s | 517.342us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | uart_tl_errors | 2.520s | 517.342us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0.640s | 18.372us | 5 | 5 | 100.00 |
uart_csr_rw | 0.660s | 11.166us | 20 | 20 | 100.00 | ||
uart_csr_aliasing | 0.740s | 15.231us | 5 | 5 | 100.00 | ||
uart_same_csr_outstanding | 0.790s | 60.065us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | uart_csr_hw_reset | 0.640s | 18.372us | 5 | 5 | 100.00 |
uart_csr_rw | 0.660s | 11.166us | 20 | 20 | 100.00 | ||
uart_csr_aliasing | 0.740s | 15.231us | 5 | 5 | 100.00 | ||
uart_same_csr_outstanding | 0.790s | 60.065us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1088 | 1090 | 99.82 | |||
V2S | tl_intg_err | uart_sec_cm | 0.900s | 123.233us | 5 | 5 | 100.00 |
uart_tl_intg_err | 1.430s | 96.076us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | uart_tl_intg_err | 1.430s | 96.076us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | uart_stress_all_with_rand_reset | 33.168m | 58.195ms | 99 | 100 | 99.00 |
V3 | TOTAL | 99 | 100 | 99.00 | |||
TOTAL | 1317 | 1320 | 99.77 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 18 | 18 | 16 | 88.89 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
99.27 | 99.27 | 97.95 | 100.00 | -- | 98.80 | 100.00 | 99.59 |
UVM_ERROR (uart_scoreboard.sv:495) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
has 1 failures:
16.uart_stress_all.113969979919161817472445292408202054660882329992154244074116461556576556497578
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/16.uart_stress_all/latest/run.log
UVM_ERROR @ 56342354742 ps: (uart_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_INFO @ 56659180806 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 6/6
UVM_INFO @ 63518823918 ps: (uart_stress_all_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_stress_all_vseq] starting stress_all sub-sequence uart_smoke_vseq
UVM_INFO @ 69332123736 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_smoke_vseq] finished run 1/2
UVM_INFO @ 69726167694 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_smoke_vseq] finished run 2/2
UVM_ERROR (uart_intr_vseq.sv:278) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*])
has 1 failures:
37.uart_intr.1319409525551513825509517386762055144901666318191186265476669237229730415181
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_intr/latest/run.log
UVM_ERROR @ 2594170188 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 2594170188 ps: (uart_intr_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 75
UVM_ERROR @ 2780370188 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 2780370188 ps: (uart_intr_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 75
UVM_ERROR @ 3000370188 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
UVM_ERROR (uart_scoreboard.sv:372) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *
has 1 failures:
91.uart_stress_all_with_rand_reset.93349488001051751638001087901411878726214209917652013960950008196619981796984
Line 479, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 103569518942 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_INFO @ 103938639542 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 20/76
UVM_ERROR @ 104279936390 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_INFO @ 104614997894 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 21/76
UVM_INFO @ 105319591766 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 22/76