UART Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	27.780s	6.070ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	15.007us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	34.980us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.480s	182.666us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	62.715us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.450s	126.326us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	34.980us	20	20	100.00
		uart_csr_aliasing	0.780s	62.715us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.291m	85.081ms	50	50	100.00
V2	parity	uart_smoke	27.780s	6.070ms	50	50	100.00
		uart_tx_rx	3.291m	85.081ms	50	50	100.00
V2	parity_error	uart_intr	11.162m	370.850ms	49	50	98.00
		uart_rx_parity_err	10.960m	133.616ms	50	50	100.00
V2	watermark	uart_tx_rx	3.291m	85.081ms	50	50	100.00
		uart_intr	11.162m	370.850ms	49	50	98.00
V2	fifo_full	uart_fifo_full	11.383m	265.100ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.692m	144.329ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.668m	280.277ms	300	300	100.00
V2	rx_frame_err	uart_intr	11.162m	370.850ms	49	50	98.00
V2	rx_break_err	uart_intr	11.162m	370.850ms	49	50	98.00
V2	rx_timeout	uart_intr	11.162m	370.850ms	49	50	98.00
V2	perf	uart_perf	22.123m	24.193ms	50	50	100.00
V2	sys_loopback	uart_loopback	25.750s	10.645ms	50	50	100.00
V2	line_loopback	uart_loopback	25.750s	10.645ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	6.958m	215.033ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.352m	46.812ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	30.950s	12.235ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.159m	7.104ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	34.017m	211.795ms	50	50	100.00
V2	stress_all	uart_stress_all	41.798m	373.614ms	50	50	100.00
V2	alert_test	uart_alert_test	0.630s	18.382us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	63.975us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.370s	211.932us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.370s	211.932us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	15.007us	5	5	100.00
		uart_csr_rw	0.680s	34.980us	20	20	100.00
		uart_csr_aliasing	0.780s	62.715us	5	5	100.00
		uart_same_csr_outstanding	0.780s	29.289us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	15.007us	5	5	100.00
		uart_csr_rw	0.680s	34.980us	20	20	100.00
		uart_csr_aliasing	0.780s	62.715us	5	5	100.00
		uart_same_csr_outstanding	0.780s	29.289us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.850s	59.423us	5	5	100.00
		uart_tl_intg_err	1.360s	72.432us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.360s	72.432us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	34.229m	1.712s	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.27	97.95	100.00	--	98.80	100.00	99.61

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:439) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark

has 1 failures:

Test uart_intr has 1 failures.

1.uart_intr.30684305683372806169810180719088838038377276969002898799240103957696497784545
Line 264, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_intr/latest/run.log

  UVM_ERROR @ 19593472465 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 19681361266 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/3
  UVM_INFO @ 19681657562 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark
  UVM_INFO @ 20073397911 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]