UART Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	37.700s	6.283ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	49.441us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	49.661us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.340s	1.278ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.790s	78.642us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.490s	34.003us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	49.661us	20	20	100.00
		uart_csr_aliasing	0.790s	78.642us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.365m	128.523ms	50	50	100.00
V2	parity	uart_smoke	37.700s	6.283ms	50	50	100.00
		uart_tx_rx	4.365m	128.523ms	50	50	100.00
V2	parity_error	uart_intr	11.990m	461.764ms	50	50	100.00
		uart_rx_parity_err	7.574m	177.278ms	50	50	100.00
V2	watermark	uart_tx_rx	4.365m	128.523ms	50	50	100.00
		uart_intr	11.990m	461.764ms	50	50	100.00
V2	fifo_full	uart_fifo_full	9.449m	209.424ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.956m	98.205ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	12.321m	223.362ms	300	300	100.00
V2	rx_frame_err	uart_intr	11.990m	461.764ms	50	50	100.00
V2	rx_break_err	uart_intr	11.990m	461.764ms	50	50	100.00
V2	rx_timeout	uart_intr	11.990m	461.764ms	50	50	100.00
V2	perf	uart_perf	25.058m	25.477ms	50	50	100.00
V2	sys_loopback	uart_loopback	31.280s	7.597ms	50	50	100.00
V2	line_loopback	uart_loopback	31.280s	7.597ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	6.235m	159.245ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.012m	39.056ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	43.920s	6.258ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.047m	7.319ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	25.115m	163.742ms	50	50	100.00
V2	stress_all	uart_stress_all	35.932m	136.136ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	12.555us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	14.821us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.400s	110.977us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.400s	110.977us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	49.441us	5	5	100.00
		uart_csr_rw	0.660s	49.661us	20	20	100.00
		uart_csr_aliasing	0.790s	78.642us	5	5	100.00
		uart_same_csr_outstanding	0.800s	35.298us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	49.441us	5	5	100.00
		uart_csr_rw	0.660s	49.661us	20	20	100.00
		uart_csr_aliasing	0.790s	78.642us	5	5	100.00
		uart_same_csr_outstanding	0.800s	35.298us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.880s	448.307us	5	5	100.00
		uart_tl_intg_err	1.360s	311.169us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.360s	311.169us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	40.735m	129.346ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1320	1320	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.48

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