UART Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	34.210s	11.098ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.650s	20.561us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	48.937us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.510s	170.192us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.800s	30.716us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.400s	132.537us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	48.937us	20	20	100.00
		uart_csr_aliasing	0.800s	30.716us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.201m	84.426ms	50	50	100.00
V2	parity	uart_smoke	34.210s	11.098ms	50	50	100.00
		uart_tx_rx	5.201m	84.426ms	50	50	100.00
V2	parity_error	uart_intr	14.256m	318.282ms	50	50	100.00
		uart_rx_parity_err	5.074m	81.833ms	50	50	100.00
V2	watermark	uart_tx_rx	5.201m	84.426ms	50	50	100.00
		uart_intr	14.256m	318.282ms	50	50	100.00
V2	fifo_full	uart_fifo_full	7.274m	144.085ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.986m	88.655ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.241m	246.297ms	300	300	100.00
V2	rx_frame_err	uart_intr	14.256m	318.282ms	50	50	100.00
V2	rx_break_err	uart_intr	14.256m	318.282ms	50	50	100.00
V2	rx_timeout	uart_intr	14.256m	318.282ms	50	50	100.00
V2	perf	uart_perf	34.462m	37.226ms	50	50	100.00
V2	sys_loopback	uart_loopback	16.890s	7.308ms	50	50	100.00
V2	line_loopback	uart_loopback	16.890s	7.308ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.785m	141.017ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.261m	46.645ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	37.970s	12.363ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.112m	7.759ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.447m	157.403ms	50	50	100.00
V2	stress_all	uart_stress_all	34.860m	436.368ms	49	50	98.00
V2	alert_test	uart_alert_test	0.630s	11.052us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	61.572us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.300s	48.850us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.300s	48.850us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.650s	20.561us	5	5	100.00
		uart_csr_rw	0.680s	48.937us	20	20	100.00
		uart_csr_aliasing	0.800s	30.716us	5	5	100.00
		uart_same_csr_outstanding	0.800s	122.477us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.650s	20.561us	5	5	100.00
		uart_csr_rw	0.680s	48.937us	20	20	100.00
		uart_csr_aliasing	0.800s	30.716us	5	5	100.00
		uart_same_csr_outstanding	0.800s	122.477us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	1.030s	447.056us	5	5	100.00
		uart_tl_intg_err	1.420s	89.944us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.420s	89.944us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	29.176m	108.521ms	96	100	96.00
V3		TOTAL			96	100	96.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.27	97.95	100.00	--	98.80	100.00	99.50

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:752) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

32.uart_stress_all_with_rand_reset.83056280472858181021844937471246005756520791452627560861073192687744785329041
Line 1660, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 92818470624 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 92818470624 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 92818533780 ps: (cip_base_vseq.sv:763) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 8/10

70.uart_stress_all_with_rand_reset.49851636247292847865804125562255003393601247775501884574400309047491112410238
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   3694087 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @   3694087 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @   3756589 ps: (cip_base_vseq.sv:763) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/10

UVM_ERROR (uart_scoreboard.sv:495) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

Test uart_stress_all has 1 failures.

29.uart_stress_all.15011058008061593656203229250046927348317268887295173272016035482197717248914
Line 262, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/29.uart_stress_all/latest/run.log

  UVM_ERROR @ 89934810729 ps: (uart_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 91594412241 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 91984121241 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 92322300417 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 92486242905 ps: (uart_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0

UVM_ERROR (uart_intr_vseq.sv:291) [uart_intr_vseq] Check failed act_intr_state & exp_mask == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

49.uart_stress_all_with_rand_reset.21988982757137958306249276250139595115170449995563566311898961781156401065013
Line 634, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 492253940761 ps: (uart_intr_vseq.sv:291) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state & exp_mask == exp (16 [0x10] vs 0 [0x0])
  UVM_ERROR @ 492253940761 ps: (uart_intr_vseq.sv:293) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[NumUartIntr-1:0] & exp_mask == exp_pin (16 [0x10] vs 0 [0x0]) uart_intr val: 0, en_intr: dc
  UVM_INFO @ 493632110184 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/3
  UVM_INFO @ 493637610195 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr

UVM_ERROR (uart_scoreboard.sv:439) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

59.uart_stress_all_with_rand_reset.41418135299831820184176816666021400106262871483577522804743003403926556643186
Line 571, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 43743916313 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 43766091313 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 119/619
  UVM_INFO @ 43804866313 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr
  UVM_INFO @ 43849366313 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]