UART Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.139m	6.102ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	54.907us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	23.510us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.400s	176.959us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.810s	25.594us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.420s	108.842us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	23.510us	20	20	100.00
		uart_csr_aliasing	0.810s	25.594us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	7.921m	152.975ms	50	50	100.00
V2	parity	uart_smoke	1.139m	6.102ms	50	50	100.00
		uart_tx_rx	7.921m	152.975ms	50	50	100.00
V2	parity_error	uart_intr	7.907m	380.024ms	50	50	100.00
		uart_rx_parity_err	9.185m	132.157ms	50	50	100.00
V2	watermark	uart_tx_rx	7.921m	152.975ms	50	50	100.00
		uart_intr	7.907m	380.024ms	50	50	100.00
V2	fifo_full	uart_fifo_full	7.746m	216.938ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.973m	176.551ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.771m	129.532ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.907m	380.024ms	50	50	100.00
V2	rx_break_err	uart_intr	7.907m	380.024ms	50	50	100.00
V2	rx_timeout	uart_intr	7.907m	380.024ms	50	50	100.00
V2	perf	uart_perf	24.522m	26.632ms	50	50	100.00
V2	sys_loopback	uart_loopback	28.840s	8.014ms	50	50	100.00
V2	line_loopback	uart_loopback	28.840s	8.014ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.546m	42.971ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.889m	68.787ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	31.460s	6.459ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.098m	7.054ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	29.485m	249.733ms	50	50	100.00
V2	stress_all	uart_stress_all	45.026m	228.997ms	49	50	98.00
V2	alert_test	uart_alert_test	0.620s	26.216us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	31.307us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.530s	116.824us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.530s	116.824us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	54.907us	5	5	100.00
		uart_csr_rw	0.660s	23.510us	20	20	100.00
		uart_csr_aliasing	0.810s	25.594us	5	5	100.00
		uart_same_csr_outstanding	0.790s	48.948us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	54.907us	5	5	100.00
		uart_csr_rw	0.660s	23.510us	20	20	100.00
		uart_csr_aliasing	0.810s	25.594us	5	5	100.00
		uart_same_csr_outstanding	0.790s	48.948us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.860s	55.143us	5	5	100.00
		uart_tl_intg_err	1.400s	330.192us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.400s	330.192us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	44.218m	175.419ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1318	1320	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.27	97.95	100.00	--	98.80	100.00	99.55

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:439) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

21.uart_stress_all_with_rand_reset.47094239875984628300014893225901199527450299726267756060421621293406062107226
Line 509, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13078012116 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 13122523957 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 13138378631 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 30/767
  UVM_INFO @ 13190515716 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 31/767

UVM_ERROR (uart_scoreboard.sv:372) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_stress_all has 1 failures.

21.uart_stress_all.83978770525300285894618797142114273067674413279132366020278741430833312499629
Line 285, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_stress_all/latest/run.log

  UVM_ERROR @ 28280769110 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 28802773286 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 30094018910 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 30411315566 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 30586140494 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1