UART Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	39.610s	11.050ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	19.358us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.670s	118.754us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.620s	302.688us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	218.123us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.480s	168.007us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.670s	118.754us	20	20	100.00
		uart_csr_aliasing	0.820s	218.123us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.519m	96.359ms	50	50	100.00
V2	parity	uart_smoke	39.610s	11.050ms	50	50	100.00
		uart_tx_rx	3.519m	96.359ms	50	50	100.00
V2	parity_error	uart_intr	11.239m	392.973ms	49	50	98.00
		uart_rx_parity_err	4.694m	91.435ms	50	50	100.00
V2	watermark	uart_tx_rx	3.519m	96.359ms	50	50	100.00
		uart_intr	11.239m	392.973ms	49	50	98.00
V2	fifo_full	uart_fifo_full	8.998m	152.750ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.117m	113.130ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.853m	273.285ms	299	300	99.67
V2	rx_frame_err	uart_intr	11.239m	392.973ms	49	50	98.00
V2	rx_break_err	uart_intr	11.239m	392.973ms	49	50	98.00
V2	rx_timeout	uart_intr	11.239m	392.973ms	49	50	98.00
V2	perf	uart_perf	32.017m	31.501ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.220s	12.038ms	50	50	100.00
V2	line_loopback	uart_loopback	21.220s	12.038ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	7.397m	168.070ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	47.660s	34.862ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	34.400s	12.450ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.119m	7.911ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.798m	181.302ms	50	50	100.00
V2	stress_all	uart_stress_all	25.864m	217.400ms	50	50	100.00
V2	alert_test	uart_alert_test	0.640s	41.098us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	19.720us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.320s	712.053us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.320s	712.053us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	19.358us	5	5	100.00
		uart_csr_rw	0.670s	118.754us	20	20	100.00
		uart_csr_aliasing	0.820s	218.123us	5	5	100.00
		uart_same_csr_outstanding	0.810s	360.525us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	19.358us	5	5	100.00
		uart_csr_rw	0.670s	118.754us	20	20	100.00
		uart_csr_aliasing	0.820s	218.123us	5	5	100.00
		uart_same_csr_outstanding	0.810s	360.525us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.870s	528.624us	5	5	100.00
		uart_tl_intg_err	1.430s	87.400us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.430s	87.400us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	31.677m	242.580ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1316	1320	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.10	97.65	100.00	--	98.38	100.00	99.41

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

Test uart_intr has 1 failures.

17.uart_intr.87176559231731368189166895556151342625810692325711368017463570412254844386465
Line 262, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_intr/latest/run.log

  UVM_ERROR @ 13038185166 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 13086255166 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 13181775166 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr

Test uart_stress_all_with_rand_reset has 1 failures.

17.uart_stress_all_with_rand_reset.8251727324735935152622247456265806908414011037913311449106406862076551129715
Line 893, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 124992202849 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 125041573170 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 125097647188 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/436
  UVM_INFO @ 125147943434 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_fifo_reset has 1 failures.

63.uart_fifo_reset.34216682941818982979540010914639671454657761829387709731963408446141811949438
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/63.uart_fifo_reset/latest/run.log

  UVM_ERROR @  12401018 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 2753501018 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/5
  UVM_INFO @ 14060301018 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/5
  UVM_INFO @ 48731001018 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/5
  UVM_INFO @ 80486801018 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/5

UVM_ERROR (uart_intr_vseq.sv:312) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

89.uart_stress_all_with_rand_reset.38588627116974008107483620417932368945824753877980808245742199363984787839322
Line 320, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 25408476269 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 25408476269 ps: (uart_intr_vseq.sv:314) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 167
  UVM_ERROR @ 25683310152 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 25683310152 ps: (uart_intr_vseq.sv:314) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 167
  UVM_ERROR @ 25960310706 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])