UART Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	34.280s	6.072ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	16.246us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	16.515us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.630s	1.034ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.840s	112.388us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.340s	28.285us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	16.515us	20	20	100.00
		uart_csr_aliasing	0.840s	112.388us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.862m	163.765ms	50	50	100.00
V2	parity	uart_smoke	34.280s	6.072ms	50	50	100.00
		uart_tx_rx	4.862m	163.765ms	50	50	100.00
V2	parity_error	uart_intr	8.168m	266.551ms	50	50	100.00
		uart_rx_parity_err	5.062m	96.249ms	50	50	100.00
V2	watermark	uart_tx_rx	4.862m	163.765ms	50	50	100.00
		uart_intr	8.168m	266.551ms	50	50	100.00
V2	fifo_full	uart_fifo_full	8.774m	181.105ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	14.077m	141.331ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.001m	121.558ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.168m	266.551ms	50	50	100.00
V2	rx_break_err	uart_intr	8.168m	266.551ms	50	50	100.00
V2	rx_timeout	uart_intr	8.168m	266.551ms	50	50	100.00
V2	perf	uart_perf	19.474m	19.895ms	50	50	100.00
V2	sys_loopback	uart_loopback	19.100s	11.534ms	50	50	100.00
V2	line_loopback	uart_loopback	19.100s	11.534ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	2.734m	77.505ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.871m	75.247ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	22.560s	6.552ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.074m	7.603ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	22.722m	183.721ms	50	50	100.00
V2	stress_all	uart_stress_all	27.962m	259.385ms	50	50	100.00
V2	alert_test	uart_alert_test	0.590s	15.490us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	19.414us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.180s	380.602us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.180s	380.602us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	16.246us	5	5	100.00
		uart_csr_rw	0.640s	16.515us	20	20	100.00
		uart_csr_aliasing	0.840s	112.388us	5	5	100.00
		uart_same_csr_outstanding	0.800s	28.098us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	16.246us	5	5	100.00
		uart_csr_rw	0.640s	16.515us	20	20	100.00
		uart_csr_aliasing	0.840s	112.388us	5	5	100.00
		uart_same_csr_outstanding	0.800s	28.098us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.860s	122.623us	5	5	100.00
		uart_tl_intg_err	1.390s	189.969us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.390s	189.969us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	34.820m	72.515ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1318	1320	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.62

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 36.uart_noise_filter.43500196833192309188055287391389882862718008237243197402505919921967390019627
    Line 266, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

92.uart_stress_all_with_rand_reset.11605609208055274525755624339566097049907168357891856702135553896398351243005
Line 1030, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 186132704016 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 186231504016 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark
  UVM_INFO @ 186292744016 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 420/484
  UVM_INFO @ 186478984016 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 421/484