UART Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	57.980s	5.986ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	50.091us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	16.757us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.560s	228.542us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.700s	74.884us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.380s	27.529us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	16.757us	20	20	100.00
		uart_csr_aliasing	0.700s	74.884us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	10.947m	132.504ms	50	50	100.00
V2	parity	uart_smoke	57.980s	5.986ms	50	50	100.00
		uart_tx_rx	10.947m	132.504ms	50	50	100.00
V2	parity_error	uart_intr	8.885m	307.093ms	49	50	98.00
		uart_rx_parity_err	4.261m	276.154ms	50	50	100.00
V2	watermark	uart_tx_rx	10.947m	132.504ms	50	50	100.00
		uart_intr	8.885m	307.093ms	49	50	98.00
V2	fifo_full	uart_fifo_full	13.064m	315.070ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.761m	98.499ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	6.589m	125.859ms	298	300	99.33
V2	rx_frame_err	uart_intr	8.885m	307.093ms	49	50	98.00
V2	rx_break_err	uart_intr	8.885m	307.093ms	49	50	98.00
V2	rx_timeout	uart_intr	8.885m	307.093ms	49	50	98.00
V2	perf	uart_perf	19.952m	22.719ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.120s	13.257ms	50	50	100.00
V2	line_loopback	uart_loopback	24.120s	13.257ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.625m	54.072ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.445m	61.907ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	27.470s	6.855ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.124m	7.506ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	18.041m	166.108ms	50	50	100.00
V2	stress_all	uart_stress_all	23.534m	454.850ms	50	50	100.00
V2	alert_test	uart_alert_test	0.620s	14.332us	50	50	100.00
V2	intr_test	uart_intr_test	0.600s	29.369us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.450s	420.652us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.450s	420.652us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	50.091us	5	5	100.00
		uart_csr_rw	0.660s	16.757us	20	20	100.00
		uart_csr_aliasing	0.700s	74.884us	5	5	100.00
		uart_same_csr_outstanding	0.810s	39.537us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	50.091us	5	5	100.00
		uart_csr_rw	0.660s	16.757us	20	20	100.00
		uart_csr_aliasing	0.700s	74.884us	5	5	100.00
		uart_same_csr_outstanding	0.810s	39.537us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	0.850s	248.491us	5	5	100.00
		uart_tl_intg_err	1.340s	299.418us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.340s	299.418us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	29.910m	613.702ms	95	100	95.00
V3		TOTAL			95	100	95.00
		TOTAL			1312	1320	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.57

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 4 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

76.uart_stress_all_with_rand_reset.79740251619603362618002397488448509758800104813319467948905568239518923470915
Line 570, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 47166556016 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 47172270416 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 37/833
  UVM_INFO @ 47243724226 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout
  UVM_INFO @ 47342464296 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 38/833

87.uart_stress_all_with_rand_reset.70789883050272955995640982247319282357473650890416505628659426833649188067899
Line 1018, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 159288283229 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 159288283229 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 159366200519 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 159522451769 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_fifo_reset has 2 failures.

295.uart_fifo_reset.90222292487958415600927324100820626481232440603239074369009915937926485753816
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/295.uart_fifo_reset/latest/run.log

  UVM_ERROR @ 24815724353 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 36404529601 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/10
  UVM_INFO @ 40538251633 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/10
  UVM_INFO @ 45356279769 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 5/10
  UVM_INFO @ 45358213073 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 6/10

298.uart_fifo_reset.17031867698593570736916007263970390145458014005028550446163002005149444179615
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/298.uart_fifo_reset/latest/run.log

  UVM_ERROR @   3152708 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 9018752708 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/8
  UVM_INFO @ 13640672708 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/8
  UVM_INFO @ 16700592708 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/8
  UVM_INFO @ 20400192708 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/8

UVM_ERROR (cip_base_vseq.sv:839) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

89.uart_stress_all_with_rand_reset.1576675542359113461767025233385157921664767608335572501945064057920727443950
Line 655, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 143592973484 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 143592984708 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 143592984708 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 6/10
  UVM_INFO @ 143592993892 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1

91.uart_stress_all_with_rand_reset.101560213577599668570164440944116450976674226039681317956277561359509980626778
Line 1313, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 78834096905 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 78834097861 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 78834097861 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 10/10
  UVM_INFO @ 78834108670 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2

UVM_ERROR (uart_intr_vseq.sv:312) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_intr has 1 failures.

23.uart_intr.13462085693261625450500351222220929788822822182508232324317180362018893449699
Line 279, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/23.uart_intr/latest/run.log

  UVM_ERROR @ 67990615869 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 68835215869 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 68839015869 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout
  UVM_ERROR @ 71611415869 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

UVM_ERROR (cip_base_vseq.sv:758) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

36.uart_stress_all_with_rand_reset.54780301209648992780078190685610181353585475391915236361952264105877352787956
Line 774, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 48017447415 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 48017447415 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/5
  UVM_INFO @ 48017549455 ps: (cip_base_vseq.sv:770) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/5