UART Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	32.230s	5.981ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	18.853us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.670s	12.108us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.570s	251.152us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	32.647us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.400s	96.844us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.670s	12.108us	20	20	100.00
		uart_csr_aliasing	0.780s	32.647us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.638m	174.304ms	50	50	100.00
V2	parity	uart_smoke	32.230s	5.981ms	50	50	100.00
		uart_tx_rx	5.638m	174.304ms	50	50	100.00
V2	parity_error	uart_intr	12.304m	469.396ms	50	50	100.00
		uart_rx_parity_err	6.884m	142.359ms	50	50	100.00
V2	watermark	uart_tx_rx	5.638m	174.304ms	50	50	100.00
		uart_intr	12.304m	469.396ms	50	50	100.00
V2	fifo_full	uart_fifo_full	19.878m	181.156ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.356m	185.382ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.521m	253.067ms	300	300	100.00
V2	rx_frame_err	uart_intr	12.304m	469.396ms	50	50	100.00
V2	rx_break_err	uart_intr	12.304m	469.396ms	50	50	100.00
V2	rx_timeout	uart_intr	12.304m	469.396ms	50	50	100.00
V2	perf	uart_perf	23.342m	26.329ms	50	50	100.00
V2	sys_loopback	uart_loopback	23.930s	10.281ms	50	50	100.00
V2	line_loopback	uart_loopback	23.930s	10.281ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	7.162m	114.202ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.042m	78.570ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	59.230s	12.266ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.127m	6.867ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	36.566m	189.156ms	50	50	100.00
V2	stress_all	uart_stress_all	43.379m	204.117ms	50	50	100.00
V2	alert_test	uart_alert_test	0.630s	24.873us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	42.825us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.370s	270.423us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.370s	270.423us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	18.853us	5	5	100.00
		uart_csr_rw	0.670s	12.108us	20	20	100.00
		uart_csr_aliasing	0.780s	32.647us	5	5	100.00
		uart_same_csr_outstanding	0.790s	181.660us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	18.853us	5	5	100.00
		uart_csr_rw	0.670s	12.108us	20	20	100.00
		uart_csr_aliasing	0.780s	32.647us	5	5	100.00
		uart_same_csr_outstanding	0.790s	181.660us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.920s	132.758us	5	5	100.00
		uart_tl_intg_err	1.560s	615.319us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.560s	615.319us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	38.710m	501.181ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1318	1320	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.55

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 36.uart_noise_filter.73162372185063100415566374761107178160967055758548220855854004522028181051581
    Line 267, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:758) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

74.uart_stress_all_with_rand_reset.31376721987589850154954039797265653308178341366850336301540138621662294327728
Line 505, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 23298259084 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 23298259084 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 23298342420 ps: (cip_base_vseq.sv:770) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 3/5