UART Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	13.980s	6.156ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.620s	1.030ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.670s	35.386us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.290s	1.163ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.670s	24.007us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.430s	263.847us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.670s	35.386us	20	20	100.00
		uart_csr_aliasing	0.670s	24.007us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.007m	65.197ms	50	50	100.00
V2	parity	uart_smoke	13.980s	6.156ms	50	50	100.00
		uart_tx_rx	4.007m	65.197ms	50	50	100.00
V2	parity_error	uart_intr	5.803m	248.750ms	49	50	98.00
		uart_rx_parity_err	8.695m	266.886ms	50	50	100.00
V2	watermark	uart_tx_rx	4.007m	65.197ms	50	50	100.00
		uart_intr	5.803m	248.750ms	49	50	98.00
V2	fifo_full	uart_fifo_full	6.258m	298.671ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.995m	116.268ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.029m	85.735ms	300	300	100.00
V2	rx_frame_err	uart_intr	5.803m	248.750ms	49	50	98.00
V2	rx_break_err	uart_intr	5.803m	248.750ms	49	50	98.00
V2	rx_timeout	uart_intr	5.803m	248.750ms	49	50	98.00
V2	perf	uart_perf	27.953m	30.454ms	49	50	98.00
V2	sys_loopback	uart_loopback	19.480s	7.170ms	50	50	100.00
V2	line_loopback	uart_loopback	19.480s	7.170ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	16.500m	125.657ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.548m	59.338ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	33.860s	11.950ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.032m	6.836ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	15.497m	117.687ms	50	50	100.00
V2	stress_all	uart_stress_all	26.123m	240.799ms	50	50	100.00
V2	alert_test	uart_alert_test	0.690s	12.348us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	21.905us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.980s	470.933us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.980s	470.933us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.620s	1.030ms	5	5	100.00
		uart_csr_rw	0.670s	35.386us	20	20	100.00
		uart_csr_aliasing	0.670s	24.007us	5	5	100.00
		uart_same_csr_outstanding	0.790s	30.672us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.620s	1.030ms	5	5	100.00
		uart_csr_rw	0.670s	35.386us	20	20	100.00
		uart_csr_aliasing	0.670s	24.007us	5	5	100.00
		uart_same_csr_outstanding	0.790s	30.672us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.860s	99.278us	5	5	100.00
		uart_tl_intg_err	1.710s	3.663ms	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.710s	3.663ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	29.350m	89.643ms	94	100	94.00
V3		TOTAL			94	100	94.00
		TOTAL			1312	1320	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.57

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 4 failures:

Test uart_stress_all_with_rand_reset has 3 failures.

20.uart_stress_all_with_rand_reset.24749092146723369366745054184139690444840363789403394101568350002613146390713
Line 405, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 44441062267 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 44517062875 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 20/917
  UVM_INFO @ 44610230287 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 21/917
  UVM_INFO @ 45118901023 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 22/917
  UVM_INFO @ 45611238295 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 23/917

58.uart_stress_all_with_rand_reset.419557298817547205870541422526650006523126391618395181573970918338910403403
Line 565, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 127392828071 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 127392828071 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 127473257125 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 127553543321 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 9/882

... and 1 more failures.

Test uart_intr has 1 failures.

36.uart_intr.9726599799172134029086243871521681079546814979994859515138804467062956525354
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_intr/latest/run.log

  UVM_ERROR @    901806 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 1121321806 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 3218471806 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone

UVM_ERROR (cip_base_vseq.sv:839) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

10.uart_stress_all_with_rand_reset.52504083435429404127246128256415471816725903829117631280152464529962290095304
Line 351, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7061953904 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 7061957246 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 7061957246 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 7061957246 ps: (csr_utils_pkg.sv:355) [csr_utils] Early-exit from csr_rd_sub because we are in reset

37.uart_stress_all_with_rand_reset.84018823633185972172627353917531555040345370475223239660167721771914016741134
Line 401, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12520279286 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 12520287021 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 12520287021 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 12520287021 ps: (csr_utils_pkg.sv:355) [csr_utils] Early-exit from csr_rd_sub because we are in reset

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_perf has 1 failures.

11.uart_perf.111129206309578162935771116669511636377239754763230858463925046378537115290780
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_perf/latest/run.log

  UVM_ERROR @ 2138984281 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 2653326546 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/10
  UVM_INFO @ 3484406809 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/10
  UVM_INFO @ 3658172905 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/10
  UVM_INFO @ 6336606097 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 6/10

UVM_ERROR (cip_base_vseq.sv:758) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

19.uart_stress_all_with_rand_reset.37561765139579881335238559132353342135968257864427861323196275853202010405581
Line 391, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40426787301 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 40426787301 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 40426987301 ps: (cip_base_vseq.sv:770) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 3/10