e971cd9798| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 33.270s | 11.108ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | uart_csr_hw_reset | 0.610s | 37.960us | 5 | 5 | 100.00 |
| V1 | csr_rw | uart_csr_rw | 0.670s | 28.821us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | uart_csr_bit_bash | 2.630s | 865.833us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | uart_csr_aliasing | 0.790s | 34.097us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 1.220s | 27.452us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 0.670s | 28.821us | 20 | 20 | 100.00 |
| uart_csr_aliasing | 0.790s | 34.097us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | base_random_seq | uart_tx_rx | 3.388m | 118.132ms | 49 | 50 | 98.00 |
| V2 | parity | uart_smoke | 33.270s | 11.108ms | 50 | 50 | 100.00 |
| uart_tx_rx | 3.388m | 118.132ms | 49 | 50 | 98.00 | ||
| V2 | parity_error | uart_intr | 5.976m | 231.474ms | 49 | 50 | 98.00 |
| uart_rx_parity_err | 6.132m | 260.086ms | 49 | 50 | 98.00 | ||
| V2 | watermark | uart_tx_rx | 3.388m | 118.132ms | 49 | 50 | 98.00 |
| uart_intr | 5.976m | 231.474ms | 49 | 50 | 98.00 | ||
| V2 | fifo_full | uart_fifo_full | 7.350m | 194.413ms | 49 | 50 | 98.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 7.094m | 133.803ms | 49 | 50 | 98.00 |
| V2 | fifo_reset | uart_fifo_reset | 9.659m | 154.948ms | 299 | 300 | 99.67 |
| V2 | rx_frame_err | uart_intr | 5.976m | 231.474ms | 49 | 50 | 98.00 |
| V2 | rx_break_err | uart_intr | 5.976m | 231.474ms | 49 | 50 | 98.00 |
| V2 | rx_timeout | uart_intr | 5.976m | 231.474ms | 49 | 50 | 98.00 |
| V2 | perf | uart_perf | 28.475m | 28.696ms | 49 | 50 | 98.00 |
| V2 | sys_loopback | uart_loopback | 31.540s | 11.318ms | 50 | 50 | 100.00 |
| V2 | line_loopback | uart_loopback | 31.540s | 11.318ms | 50 | 50 | 100.00 |
| V2 | rx_noise_filter | uart_noise_filter | 3.941m | 126.597ms | 49 | 50 | 98.00 |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 1.968m | 76.110ms | 50 | 50 | 100.00 |
| V2 | tx_overide | uart_tx_ovrd | 22.670s | 6.193ms | 50 | 50 | 100.00 |
| V2 | rx_oversample | uart_rx_oversample | 1.067m | 7.144ms | 49 | 50 | 98.00 |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 29.894m | 164.304ms | 48 | 50 | 96.00 |
| V2 | stress_all | uart_stress_all | 41.297m | 558.911ms | 50 | 50 | 100.00 |
| V2 | alert_test | uart_alert_test | 0.650s | 17.068us | 50 | 50 | 100.00 |
| V2 | intr_test | uart_intr_test | 0.620s | 12.738us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 2.630s | 621.098us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | uart_tl_errors | 2.630s | 621.098us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0.610s | 37.960us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.670s | 28.821us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 0.790s | 34.097us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.790s | 28.897us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 0.610s | 37.960us | 5 | 5 | 100.00 |
| uart_csr_rw | 0.670s | 28.821us | 20 | 20 | 100.00 | ||
| uart_csr_aliasing | 0.790s | 34.097us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 0.790s | 28.897us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1079 | 1090 | 98.99 | |||
| V2S | tl_intg_err | uart_sec_cm | 0.910s | 106.235us | 5 | 5 | 100.00 |
| uart_tl_intg_err | 1.430s | 137.228us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 1.430s | 137.228us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | uart_stress_all_with_rand_reset | 47.744m | 147.428ms | 99 | 100 | 99.00 |
| V3 | TOTAL | 99 | 100 | 99.00 | |||
| TOTAL | 1308 | 1320 | 99.09 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 18 | 18 | 8 | 44.44 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.12 | 99.10 | 97.65 | 100.00 | -- | 98.38 | 100.00 | 99.62 |
Exit reason: Error: User command failed Job returned non-zero exit code has 9 failures:
Test uart_long_xfer_wo_dly has 1 failures.
45.uart_long_xfer_wo_dly.40457538659378971754326664422598061813336737531092286571364605055702796251098
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest/run.log
[make]: simulate
cd /workspace/45.uart_long_xfer_wo_dly/latest && /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234087898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1234087898
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jul 21 19:17 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test uart_rx_oversample has 1 failures.
46.uart_rx_oversample.43560915680532506628210508116932493466127193483035652820857500921040426041885
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/46.uart_rx_oversample/latest/run.log
[make]: simulate
cd /workspace/46.uart_rx_oversample/latest && /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029767709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1029767709
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jul 21 19:17 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test uart_intr has 1 failures.
47.uart_intr.100610241906686798790336450438583339178682866374855333399424528126640173205143
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_intr/latest/run.log
[make]: simulate
cd /workspace/47.uart_intr/latest && /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381432471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2381432471
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jul 21 19:17 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test uart_noise_filter has 1 failures.
47.uart_noise_filter.37831880350234974481277219753549810708395003510523781024807576608989631146608
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_noise_filter/latest/run.log
[make]: simulate
cd /workspace/47.uart_noise_filter/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635707504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1635707504
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jul 21 19:17 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test uart_rx_parity_err has 1 failures.
47.uart_rx_parity_err.115159681807318099617117740332360364028817333133574606362070113867243927092335
Log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_rx_parity_err/latest/run.log
[make]: simulate
cd /workspace/47.uart_rx_parity_err/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547053167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3547053167
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jul 21 19:17 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
... and 4 more tests.
UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 2 failures:
Test uart_long_xfer_wo_dly has 1 failures.
13.uart_long_xfer_wo_dly.5917659344540114840146301647983210719892815343618364242260617051164595458450
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest/run.log
UVM_ERROR @ 3352601 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
UVM_ERROR @ 3352601 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
UVM_INFO @ 27420864790 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/10
UVM_INFO @ 63951752601 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/10
UVM_INFO @ 93835872601 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/10
Test uart_stress_all_with_rand_reset has 1 failures.
13.uart_stress_all_with_rand_reset.55361977780947755411491528847170127293345951184548001749271786420047190939463
Line 455, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 79279988479 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
UVM_INFO @ 80108295343 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/871
UVM_INFO @ 80826294625 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/871
UVM_INFO @ 81598524622 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/871
UVM_INFO @ 82126447171 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/871
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
35.uart_fifo_full.13171599509056767513042817656478146506312460001580878843753534781376400284048
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/35.uart_fifo_full/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---