UART Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	21.470s	5.969ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	37.603us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	43.433us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.180s	57.479us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	25.688us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.330s	29.736us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	43.433us	20	20	100.00
		uart_csr_aliasing	0.780s	25.688us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	9.339m	116.539ms	50	50	100.00
V2	parity	uart_smoke	21.470s	5.969ms	50	50	100.00
		uart_tx_rx	9.339m	116.539ms	50	50	100.00
V2	parity_error	uart_intr	3.777m	241.644ms	48	50	96.00
		uart_rx_parity_err	6.606m	230.930ms	49	50	98.00
V2	watermark	uart_tx_rx	9.339m	116.539ms	50	50	100.00
		uart_intr	3.777m	241.644ms	48	50	96.00
V2	fifo_full	uart_fifo_full	21.813m	221.794ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	11.143m	143.349ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.300m	88.179ms	300	300	100.00
V2	rx_frame_err	uart_intr	3.777m	241.644ms	48	50	96.00
V2	rx_break_err	uart_intr	3.777m	241.644ms	48	50	96.00
V2	rx_timeout	uart_intr	3.777m	241.644ms	48	50	96.00
V2	perf	uart_perf	28.462m	29.076ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.620s	10.237ms	50	50	100.00
V2	line_loopback	uart_loopback	24.620s	10.237ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.124m	106.024ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	57.570s	35.616ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	53.430s	12.251ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.064m	6.790ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.837m	157.312ms	50	50	100.00
V2	stress_all	uart_stress_all	29.029m	318.946ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	11.800us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	26.166us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.400s	1.091ms	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.400s	1.091ms	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	37.603us	5	5	100.00
		uart_csr_rw	0.650s	43.433us	20	20	100.00
		uart_csr_aliasing	0.780s	25.688us	5	5	100.00
		uart_same_csr_outstanding	0.750s	94.845us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	37.603us	5	5	100.00
		uart_csr_rw	0.650s	43.433us	20	20	100.00
		uart_csr_aliasing	0.780s	25.688us	5	5	100.00
		uart_same_csr_outstanding	0.750s	94.845us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	0.870s	328.838us	5	5	100.00
		uart_tl_intg_err	1.350s	295.370us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.350s	295.370us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	33.137m	521.035ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.50

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

Test uart_intr has 2 failures.

5.uart_intr.97885450577893599438152801464414781706626730311079447540671107918053554959295
Line 252, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_intr/latest/run.log

  UVM_ERROR @ 157507143 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 241147143 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 398247143 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty

10.uart_intr.92014287825810168729633164128434741588674284211325842261602935435677260578703
Line 292, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_intr/latest/run.log

  UVM_ERROR @ 27802895259 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 27846254913 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr
  UVM_INFO @ 27890398051 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr

Test uart_rx_parity_err has 1 failures.

6.uart_rx_parity_err.12741871784480489530797052866605659486672510345382178714802796156146719634860
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_rx_parity_err/latest/run.log

  UVM_ERROR @   8516786 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 2762180699 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 1/10
  UVM_INFO @ 12142282430 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 2/10
  UVM_INFO @ 14956946282 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 3/10
  UVM_INFO @ 18962831165 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 4/10

UVM_ERROR (cip_base_vseq.sv:758) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

54.uart_stress_all_with_rand_reset.20061192821421277095950975687518384243689735877491801967956506106238844966569
Line 683, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 117246999738 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 117246999738 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 117247272468 ps: (cip_base_vseq.sv:770) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/10

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

86.uart_stress_all_with_rand_reset.17771897079700800574826050429630289242326552887990390300789708924231135086749
Line 374, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40925281807 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 41010576607 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 52/944
  UVM_INFO @ 41653993519 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 53/944
  UVM_ERROR @ 41776170967 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 41981702023 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 54/944