UART Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	44.950s	11.621ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	16.654us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	13.580us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.480s	443.997us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.810s	30.273us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.410s	32.497us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	13.580us	20	20	100.00
		uart_csr_aliasing	0.810s	30.273us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	7.715m	109.418ms	49	50	98.00
V2	parity	uart_smoke	44.950s	11.621ms	50	50	100.00
		uart_tx_rx	7.715m	109.418ms	49	50	98.00
V2	parity_error	uart_intr	20.043m	629.333ms	49	50	98.00
		uart_rx_parity_err	5.403m	103.176ms	50	50	100.00
V2	watermark	uart_tx_rx	7.715m	109.418ms	49	50	98.00
		uart_intr	20.043m	629.333ms	49	50	98.00
V2	fifo_full	uart_fifo_full	10.227m	336.936ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.570m	101.165ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	15.079m	164.886ms	300	300	100.00
V2	rx_frame_err	uart_intr	20.043m	629.333ms	49	50	98.00
V2	rx_break_err	uart_intr	20.043m	629.333ms	49	50	98.00
V2	rx_timeout	uart_intr	20.043m	629.333ms	49	50	98.00
V2	perf	uart_perf	18.677m	19.969ms	50	50	100.00
V2	sys_loopback	uart_loopback	29.040s	13.771ms	50	50	100.00
V2	line_loopback	uart_loopback	29.040s	13.771ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.829m	128.460ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.093m	40.195ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	31.430s	6.935ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.073m	7.296ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	17.826m	90.955ms	50	50	100.00
V2	stress_all	uart_stress_all	32.218m	406.035ms	50	50	100.00
V2	alert_test	uart_alert_test	0.590s	13.358us	50	50	100.00
V2	intr_test	uart_intr_test	0.610s	33.082us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.550s	540.487us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.550s	540.487us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	16.654us	5	5	100.00
		uart_csr_rw	0.650s	13.580us	20	20	100.00
		uart_csr_aliasing	0.810s	30.273us	5	5	100.00
		uart_same_csr_outstanding	0.760s	59.847us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	16.654us	5	5	100.00
		uart_csr_rw	0.650s	13.580us	20	20	100.00
		uart_csr_aliasing	0.810s	30.273us	5	5	100.00
		uart_same_csr_outstanding	0.760s	59.847us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.930s	577.465us	5	5	100.00
		uart_tl_intg_err	1.460s	91.552us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.460s	91.552us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	57.446m	242.308ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.57

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty

has 3 failures:

Test uart_tx_rx has 1 failures.

27.uart_tx_rx.82996233429897942171912022210157488155252613783915224114017634048008985822216
Line 257, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/27.uart_tx_rx/latest/run.log

  UVM_ERROR @ 11504497775 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 12198113875 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 10/14
  UVM_INFO @ 12956155500 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 11/14
  UVM_INFO @ 15707721594 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 12/14
  UVM_INFO @ 15827482555 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 13/14

Test uart_stress_all_with_rand_reset has 1 failures.

39.uart_stress_all_with_rand_reset.109749274756679472862485949400224599457079411363905807982356855067991764366278
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   1583667 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 116931068 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/279
  UVM_INFO @ 182135493 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/279
  UVM_INFO @ 237917492 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/279
  UVM_INFO @ 251729239 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/7

Test uart_intr has 1 failures.

48.uart_intr.9971301379699213718103673030071799541782782415202814831770598465403476958500
Line 269, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/48.uart_intr/latest/run.log

  UVM_ERROR @ 6453977380 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 6547180716 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow
  UVM_INFO @ 12190482508 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark