UART Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	36.830s	11.034ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.630s	26.741us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	12.167us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.500s	720.581us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.790s	49.664us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.100s	85.540us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	12.167us	20	20	100.00
		uart_csr_aliasing	0.790s	49.664us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.054m	81.347ms	50	50	100.00
V2	parity	uart_smoke	36.830s	11.034ms	50	50	100.00
		uart_tx_rx	3.054m	81.347ms	50	50	100.00
V2	parity_error	uart_intr	7.279m	302.793ms	50	50	100.00
		uart_rx_parity_err	13.021m	106.734ms	50	50	100.00
V2	watermark	uart_tx_rx	3.054m	81.347ms	50	50	100.00
		uart_intr	7.279m	302.793ms	50	50	100.00
V2	fifo_full	uart_fifo_full	13.173m	251.086ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.839m	118.816ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.176m	330.674ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.279m	302.793ms	50	50	100.00
V2	rx_break_err	uart_intr	7.279m	302.793ms	50	50	100.00
V2	rx_timeout	uart_intr	7.279m	302.793ms	50	50	100.00
V2	perf	uart_perf	21.629m	27.551ms	50	50	100.00
V2	sys_loopback	uart_loopback	22.480s	5.496ms	50	50	100.00
V2	line_loopback	uart_loopback	22.480s	5.496ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.249m	106.585ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.854m	72.793ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	47.190s	12.877ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.014m	6.770ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.977m	166.990ms	50	50	100.00
V2	stress_all	uart_stress_all	24.710m	268.437ms	50	50	100.00
V2	alert_test	uart_alert_test	0.600s	52.257us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	22.240us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.550s	193.511us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.550s	193.511us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.630s	26.741us	5	5	100.00
		uart_csr_rw	0.660s	12.167us	20	20	100.00
		uart_csr_aliasing	0.790s	49.664us	5	5	100.00
		uart_same_csr_outstanding	0.780s	63.401us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.630s	26.741us	5	5	100.00
		uart_csr_rw	0.660s	12.167us	20	20	100.00
		uart_csr_aliasing	0.790s	49.664us	5	5	100.00
		uart_same_csr_outstanding	0.780s	63.401us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.880s	238.994us	5	5	100.00
		uart_tl_intg_err	1.460s	95.591us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.460s	95.591us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	42.485m	168.529ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1318	1320	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.57

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:758) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

21.uart_stress_all_with_rand_reset.49582687904894094560397949351831810661111451029332227944251507187321749868292
Line 339, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16569108647 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 16569108647 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 16569456471 ps: (cip_base_vseq.sv:770) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 2/10

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

56.uart_stress_all_with_rand_reset.21918659064818583761943020853348560499474879580444907967071916949945185292097
Line 360, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14419666674 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 14505375693 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 2/2
  UVM_INFO @ 14528584212 ps: (uart_stress_all_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_stress_all_vseq] starting stress_all sub-sequence uart_tx_rx_vseq
  UVM_INFO @ 14628501678 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 51/256
  UVM_INFO @ 14932420776 ps: (cip_base_vseq__tl_errors.svh:201) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 52/256