UART Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	23.240s	11.067ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.630s	42.358us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	18.510us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.320s	661.581us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	57.471us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.390s	71.550us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	18.510us	20	20	100.00
		uart_csr_aliasing	0.820s	57.471us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.804m	82.404ms	50	50	100.00
V2	parity	uart_smoke	23.240s	11.067ms	50	50	100.00
		uart_tx_rx	5.804m	82.404ms	50	50	100.00
V2	parity_error	uart_intr	6.047m	247.400ms	50	50	100.00
		uart_rx_parity_err	6.389m	220.504ms	50	50	100.00
V2	watermark	uart_tx_rx	5.804m	82.404ms	50	50	100.00
		uart_intr	6.047m	247.400ms	50	50	100.00
V2	fifo_full	uart_fifo_full	10.536m	141.149ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	12.116m	103.778ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.139m	108.042ms	300	300	100.00
V2	rx_frame_err	uart_intr	6.047m	247.400ms	50	50	100.00
V2	rx_break_err	uart_intr	6.047m	247.400ms	50	50	100.00
V2	rx_timeout	uart_intr	6.047m	247.400ms	50	50	100.00
V2	perf	uart_perf	31.357m	35.100ms	50	50	100.00
V2	sys_loopback	uart_loopback	30.530s	9.731ms	50	50	100.00
V2	line_loopback	uart_loopback	30.530s	9.731ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	6.250m	97.749ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.462m	65.329ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	54.040s	12.588ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.062m	7.201ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	17.491m	149.190ms	50	50	100.00
V2	stress_all	uart_stress_all	26.510m	351.004ms	49	50	98.00
V2	alert_test	uart_alert_test	0.610s	14.099us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	184.831us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.280s	46.419us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.280s	46.419us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.630s	42.358us	5	5	100.00
		uart_csr_rw	0.680s	18.510us	20	20	100.00
		uart_csr_aliasing	0.820s	57.471us	5	5	100.00
		uart_same_csr_outstanding	0.770s	16.392us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.630s	42.358us	5	5	100.00
		uart_csr_rw	0.680s	18.510us	20	20	100.00
		uart_csr_aliasing	0.820s	57.471us	5	5	100.00
		uart_same_csr_outstanding	0.770s	16.392us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	1.130s	1.243ms	5	5	100.00
		uart_tl_intg_err	1.440s	169.719us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.440s	169.719us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	38.034m	167.277ms	96	100	96.00
V3		TOTAL			96	100	96.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.59

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:755) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 3 failures:

Test uart_stress_all_with_rand_reset has 3 failures.

11.uart_stress_all_with_rand_reset.16873693865941943628489095047437665441679765668889666939909657708558984560507
Line 356, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9209884133 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9209884133 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 9209884133 ps: (csr_utils_pkg.sv:355) [csr_utils] Early-exit from csr_rd_sub because we are in reset
  UVM_INFO @ 9209884133 ps: (csr_utils_pkg.sv:355) [csr_utils] Early-exit from csr_rd_sub because we are in reset

13.uart_stress_all_with_rand_reset.100136581624946427957685860004045345778987923944494019397707898312728167525374
Line 886, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 75853854052 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 75853854052 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 75853954052 ps: (cip_base_vseq.sv:767) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/10

... and 1 more failures.

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty

has 2 failures:

Test uart_stress_all has 1 failures.

22.uart_stress_all.115556816256241107206884341900653937529315807756639192615981781537497669363391
Line 322, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/22.uart_stress_all/latest/run.log

  UVM_ERROR @ 38968087252 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 39045877252 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 39514687252 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark

Test uart_stress_all_with_rand_reset has 1 failures.

33.uart_stress_all_with_rand_reset.15186646020405023422703975300270511253005392134107584574375597249090454944334
Line 742, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 489044472773 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 489136806291 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow
  UVM_INFO @ 489635807289 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 71/379
  UVM_INFO @ 490297641946 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 72/379