UART Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	27.350s	6.244ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.590s	14.652us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	40.271us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.280s	118.018us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.800s	149.871us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.180s	95.867us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	40.271us	20	20	100.00
		uart_csr_aliasing	0.800s	149.871us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	7.430m	92.996ms	49	50	98.00
V2	parity	uart_smoke	27.350s	6.244ms	50	50	100.00
		uart_tx_rx	7.430m	92.996ms	49	50	98.00
V2	parity_error	uart_intr	8.799m	355.221ms	47	50	94.00
		uart_rx_parity_err	7.378m	290.190ms	50	50	100.00
V2	watermark	uart_tx_rx	7.430m	92.996ms	49	50	98.00
		uart_intr	8.799m	355.221ms	47	50	94.00
V2	fifo_full	uart_fifo_full	5.441m	167.014ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	2.956m	129.176ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.133m	186.891ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.799m	355.221ms	47	50	94.00
V2	rx_break_err	uart_intr	8.799m	355.221ms	47	50	94.00
V2	rx_timeout	uart_intr	8.799m	355.221ms	47	50	94.00
V2	perf	uart_perf	22.523m	23.116ms	50	50	100.00
V2	sys_loopback	uart_loopback	27.750s	8.319ms	50	50	100.00
V2	line_loopback	uart_loopback	27.750s	8.319ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.216m	270.201ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.005m	39.529ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	26.680s	7.100ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.133m	7.380ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	24.864m	143.535ms	50	50	100.00
V2	stress_all	uart_stress_all	33.899m	68.112ms	49	50	98.00
V2	alert_test	uart_alert_test	0.620s	171.029us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	40.431us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.270s	132.021us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.270s	132.021us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.590s	14.652us	5	5	100.00
		uart_csr_rw	0.640s	40.271us	20	20	100.00
		uart_csr_aliasing	0.800s	149.871us	5	5	100.00
		uart_same_csr_outstanding	0.810s	32.314us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.590s	14.652us	5	5	100.00
		uart_csr_rw	0.640s	40.271us	20	20	100.00
		uart_csr_aliasing	0.800s	149.871us	5	5	100.00
		uart_same_csr_outstanding	0.810s	32.314us	20	20	100.00
V2		TOTAL			1085	1090	99.54
V2S	tl_intg_err	uart_sec_cm	0.950s	67.308us	5	5	100.00
		uart_tl_intg_err	1.380s	90.685us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.380s	90.685us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	46.962m	115.140ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1313	1320	99.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.57

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 6 failures:

Test uart_stress_all has 1 failures.

16.uart_stress_all.20032080173972634751111460433069379434312744000877943011810884562826009111763
Line 309, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/16.uart_stress_all/latest/run.log

  UVM_ERROR @ 165560797990 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 165645353461 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 166508019265 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone

Test uart_tx_rx has 1 failures.

19.uart_tx_rx.45580840170905841508598354687314833890057661579370149701322777691637973313640
Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_tx_rx/latest/run.log

  UVM_ERROR @ 98757898945 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 101368943953 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 16/16
  UVM_INFO @ 140252286027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test uart_intr has 3 failures.

30.uart_intr.76581284240812257931118548468083374360083488280578954550705385748475174279238
Line 264, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/30.uart_intr/latest/run.log

  UVM_ERROR @ 9457823716 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 9543494830 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 9715458092 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2
  UVM_INFO @ 9715542300 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

46.uart_intr.42054565679580181057089767414279058901711240291379381226934428034682200152520
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/46.uart_intr/latest/run.log

  UVM_ERROR @ 319566853 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 397680299 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 554012451 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark

... and 1 more failures.

Test uart_stress_all_with_rand_reset has 1 failures.

37.uart_stress_all_with_rand_reset.45477867243738559588106240209540467085932482103555463681287667404081466086641
Line 905, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 166415679284 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 166492439284 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 166555319284 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 50/50
  UVM_INFO @ 166648679284 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

UVM_ERROR (cip_base_vseq.sv:755) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

51.uart_stress_all_with_rand_reset.62821650823485783319903950609259131822459624616364665845681665842420369877784
Line 1138, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 57529829366 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 57529829366 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 7/10
  UVM_INFO @ 57529889972 ps: (cip_base_vseq.sv:767) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 7/10