UART Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	39.320s	5.907ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.940s	1.032ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	22.197us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.560s	1.634ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	102.796us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.250s	28.448us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	22.197us	20	20	100.00
		uart_csr_aliasing	0.780s	102.796us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.706m	136.245ms	50	50	100.00
V2	parity	uart_smoke	39.320s	5.907ms	50	50	100.00
		uart_tx_rx	4.706m	136.245ms	50	50	100.00
V2	parity_error	uart_intr	5.212m	193.903ms	49	50	98.00
		uart_rx_parity_err	4.154m	189.355ms	50	50	100.00
V2	watermark	uart_tx_rx	4.706m	136.245ms	50	50	100.00
		uart_intr	5.212m	193.903ms	49	50	98.00
V2	fifo_full	uart_fifo_full	6.936m	234.839ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.545m	175.491ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	17.268m	193.570ms	300	300	100.00
V2	rx_frame_err	uart_intr	5.212m	193.903ms	49	50	98.00
V2	rx_break_err	uart_intr	5.212m	193.903ms	49	50	98.00
V2	rx_timeout	uart_intr	5.212m	193.903ms	49	50	98.00
V2	perf	uart_perf	23.132m	28.458ms	50	50	100.00
V2	sys_loopback	uart_loopback	18.590s	8.845ms	50	50	100.00
V2	line_loopback	uart_loopback	18.590s	8.845ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.353m	67.119ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.187m	47.219ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	42.190s	12.256ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.094m	6.979ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	26.041m	156.136ms	50	50	100.00
V2	stress_all	uart_stress_all	24.167m	350.167ms	50	50	100.00
V2	alert_test	uart_alert_test	0.690s	24.474us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	33.405us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.450s	353.592us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.450s	353.592us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.940s	1.032ms	5	5	100.00
		uart_csr_rw	0.680s	22.197us	20	20	100.00
		uart_csr_aliasing	0.780s	102.796us	5	5	100.00
		uart_same_csr_outstanding	0.830s	35.192us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.940s	1.032ms	5	5	100.00
		uart_csr_rw	0.680s	22.197us	20	20	100.00
		uart_csr_aliasing	0.780s	102.796us	5	5	100.00
		uart_same_csr_outstanding	0.830s	35.192us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.910s	234.809us	5	5	100.00
		uart_tl_intg_err	1.410s	511.889us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.410s	511.889us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	31.774m	83.059ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.48

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty

has 4 failures:

Test uart_intr has 1 failures.

13.uart_intr.57684423922764697075775170711850425250616483347732397298297995462365451514397
Line 260, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_intr/latest/run.log

  UVM_ERROR @ 15948556926 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 16034229710 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 17249607742 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout

Test uart_stress_all_with_rand_reset has 3 failures.

36.uart_stress_all_with_rand_reset.82436843485376717116043722020818393757119577177738845979668567961509772688817
Line 386, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10277603616 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 10331173489 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 9/330
  UVM_INFO @ 10353979227 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 10376368295 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 10/330

68.uart_stress_all_with_rand_reset.23540981179925733826554504089237247114225164102367903502530095641315104256137
Line 581, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 62751814231 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 62796314587 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 62883148615 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 44.uart_noise_filter.3698725661074190356440773697976242624739904567426774578358087791054546993930
    Line 262, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/44.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```