| T410 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.3247117758 |
|
|
Oct 09 05:33:32 AM UTC 24 |
Oct 09 05:33:40 AM UTC 24 |
937002582 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_smoke.2335164753 |
|
|
Oct 09 05:33:11 AM UTC 24 |
Oct 09 05:33:41 AM UTC 24 |
5369694775 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_loopback.2079253600 |
|
|
Oct 09 05:33:33 AM UTC 24 |
Oct 09 05:33:41 AM UTC 24 |
6019430337 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_alert_test.1298363933 |
|
|
Oct 09 05:33:40 AM UTC 24 |
Oct 09 05:33:42 AM UTC 24 |
35571757 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_smoke.1561206644 |
|
|
Oct 09 05:33:41 AM UTC 24 |
Oct 09 05:33:43 AM UTC 24 |
279429464 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.390559106 |
|
|
Oct 09 05:33:04 AM UTC 24 |
Oct 09 05:33:44 AM UTC 24 |
3278307412 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.2285504599 |
|
|
Oct 09 05:32:44 AM UTC 24 |
Oct 09 05:33:45 AM UTC 24 |
76524023118 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_noise_filter.3653230850 |
|
|
Oct 09 05:32:25 AM UTC 24 |
Oct 09 05:33:45 AM UTC 24 |
40984682085 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.1444811024 |
|
|
Oct 09 05:29:14 AM UTC 24 |
Oct 09 05:33:47 AM UTC 24 |
172605534088 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_noise_filter.2617147460 |
|
|
Oct 09 05:30:26 AM UTC 24 |
Oct 09 05:33:48 AM UTC 24 |
108366904488 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.1984708302 |
|
|
Oct 09 05:33:48 AM UTC 24 |
Oct 09 05:33:52 AM UTC 24 |
1724890370 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.4203028243 |
|
|
Oct 09 05:33:53 AM UTC 24 |
Oct 09 05:33:58 AM UTC 24 |
499699142 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_tx_rx.1630780459 |
|
|
Oct 09 05:32:42 AM UTC 24 |
Oct 09 05:34:04 AM UTC 24 |
75669530878 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.2045035085 |
|
|
Oct 09 05:32:08 AM UTC 24 |
Oct 09 05:34:08 AM UTC 24 |
15480604575 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_perf.955796429 |
|
|
Oct 09 05:29:34 AM UTC 24 |
Oct 09 05:34:09 AM UTC 24 |
19594905452 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_intr.900869515 |
|
|
Oct 09 05:33:46 AM UTC 24 |
Oct 09 05:34:11 AM UTC 24 |
24268327469 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_fifo_full.946168429 |
|
|
Oct 09 05:33:43 AM UTC 24 |
Oct 09 05:34:20 AM UTC 24 |
48935213346 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_alert_test.217064500 |
|
|
Oct 09 05:34:19 AM UTC 24 |
Oct 09 05:34:22 AM UTC 24 |
14084200 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_smoke.3053190461 |
|
|
Oct 09 05:34:21 AM UTC 24 |
Oct 09 05:34:24 AM UTC 24 |
629021838 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_fifo_full.1504743297 |
|
|
Oct 09 05:33:14 AM UTC 24 |
Oct 09 05:34:29 AM UTC 24 |
39050409504 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_fifo_reset.3472090600 |
|
|
Oct 09 05:33:44 AM UTC 24 |
Oct 09 05:34:33 AM UTC 24 |
73661445015 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_perf.1078519711 |
|
|
Oct 09 05:31:36 AM UTC 24 |
Oct 09 05:34:35 AM UTC 24 |
4780578563 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_rx_oversample.3248877777 |
|
|
Oct 09 05:34:30 AM UTC 24 |
Oct 09 05:34:38 AM UTC 24 |
2441396581 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_fifo_full.2706630818 |
|
|
Oct 09 05:30:48 AM UTC 24 |
Oct 09 05:34:40 AM UTC 24 |
114042600110 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.11433960 |
|
|
Oct 09 05:34:39 AM UTC 24 |
Oct 09 05:34:48 AM UTC 24 |
2444264320 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.3189476853 |
|
|
Oct 09 05:34:10 AM UTC 24 |
Oct 09 05:34:51 AM UTC 24 |
3491234198 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.2216577280 |
|
|
Oct 09 05:34:48 AM UTC 24 |
Oct 09 05:34:51 AM UTC 24 |
844736068 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_perf.1991407692 |
|
|
Oct 09 05:28:23 AM UTC 24 |
Oct 09 05:34:52 AM UTC 24 |
5495284780 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_noise_filter.3319068506 |
|
|
Oct 09 05:33:27 AM UTC 24 |
Oct 09 05:34:53 AM UTC 24 |
252234790628 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_fifo_reset.3526526598 |
|
|
Oct 09 05:32:20 AM UTC 24 |
Oct 09 05:34:54 AM UTC 24 |
82037182826 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_intr.2331956519 |
|
|
Oct 09 05:34:34 AM UTC 24 |
Oct 09 05:34:57 AM UTC 24 |
20836189542 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_alert_test.1703450631 |
|
|
Oct 09 05:34:59 AM UTC 24 |
Oct 09 05:35:00 AM UTC 24 |
185908940 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_tx_rx.1068051038 |
|
|
Oct 09 05:34:22 AM UTC 24 |
Oct 09 05:35:03 AM UTC 24 |
16243725077 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_smoke.459964169 |
|
|
Oct 09 05:35:02 AM UTC 24 |
Oct 09 05:35:04 AM UTC 24 |
102173715 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_loopback.1031347885 |
|
|
Oct 09 05:34:52 AM UTC 24 |
Oct 09 05:35:05 AM UTC 24 |
3128138889 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_noise_filter.913294104 |
|
|
Oct 09 05:34:36 AM UTC 24 |
Oct 09 05:35:05 AM UTC 24 |
14403035879 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_stress_all.362708632 |
|
|
Oct 09 05:34:12 AM UTC 24 |
Oct 09 05:35:10 AM UTC 24 |
392039288952 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_noise_filter.2444139150 |
|
|
Oct 09 05:28:10 AM UTC 24 |
Oct 09 05:35:11 AM UTC 24 |
160875517972 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1105363031 |
|
|
Oct 09 05:33:45 AM UTC 24 |
Oct 09 05:35:11 AM UTC 24 |
7032260468 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.630752316 |
|
|
Oct 09 05:32:51 AM UTC 24 |
Oct 09 05:35:12 AM UTC 24 |
171510992165 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_stress_all.1647609186 |
|
|
Oct 09 05:26:16 AM UTC 24 |
Oct 09 05:35:12 AM UTC 24 |
396300485133 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_fifo_reset.1831271422 |
|
|
Oct 09 05:33:17 AM UTC 24 |
Oct 09 05:35:13 AM UTC 24 |
36157149539 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.39826785 |
|
|
Oct 09 05:34:41 AM UTC 24 |
Oct 09 05:35:15 AM UTC 24 |
30805462503 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_rx_oversample.627155460 |
|
|
Oct 09 05:35:11 AM UTC 24 |
Oct 09 05:35:16 AM UTC 24 |
2629988552 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.2376038187 |
|
|
Oct 09 05:33:38 AM UTC 24 |
Oct 09 05:35:18 AM UTC 24 |
13244395418 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_perf.3419128423 |
|
|
Oct 09 05:33:00 AM UTC 24 |
Oct 09 05:35:18 AM UTC 24 |
9336765693 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.3634531239 |
|
|
Oct 09 05:35:12 AM UTC 24 |
Oct 09 05:35:21 AM UTC 24 |
32454336406 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_tx_rx.3723858649 |
|
|
Oct 09 05:35:04 AM UTC 24 |
Oct 09 05:35:21 AM UTC 24 |
46726166300 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_fifo_full.1610454746 |
|
|
Oct 09 05:34:22 AM UTC 24 |
Oct 09 05:35:24 AM UTC 24 |
68904649105 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_alert_test.847744400 |
|
|
Oct 09 05:35:22 AM UTC 24 |
Oct 09 05:35:24 AM UTC 24 |
19390895 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_smoke.2456407277 |
|
|
Oct 09 05:35:24 AM UTC 24 |
Oct 09 05:35:27 AM UTC 24 |
291955681 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.4018892420 |
|
|
Oct 09 05:32:06 AM UTC 24 |
Oct 09 05:35:31 AM UTC 24 |
156385353171 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.1339140253 |
|
|
Oct 09 05:27:56 AM UTC 24 |
Oct 09 05:35:31 AM UTC 24 |
110322543395 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_stress_all.3237622991 |
|
|
Oct 09 05:29:38 AM UTC 24 |
Oct 09 05:35:34 AM UTC 24 |
346495017939 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_loopback.1041361581 |
|
|
Oct 09 05:35:16 AM UTC 24 |
Oct 09 05:35:35 AM UTC 24 |
7656964820 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_stress_all.3946869602 |
|
|
Oct 09 05:28:26 AM UTC 24 |
Oct 09 05:35:39 AM UTC 24 |
45673928299 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.1913083341 |
|
|
Oct 09 05:35:14 AM UTC 24 |
Oct 09 05:35:45 AM UTC 24 |
7057025882 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_stress_all.1079000547 |
|
|
Oct 09 05:31:19 AM UTC 24 |
Oct 09 05:35:46 AM UTC 24 |
237616429189 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_fifo_reset.206227221 |
|
|
Oct 09 05:35:32 AM UTC 24 |
Oct 09 05:35:51 AM UTC 24 |
23405352378 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_fifo_full.272949709 |
|
|
Oct 09 05:35:05 AM UTC 24 |
Oct 09 05:35:54 AM UTC 24 |
28356415640 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_stress_all.4241745075 |
|
|
Oct 09 05:26:56 AM UTC 24 |
Oct 09 05:35:58 AM UTC 24 |
592669515829 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.4144385315 |
|
|
Oct 09 05:35:52 AM UTC 24 |
Oct 09 05:35:58 AM UTC 24 |
4346639468 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_noise_filter.3124392131 |
|
|
Oct 09 05:33:46 AM UTC 24 |
Oct 09 05:35:58 AM UTC 24 |
91001520617 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.1225020991 |
|
|
Oct 09 05:35:19 AM UTC 24 |
Oct 09 05:36:01 AM UTC 24 |
6219444583 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.1387455955 |
|
|
Oct 09 05:35:32 AM UTC 24 |
Oct 09 05:36:03 AM UTC 24 |
19342308438 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_intr.2205180175 |
|
|
Oct 09 05:35:12 AM UTC 24 |
Oct 09 05:36:04 AM UTC 24 |
22330066754 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.3272816430 |
|
|
Oct 09 05:34:23 AM UTC 24 |
Oct 09 05:36:05 AM UTC 24 |
62182320497 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.3716922564 |
|
|
Oct 09 05:35:46 AM UTC 24 |
Oct 09 05:36:06 AM UTC 24 |
4883668035 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_stress_all.543754756 |
|
|
Oct 09 05:29:21 AM UTC 24 |
Oct 09 05:36:06 AM UTC 24 |
361662575404 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_alert_test.1094054589 |
|
|
Oct 09 05:36:05 AM UTC 24 |
Oct 09 05:36:07 AM UTC 24 |
42616871 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_loopback.2016977439 |
|
|
Oct 09 05:35:55 AM UTC 24 |
Oct 09 05:36:08 AM UTC 24 |
6828576192 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_smoke.3799247694 |
|
|
Oct 09 05:36:05 AM UTC 24 |
Oct 09 05:36:09 AM UTC 24 |
483748795 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.2721121226 |
|
|
Oct 09 05:35:59 AM UTC 24 |
Oct 09 05:36:10 AM UTC 24 |
1412455944 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_perf.3145835159 |
|
|
Oct 09 05:33:33 AM UTC 24 |
Oct 09 05:36:13 AM UTC 24 |
11483408193 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_noise_filter.3722696441 |
|
|
Oct 09 05:35:40 AM UTC 24 |
Oct 09 05:36:15 AM UTC 24 |
81565739707 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_perf.4249523089 |
|
|
Oct 09 05:30:11 AM UTC 24 |
Oct 09 05:36:17 AM UTC 24 |
15069344242 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.2029947712 |
|
|
Oct 09 05:33:14 AM UTC 24 |
Oct 09 05:36:18 AM UTC 24 |
131951493933 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.2260951186 |
|
|
Oct 09 05:36:13 AM UTC 24 |
Oct 09 05:36:20 AM UTC 24 |
3848614321 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_loopback.3139003632 |
|
|
Oct 09 05:36:19 AM UTC 24 |
Oct 09 05:36:21 AM UTC 24 |
228622925 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.2724956506 |
|
|
Oct 09 05:35:47 AM UTC 24 |
Oct 09 05:36:22 AM UTC 24 |
70954510756 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.3341243791 |
|
|
Oct 09 05:36:19 AM UTC 24 |
Oct 09 05:36:25 AM UTC 24 |
1451530041 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.1722506208 |
|
|
Oct 09 05:30:28 AM UTC 24 |
Oct 09 05:36:29 AM UTC 24 |
154162593308 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.3836392832 |
|
|
Oct 09 05:26:31 AM UTC 24 |
Oct 09 05:36:32 AM UTC 24 |
328359341835 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_alert_test.1035858507 |
|
|
Oct 09 05:36:30 AM UTC 24 |
Oct 09 05:36:32 AM UTC 24 |
13621647 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.2451454974 |
|
|
Oct 09 05:33:43 AM UTC 24 |
Oct 09 05:36:35 AM UTC 24 |
167713240182 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_smoke.476526392 |
|
|
Oct 09 05:36:32 AM UTC 24 |
Oct 09 05:36:37 AM UTC 24 |
745729828 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_rx_oversample.3686344224 |
|
|
Oct 09 05:35:35 AM UTC 24 |
Oct 09 05:36:39 AM UTC 24 |
5059755875 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.1323166966 |
|
|
Oct 09 05:33:00 AM UTC 24 |
Oct 09 05:36:41 AM UTC 24 |
75568393589 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.2565140615 |
|
|
Oct 09 05:36:17 AM UTC 24 |
Oct 09 05:36:43 AM UTC 24 |
8774283566 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.2164350306 |
|
|
Oct 09 05:35:14 AM UTC 24 |
Oct 09 05:36:44 AM UTC 24 |
158558865227 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.2805416395 |
|
|
Oct 09 05:33:32 AM UTC 24 |
Oct 09 05:36:45 AM UTC 24 |
113456458765 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.1336696956 |
|
|
Oct 09 05:36:23 AM UTC 24 |
Oct 09 05:36:48 AM UTC 24 |
2786412120 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.1497044759 |
|
|
Oct 09 05:36:45 AM UTC 24 |
Oct 09 05:36:49 AM UTC 24 |
1939702711 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_stress_all.3678311667 |
|
|
Oct 09 05:33:39 AM UTC 24 |
Oct 09 05:36:50 AM UTC 24 |
194408250540 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_intr.3380686067 |
|
|
Oct 09 05:36:44 AM UTC 24 |
Oct 09 05:36:51 AM UTC 24 |
2656746166 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_loopback.2680974291 |
|
|
Oct 09 05:36:49 AM UTC 24 |
Oct 09 05:36:52 AM UTC 24 |
152651416 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.204539023 |
|
|
Oct 09 05:36:48 AM UTC 24 |
Oct 09 05:36:53 AM UTC 24 |
2041079893 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_fifo_reset.2990632045 |
|
|
Oct 09 05:35:06 AM UTC 24 |
Oct 09 05:36:57 AM UTC 24 |
108700895525 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_alert_test.2223637089 |
|
|
Oct 09 05:36:58 AM UTC 24 |
Oct 09 05:37:00 AM UTC 24 |
33043383 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.31232015 |
|
|
Oct 09 05:36:46 AM UTC 24 |
Oct 09 05:37:02 AM UTC 24 |
6002261046 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_smoke.3977806146 |
|
|
Oct 09 05:37:01 AM UTC 24 |
Oct 09 05:37:05 AM UTC 24 |
957669887 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_fifo_reset.2175236274 |
|
|
Oct 09 05:36:07 AM UTC 24 |
Oct 09 05:37:06 AM UTC 24 |
112594657152 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_tx_rx.1592062552 |
|
|
Oct 09 05:36:33 AM UTC 24 |
Oct 09 05:37:11 AM UTC 24 |
16564156911 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_rx_oversample.3324055640 |
|
|
Oct 09 05:36:08 AM UTC 24 |
Oct 09 05:37:13 AM UTC 24 |
7135358578 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.2754773469 |
|
|
Oct 09 05:30:11 AM UTC 24 |
Oct 09 05:37:15 AM UTC 24 |
48500767922 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_tx_rx.2531217872 |
|
|
Oct 09 05:35:25 AM UTC 24 |
Oct 09 05:37:17 AM UTC 24 |
51025928610 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_rx_oversample.1544529741 |
|
|
Oct 09 05:36:43 AM UTC 24 |
Oct 09 05:37:17 AM UTC 24 |
4029345867 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_fifo_reset.1744006664 |
|
|
Oct 09 05:29:27 AM UTC 24 |
Oct 09 05:37:18 AM UTC 24 |
350220776214 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_fifo_full.475966624 |
|
|
Oct 09 05:36:07 AM UTC 24 |
Oct 09 05:37:20 AM UTC 24 |
96546613517 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_fifo_reset.3720467933 |
|
|
Oct 09 05:34:25 AM UTC 24 |
Oct 09 05:37:22 AM UTC 24 |
212691472032 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_tx_rx.3594204215 |
|
|
Oct 09 05:37:03 AM UTC 24 |
Oct 09 05:37:23 AM UTC 24 |
11387290511 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.757772782 |
|
|
Oct 09 05:27:15 AM UTC 24 |
Oct 09 05:37:23 AM UTC 24 |
165172306192 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.4206142696 |
|
|
Oct 09 05:37:19 AM UTC 24 |
Oct 09 05:37:24 AM UTC 24 |
38381158107 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.721897624 |
|
|
Oct 09 05:37:21 AM UTC 24 |
Oct 09 05:37:24 AM UTC 24 |
1116281810 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_fifo_full.3402815851 |
|
|
Oct 09 05:36:36 AM UTC 24 |
Oct 09 05:37:29 AM UTC 24 |
45099624884 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_perf.1897149001 |
|
|
Oct 09 05:35:17 AM UTC 24 |
Oct 09 05:37:31 AM UTC 24 |
18910905266 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_rx_oversample.3978916107 |
|
|
Oct 09 05:37:13 AM UTC 24 |
Oct 09 05:37:31 AM UTC 24 |
7137514269 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_alert_test.3686021527 |
|
|
Oct 09 05:37:29 AM UTC 24 |
Oct 09 05:37:31 AM UTC 24 |
12451230 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_loopback.1450200910 |
|
|
Oct 09 05:37:23 AM UTC 24 |
Oct 09 05:37:33 AM UTC 24 |
3366375412 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_noise_filter.1830599088 |
|
|
Oct 09 05:36:10 AM UTC 24 |
Oct 09 05:37:34 AM UTC 24 |
51002172360 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_smoke.806616272 |
|
|
Oct 09 05:37:31 AM UTC 24 |
Oct 09 05:37:34 AM UTC 24 |
474820669 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_stress_all.702544190 |
|
|
Oct 09 05:32:37 AM UTC 24 |
Oct 09 05:37:36 AM UTC 24 |
137292049138 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_intr.191992672 |
|
|
Oct 09 05:37:15 AM UTC 24 |
Oct 09 05:37:40 AM UTC 24 |
24107852259 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_rx_oversample.1008200409 |
|
|
Oct 09 05:37:35 AM UTC 24 |
Oct 09 05:37:45 AM UTC 24 |
2268373493 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_fifo_full.1619969228 |
|
|
Oct 09 05:37:06 AM UTC 24 |
Oct 09 05:37:46 AM UTC 24 |
91508167067 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.2913271674 |
|
|
Oct 09 05:34:53 AM UTC 24 |
Oct 09 05:37:47 AM UTC 24 |
39437677509 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.3746863093 |
|
|
Oct 09 05:31:11 AM UTC 24 |
Oct 09 05:37:47 AM UTC 24 |
63466375188 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.2982041787 |
|
|
Oct 09 05:33:48 AM UTC 24 |
Oct 09 05:37:48 AM UTC 24 |
134834504640 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.758781533 |
|
|
Oct 09 05:37:46 AM UTC 24 |
Oct 09 05:37:50 AM UTC 24 |
2297494257 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.3889329422 |
|
|
Oct 09 05:37:25 AM UTC 24 |
Oct 09 05:37:52 AM UTC 24 |
3161140333 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_loopback.2764091144 |
|
|
Oct 09 05:37:48 AM UTC 24 |
Oct 09 05:37:53 AM UTC 24 |
2687846556 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.3737361636 |
|
|
Oct 09 05:28:24 AM UTC 24 |
Oct 09 05:37:54 AM UTC 24 |
96541103560 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_alert_test.590370604 |
|
|
Oct 09 05:37:55 AM UTC 24 |
Oct 09 05:37:57 AM UTC 24 |
41913031 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_intr.1857339974 |
|
|
Oct 09 05:33:21 AM UTC 24 |
Oct 09 05:37:58 AM UTC 24 |
304609812038 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_smoke.4239699749 |
|
|
Oct 09 05:37:58 AM UTC 24 |
Oct 09 05:38:01 AM UTC 24 |
247598753 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_stress_all.2629813483 |
|
|
Oct 09 05:36:25 AM UTC 24 |
Oct 09 05:38:03 AM UTC 24 |
220592367869 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_noise_filter.2202824881 |
|
|
Oct 09 05:36:44 AM UTC 24 |
Oct 09 05:38:07 AM UTC 24 |
150157714402 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.4114331431 |
|
|
Oct 09 05:37:48 AM UTC 24 |
Oct 09 05:38:08 AM UTC 24 |
10386161728 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.2650933161 |
|
|
Oct 09 05:35:06 AM UTC 24 |
Oct 09 05:38:11 AM UTC 24 |
90015766344 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_stress_all.2629881317 |
|
|
Oct 09 05:31:43 AM UTC 24 |
Oct 09 05:38:14 AM UTC 24 |
47188977063 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.3913023623 |
|
|
Oct 09 05:36:53 AM UTC 24 |
Oct 09 05:38:15 AM UTC 24 |
10415681675 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_rx_oversample.4205440025 |
|
|
Oct 09 05:38:08 AM UTC 24 |
Oct 09 05:38:16 AM UTC 24 |
2614933894 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_fifo_reset.2072141629 |
|
|
Oct 09 05:36:40 AM UTC 24 |
Oct 09 05:38:19 AM UTC 24 |
88701940782 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_noise_filter.422000614 |
|
|
Oct 09 05:35:12 AM UTC 24 |
Oct 09 05:38:22 AM UTC 24 |
120910066990 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.3319576575 |
|
|
Oct 09 05:38:17 AM UTC 24 |
Oct 09 05:38:22 AM UTC 24 |
3473723443 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.3980505685 |
|
|
Oct 09 05:38:21 AM UTC 24 |
Oct 09 05:38:24 AM UTC 24 |
433226241 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.4117665822 |
|
|
Oct 09 05:37:34 AM UTC 24 |
Oct 09 05:38:25 AM UTC 24 |
28893533185 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_tx_rx.4168810410 |
|
|
Oct 09 05:36:06 AM UTC 24 |
Oct 09 05:38:25 AM UTC 24 |
58418635333 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_fifo_full.3274854809 |
|
|
Oct 09 05:35:28 AM UTC 24 |
Oct 09 05:38:26 AM UTC 24 |
128723530560 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_alert_test.3299777759 |
|
|
Oct 09 05:38:28 AM UTC 24 |
Oct 09 05:38:29 AM UTC 24 |
42560356 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_loopback.453045345 |
|
|
Oct 09 05:38:23 AM UTC 24 |
Oct 09 05:38:30 AM UTC 24 |
5447910943 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_perf.2345118508 |
|
|
Oct 09 05:28:48 AM UTC 24 |
Oct 09 05:38:31 AM UTC 24 |
17664779519 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_noise_filter.1468994997 |
|
|
Oct 09 05:37:40 AM UTC 24 |
Oct 09 05:38:33 AM UTC 24 |
18339622676 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_intr.3085167524 |
|
|
Oct 09 05:37:36 AM UTC 24 |
Oct 09 05:38:35 AM UTC 24 |
32310129984 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_smoke.2497990797 |
|
|
Oct 09 05:38:31 AM UTC 24 |
Oct 09 05:38:39 AM UTC 24 |
841244799 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_rx_oversample.1793393363 |
|
|
Oct 09 05:38:35 AM UTC 24 |
Oct 09 05:38:41 AM UTC 24 |
1975044425 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_fifo_reset.2744796828 |
|
|
Oct 09 05:37:12 AM UTC 24 |
Oct 09 05:38:43 AM UTC 24 |
232487772792 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.1626712758 |
|
|
Oct 09 05:37:20 AM UTC 24 |
Oct 09 05:38:44 AM UTC 24 |
38039722153 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.3788029337 |
|
|
Oct 09 05:38:04 AM UTC 24 |
Oct 09 05:38:48 AM UTC 24 |
110906749327 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.3910236392 |
|
|
Oct 09 05:37:07 AM UTC 24 |
Oct 09 05:38:49 AM UTC 24 |
189953169292 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.4176132277 |
|
|
Oct 09 05:38:44 AM UTC 24 |
Oct 09 05:38:56 AM UTC 24 |
2032651769 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_loopback.2552048609 |
|
|
Oct 09 05:38:50 AM UTC 24 |
Oct 09 05:38:56 AM UTC 24 |
779152529 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_noise_filter.40504858 |
|
|
Oct 09 05:38:15 AM UTC 24 |
Oct 09 05:38:56 AM UTC 24 |
74766782245 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_tx_rx.2299298243 |
|
|
Oct 09 05:37:31 AM UTC 24 |
Oct 09 05:39:01 AM UTC 24 |
43728717418 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.266258792 |
|
|
Oct 09 05:37:53 AM UTC 24 |
Oct 09 05:39:03 AM UTC 24 |
30972100531 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_alert_test.3168470871 |
|
|
Oct 09 05:39:02 AM UTC 24 |
Oct 09 05:39:04 AM UTC 24 |
11054465 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_fifo_reset.1186822386 |
|
|
Oct 09 05:37:35 AM UTC 24 |
Oct 09 05:39:07 AM UTC 24 |
156269458782 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_perf.2452643496 |
|
|
Oct 09 05:31:05 AM UTC 24 |
Oct 09 05:39:07 AM UTC 24 |
9993463362 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_fifo_reset.2515392565 |
|
|
Oct 09 05:38:07 AM UTC 24 |
Oct 09 05:39:07 AM UTC 24 |
42801494463 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_smoke.224639018 |
|
|
Oct 09 05:39:04 AM UTC 24 |
Oct 09 05:39:08 AM UTC 24 |
648599101 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.602932416 |
|
|
Oct 09 05:38:49 AM UTC 24 |
Oct 09 05:39:11 AM UTC 24 |
6541093529 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_fifo_reset.1649489887 |
|
|
Oct 09 05:38:34 AM UTC 24 |
Oct 09 05:39:11 AM UTC 24 |
33025352682 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.2942992020 |
|
|
Oct 09 05:38:27 AM UTC 24 |
Oct 09 05:39:17 AM UTC 24 |
10470213843 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_tx_rx.1878073853 |
|
|
Oct 09 05:37:59 AM UTC 24 |
Oct 09 05:39:17 AM UTC 24 |
87274854074 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.1559676493 |
|
|
Oct 09 05:32:33 AM UTC 24 |
Oct 09 05:39:19 AM UTC 24 |
172039915810 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.6483417 |
|
|
Oct 09 05:39:17 AM UTC 24 |
Oct 09 05:39:22 AM UTC 24 |
5427055203 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.1162695109 |
|
|
Oct 09 05:38:32 AM UTC 24 |
Oct 09 05:39:23 AM UTC 24 |
45776287885 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_loopback.2572466417 |
|
|
Oct 09 05:39:24 AM UTC 24 |
Oct 09 05:39:27 AM UTC 24 |
843252909 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.4140580059 |
|
|
Oct 09 05:39:20 AM UTC 24 |
Oct 09 05:39:29 AM UTC 24 |
1158463072 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.3974130597 |
|
|
Oct 09 05:37:47 AM UTC 24 |
Oct 09 05:39:30 AM UTC 24 |
30590043263 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_noise_filter.1439373703 |
|
|
Oct 09 05:38:42 AM UTC 24 |
Oct 09 05:39:31 AM UTC 24 |
24299579340 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_rx_oversample.3338978693 |
|
|
Oct 09 05:39:09 AM UTC 24 |
Oct 09 05:39:33 AM UTC 24 |
2605674728 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_alert_test.180134408 |
|
|
Oct 09 05:39:31 AM UTC 24 |
Oct 09 05:39:34 AM UTC 24 |
47408138 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_smoke.1568203769 |
|
|
Oct 09 05:39:32 AM UTC 24 |
Oct 09 05:39:35 AM UTC 24 |
121607739 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.3303508396 |
|
|
Oct 09 05:38:45 AM UTC 24 |
Oct 09 05:39:36 AM UTC 24 |
28589190118 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_fifo_full.2354733748 |
|
|
Oct 09 05:37:33 AM UTC 24 |
Oct 09 05:39:38 AM UTC 24 |
113240419631 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.4192246201 |
|
|
Oct 09 05:38:57 AM UTC 24 |
Oct 09 05:39:43 AM UTC 24 |
3395344714 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_intr.1007658514 |
|
|
Oct 09 05:39:12 AM UTC 24 |
Oct 09 05:39:53 AM UTC 24 |
26900657579 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.3901842958 |
|
|
Oct 09 05:39:18 AM UTC 24 |
Oct 09 05:39:54 AM UTC 24 |
42218168120 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.2122019721 |
|
|
Oct 09 05:38:17 AM UTC 24 |
Oct 09 05:39:58 AM UTC 24 |
106311868683 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_fifo_reset.2689818563 |
|
|
Oct 09 05:39:08 AM UTC 24 |
Oct 09 05:40:02 AM UTC 24 |
48275710536 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.1358694963 |
|
|
Oct 09 05:34:52 AM UTC 24 |
Oct 09 05:40:02 AM UTC 24 |
189668510601 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.2094105747 |
|
|
Oct 09 05:36:38 AM UTC 24 |
Oct 09 05:40:05 AM UTC 24 |
109318178183 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_stress_all.4261832949 |
|
|
Oct 09 05:32:08 AM UTC 24 |
Oct 09 05:40:06 AM UTC 24 |
146412185383 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.2302899204 |
|
|
Oct 09 05:40:03 AM UTC 24 |
Oct 09 05:40:07 AM UTC 24 |
847226386 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.1261386812 |
|
|
Oct 09 05:39:28 AM UTC 24 |
Oct 09 05:40:07 AM UTC 24 |
6308399316 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_fifo_full.1745804678 |
|
|
Oct 09 05:39:08 AM UTC 24 |
Oct 09 05:40:08 AM UTC 24 |
16656531441 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_noise_filter.3282599573 |
|
|
Oct 09 05:39:12 AM UTC 24 |
Oct 09 05:40:10 AM UTC 24 |
65192586507 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_alert_test.2216595929 |
|
|
Oct 09 05:40:09 AM UTC 24 |
Oct 09 05:40:11 AM UTC 24 |
22345446 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.824929606 |
|
|
Oct 09 05:39:37 AM UTC 24 |
Oct 09 05:40:12 AM UTC 24 |
40487199225 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_tx_rx.632989147 |
|
|
Oct 09 05:39:06 AM UTC 24 |
Oct 09 05:40:19 AM UTC 24 |
108409241294 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.2196398122 |
|
|
Oct 09 05:39:55 AM UTC 24 |
Oct 09 05:40:19 AM UTC 24 |
40951416405 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_stress_all.3082036126 |
|
|
Oct 09 05:34:56 AM UTC 24 |
Oct 09 05:40:23 AM UTC 24 |
133955993256 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_loopback.208179239 |
|
|
Oct 09 05:40:03 AM UTC 24 |
Oct 09 05:40:25 AM UTC 24 |
6976155917 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_stress_all.883805713 |
|
|
Oct 09 05:40:08 AM UTC 24 |
Oct 09 05:40:27 AM UTC 24 |
7112742864 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_intr.1837985268 |
|
|
Oct 09 05:35:36 AM UTC 24 |
Oct 09 05:40:32 AM UTC 24 |
154003630847 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_smoke.2430569399 |
|
|
Oct 09 05:40:11 AM UTC 24 |
Oct 09 05:40:35 AM UTC 24 |
6016387148 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.1048685011 |
|
|
Oct 09 05:40:34 AM UTC 24 |
Oct 09 05:40:39 AM UTC 24 |
2962994407 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.725104374 |
|
|
Oct 09 05:40:40 AM UTC 24 |
Oct 09 05:40:45 AM UTC 24 |
2172326043 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_intr.1091755790 |
|
|
Oct 09 05:39:44 AM UTC 24 |
Oct 09 05:40:53 AM UTC 24 |
19011196344 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_tx_rx.1083702079 |
|
|
Oct 09 05:39:33 AM UTC 24 |
Oct 09 05:41:02 AM UTC 24 |
80227971209 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.3562257897 |
|
|
Oct 09 05:29:29 AM UTC 24 |
Oct 09 05:41:02 AM UTC 24 |
124006381789 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_fifo_reset.1774224943 |
|
|
Oct 09 05:40:20 AM UTC 24 |
Oct 09 05:41:03 AM UTC 24 |
58444656070 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_loopback.2390359287 |
|
|
Oct 09 05:40:46 AM UTC 24 |
Oct 09 05:41:10 AM UTC 24 |
5753504005 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_intr.3018436242 |
|
|
Oct 09 05:38:39 AM UTC 24 |
Oct 09 05:41:11 AM UTC 24 |
72349973098 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_alert_test.1907460629 |
|
|
Oct 09 05:41:11 AM UTC 24 |
Oct 09 05:41:12 AM UTC 24 |
88227190 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.1899931565 |
|
|
Oct 09 05:31:38 AM UTC 24 |
Oct 09 05:41:13 AM UTC 24 |
107460116704 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_tx_rx.947851264 |
|
|
Oct 09 05:38:31 AM UTC 24 |
Oct 09 05:41:14 AM UTC 24 |
68779477801 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.2368781882 |
|
|
Oct 09 05:39:58 AM UTC 24 |
Oct 09 05:41:16 AM UTC 24 |
37837897648 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.408615455 |
|
|
Oct 09 05:38:25 AM UTC 24 |
Oct 09 05:41:19 AM UTC 24 |
101745853071 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_perf.3989149733 |
|
|
Oct 09 05:36:51 AM UTC 24 |
Oct 09 05:41:21 AM UTC 24 |
4690840171 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_perf.3605647344 |
|
|
Oct 09 05:37:48 AM UTC 24 |
Oct 09 05:41:24 AM UTC 24 |
16096635879 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_intr.2125707120 |
|
|
Oct 09 05:40:26 AM UTC 24 |
Oct 09 05:41:27 AM UTC 24 |
33382370212 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_fifo_full.1135362357 |
|
|
Oct 09 05:38:32 AM UTC 24 |
Oct 09 05:41:28 AM UTC 24 |
72442697524 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_rx_oversample.1818252189 |
|
|
Oct 09 05:39:39 AM UTC 24 |
Oct 09 05:41:28 AM UTC 24 |
7934241430 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_rx_oversample.2184582257 |
|
|
Oct 09 05:41:20 AM UTC 24 |
Oct 09 05:41:28 AM UTC 24 |
6421137460 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_smoke.420031751 |
|
|
Oct 09 05:41:12 AM UTC 24 |
Oct 09 05:41:30 AM UTC 24 |
5471475863 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.2674010694 |
|
|
Oct 09 05:40:08 AM UTC 24 |
Oct 09 05:41:33 AM UTC 24 |
24914884799 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.3879213306 |
|
|
Oct 09 05:41:29 AM UTC 24 |
Oct 09 05:41:34 AM UTC 24 |
894969089 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.3044869421 |
|
|
Oct 09 05:41:28 AM UTC 24 |
Oct 09 05:41:35 AM UTC 24 |
2987076574 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_rx_oversample.1471495757 |
|
|
Oct 09 05:40:23 AM UTC 24 |
Oct 09 05:41:36 AM UTC 24 |
6939499457 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.3550321701 |
|
|
Oct 09 05:36:07 AM UTC 24 |
Oct 09 05:41:38 AM UTC 24 |
179410805314 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_alert_test.413868067 |
|
|
Oct 09 05:41:37 AM UTC 24 |
Oct 09 05:41:39 AM UTC 24 |
11485679 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.2939854751 |
|
|
Oct 09 05:41:03 AM UTC 24 |
Oct 09 05:41:40 AM UTC 24 |
9956208988 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_loopback.2508157696 |
|
|
Oct 09 05:41:30 AM UTC 24 |
Oct 09 05:41:40 AM UTC 24 |
15654719334 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_fifo_full.2447591691 |
|
|
Oct 09 05:40:13 AM UTC 24 |
Oct 09 05:41:41 AM UTC 24 |
34026578234 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_smoke.2091737622 |
|
|
Oct 09 05:41:38 AM UTC 24 |
Oct 09 05:41:46 AM UTC 24 |
925644359 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.1910375015 |
|
|
Oct 09 05:41:15 AM UTC 24 |
Oct 09 05:41:54 AM UTC 24 |
87516751723 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_tx_rx.3212306521 |
|
|
Oct 09 05:41:14 AM UTC 24 |
Oct 09 05:41:56 AM UTC 24 |
17157439221 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_noise_filter.4045888743 |
|
|
Oct 09 05:39:54 AM UTC 24 |
Oct 09 05:42:01 AM UTC 24 |
104099399357 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_stress_all.2655848348 |
|
|
Oct 09 05:35:22 AM UTC 24 |
Oct 09 05:42:02 AM UTC 24 |
141937722394 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_noise_filter.2431771820 |
|
|
Oct 09 05:40:28 AM UTC 24 |
Oct 09 05:42:02 AM UTC 24 |
125519142685 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.3425237489 |
|
|
Oct 09 05:42:03 AM UTC 24 |
Oct 09 05:42:08 AM UTC 24 |
1976433006 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_loopback.3184540369 |
|
|
Oct 09 05:42:09 AM UTC 24 |
Oct 09 05:42:12 AM UTC 24 |
2729463151 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_intr.4137091517 |
|
|
Oct 09 05:41:21 AM UTC 24 |
Oct 09 05:42:14 AM UTC 24 |
35784951691 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.734492742 |
|
|
Oct 09 05:33:38 AM UTC 24 |
Oct 09 05:42:19 AM UTC 24 |
215879249449 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_perf.2885109514 |
|
|
Oct 09 05:38:57 AM UTC 24 |
Oct 09 05:42:21 AM UTC 24 |
14194782661 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_tx_rx.3631729316 |
|
|
Oct 09 05:41:40 AM UTC 24 |
Oct 09 05:42:27 AM UTC 24 |
48180610129 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_alert_test.393372470 |
|
|
Oct 09 05:42:28 AM UTC 24 |
Oct 09 05:42:30 AM UTC 24 |
19180241 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_rx_oversample.3714610983 |
|
|
Oct 09 05:41:47 AM UTC 24 |
Oct 09 05:42:33 AM UTC 24 |
4106622042 ps |