| T264 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/188.uart_fifo_reset.3427540614 |
|
|
Oct 09 05:58:15 AM UTC 24 |
Oct 09 05:59:01 AM UTC 24 |
37385999506 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/209.uart_fifo_reset.2534398707 |
|
|
Oct 09 05:58:47 AM UTC 24 |
Oct 09 05:59:08 AM UTC 24 |
46906816838 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/113.uart_fifo_reset.1380326216 |
|
|
Oct 09 05:56:11 AM UTC 24 |
Oct 09 05:59:09 AM UTC 24 |
165683123045 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_stress_all.3840623716 |
|
|
Oct 09 05:50:31 AM UTC 24 |
Oct 09 05:59:10 AM UTC 24 |
135137921859 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3646519498 |
|
|
Oct 09 05:58:33 AM UTC 24 |
Oct 09 05:59:11 AM UTC 24 |
167137251592 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/87.uart_fifo_reset.4056377249 |
|
|
Oct 09 05:55:09 AM UTC 24 |
Oct 09 05:59:12 AM UTC 24 |
135717035527 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/201.uart_fifo_reset.3788667437 |
|
|
Oct 09 05:58:31 AM UTC 24 |
Oct 09 05:59:15 AM UTC 24 |
19313658380 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/203.uart_fifo_reset.1399898884 |
|
|
Oct 09 05:58:34 AM UTC 24 |
Oct 09 05:59:19 AM UTC 24 |
22983886488 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/218.uart_fifo_reset.3534291045 |
|
|
Oct 09 05:59:02 AM UTC 24 |
Oct 09 05:59:20 AM UTC 24 |
46548467651 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/196.uart_fifo_reset.1798365082 |
|
|
Oct 09 05:58:23 AM UTC 24 |
Oct 09 05:59:23 AM UTC 24 |
38100317391 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/181.uart_fifo_reset.627331021 |
|
|
Oct 09 05:58:06 AM UTC 24 |
Oct 09 05:59:26 AM UTC 24 |
466938414355 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/174.uart_fifo_reset.3683377505 |
|
|
Oct 09 05:57:59 AM UTC 24 |
Oct 09 05:59:37 AM UTC 24 |
92529253441 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/224.uart_fifo_reset.3473202527 |
|
|
Oct 09 05:59:16 AM UTC 24 |
Oct 09 05:59:41 AM UTC 24 |
54217456280 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/208.uart_fifo_reset.495071214 |
|
|
Oct 09 05:58:45 AM UTC 24 |
Oct 09 05:59:45 AM UTC 24 |
252066051190 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/179.uart_fifo_reset.308530582 |
|
|
Oct 09 05:58:05 AM UTC 24 |
Oct 09 05:59:45 AM UTC 24 |
65664564299 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/195.uart_fifo_reset.3198083699 |
|
|
Oct 09 05:58:20 AM UTC 24 |
Oct 09 05:59:47 AM UTC 24 |
377266186637 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_perf.4127208189 |
|
|
Oct 09 05:43:04 AM UTC 24 |
Oct 09 05:59:49 AM UTC 24 |
13940363878 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/219.uart_fifo_reset.3582389570 |
|
|
Oct 09 05:59:09 AM UTC 24 |
Oct 09 05:59:49 AM UTC 24 |
59365599333 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_stress_all.2216197128 |
|
|
Oct 09 05:45:32 AM UTC 24 |
Oct 09 05:59:53 AM UTC 24 |
270420857704 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/177.uart_fifo_reset.2471137325 |
|
|
Oct 09 05:58:04 AM UTC 24 |
Oct 09 05:59:53 AM UTC 24 |
181432965856 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/227.uart_fifo_reset.1562087903 |
|
|
Oct 09 05:59:24 AM UTC 24 |
Oct 09 05:59:53 AM UTC 24 |
31132874614 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/194.uart_fifo_reset.4170555948 |
|
|
Oct 09 05:58:18 AM UTC 24 |
Oct 09 05:59:58 AM UTC 24 |
104133992367 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/211.uart_fifo_reset.2850098131 |
|
|
Oct 09 05:58:50 AM UTC 24 |
Oct 09 06:00:00 AM UTC 24 |
281455877289 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.385227929 |
|
|
Oct 09 05:48:08 AM UTC 24 |
Oct 09 06:00:01 AM UTC 24 |
132281920992 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/228.uart_fifo_reset.19423945 |
|
|
Oct 09 05:59:28 AM UTC 24 |
Oct 09 06:00:02 AM UTC 24 |
59311705304 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/175.uart_fifo_reset.683699729 |
|
|
Oct 09 05:58:01 AM UTC 24 |
Oct 09 06:00:04 AM UTC 24 |
286747982694 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/88.uart_fifo_reset.98996848 |
|
|
Oct 09 05:55:12 AM UTC 24 |
Oct 09 06:00:05 AM UTC 24 |
152503682396 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/171.uart_fifo_reset.880269646 |
|
|
Oct 09 05:57:44 AM UTC 24 |
Oct 09 06:00:05 AM UTC 24 |
82475981008 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2047513566 |
|
|
Oct 09 05:58:34 AM UTC 24 |
Oct 09 06:00:08 AM UTC 24 |
52226772515 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/212.uart_fifo_reset.2127554268 |
|
|
Oct 09 05:58:54 AM UTC 24 |
Oct 09 06:00:08 AM UTC 24 |
155486128387 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/166.uart_fifo_reset.784528395 |
|
|
Oct 09 05:57:39 AM UTC 24 |
Oct 09 06:00:08 AM UTC 24 |
151722543460 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/157.uart_fifo_reset.2040472512 |
|
|
Oct 09 05:57:27 AM UTC 24 |
Oct 09 06:00:11 AM UTC 24 |
284375088439 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/192.uart_fifo_reset.1190096493 |
|
|
Oct 09 05:58:17 AM UTC 24 |
Oct 09 06:00:15 AM UTC 24 |
49117226950 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/213.uart_fifo_reset.4123871857 |
|
|
Oct 09 05:58:57 AM UTC 24 |
Oct 09 06:00:15 AM UTC 24 |
21191096090 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/210.uart_fifo_reset.913017341 |
|
|
Oct 09 05:58:48 AM UTC 24 |
Oct 09 06:00:20 AM UTC 24 |
185403316180 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/236.uart_fifo_reset.256271553 |
|
|
Oct 09 05:59:54 AM UTC 24 |
Oct 09 06:00:22 AM UTC 24 |
21675200712 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/217.uart_fifo_reset.1280525734 |
|
|
Oct 09 05:59:01 AM UTC 24 |
Oct 09 06:00:24 AM UTC 24 |
154085959757 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/150.uart_fifo_reset.1262618929 |
|
|
Oct 09 05:57:22 AM UTC 24 |
Oct 09 06:00:24 AM UTC 24 |
120022914183 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/230.uart_fifo_reset.829731516 |
|
|
Oct 09 05:59:42 AM UTC 24 |
Oct 09 06:00:24 AM UTC 24 |
23952249734 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/231.uart_fifo_reset.4163940467 |
|
|
Oct 09 05:59:46 AM UTC 24 |
Oct 09 06:00:24 AM UTC 24 |
84434442224 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3639776614 |
|
|
Oct 09 06:00:10 AM UTC 24 |
Oct 09 06:00:26 AM UTC 24 |
7854397599 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/226.uart_fifo_reset.501367968 |
|
|
Oct 09 05:59:21 AM UTC 24 |
Oct 09 06:00:27 AM UTC 24 |
19611934378 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1722009099 |
|
|
Oct 09 05:58:59 AM UTC 24 |
Oct 09 06:00:31 AM UTC 24 |
101954367306 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/198.uart_fifo_reset.267794537 |
|
|
Oct 09 05:58:27 AM UTC 24 |
Oct 09 06:00:32 AM UTC 24 |
80893626323 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/221.uart_fifo_reset.1524157829 |
|
|
Oct 09 05:59:11 AM UTC 24 |
Oct 09 06:00:35 AM UTC 24 |
44477089005 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/242.uart_fifo_reset.285369409 |
|
|
Oct 09 06:00:03 AM UTC 24 |
Oct 09 06:00:39 AM UTC 24 |
12581959075 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/253.uart_fifo_reset.3108009142 |
|
|
Oct 09 06:00:22 AM UTC 24 |
Oct 09 06:00:41 AM UTC 24 |
10319366665 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/240.uart_fifo_reset.54147809 |
|
|
Oct 09 06:00:01 AM UTC 24 |
Oct 09 06:00:44 AM UTC 24 |
16696087548 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/225.uart_fifo_reset.2338197310 |
|
|
Oct 09 05:59:19 AM UTC 24 |
Oct 09 06:00:45 AM UTC 24 |
28059341725 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2979676450 |
|
|
Oct 09 05:59:47 AM UTC 24 |
Oct 09 06:00:47 AM UTC 24 |
17637885659 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/220.uart_fifo_reset.3771838766 |
|
|
Oct 09 05:59:10 AM UTC 24 |
Oct 09 06:00:49 AM UTC 24 |
137951343069 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/254.uart_fifo_reset.52525046 |
|
|
Oct 09 06:00:24 AM UTC 24 |
Oct 09 06:00:51 AM UTC 24 |
31611661535 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/252.uart_fifo_reset.1005133037 |
|
|
Oct 09 06:00:21 AM UTC 24 |
Oct 09 06:00:52 AM UTC 24 |
106228332951 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/245.uart_fifo_reset.2522188518 |
|
|
Oct 09 06:00:09 AM UTC 24 |
Oct 09 06:00:55 AM UTC 24 |
18834738037 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/215.uart_fifo_reset.3084052583 |
|
|
Oct 09 05:58:59 AM UTC 24 |
Oct 09 06:00:55 AM UTC 24 |
105279606158 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/176.uart_fifo_reset.3001780909 |
|
|
Oct 09 05:58:03 AM UTC 24 |
Oct 09 06:00:58 AM UTC 24 |
73815006566 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1096365564 |
|
|
Oct 09 06:00:16 AM UTC 24 |
Oct 09 06:00:59 AM UTC 24 |
37251239067 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/238.uart_fifo_reset.1769093591 |
|
|
Oct 09 05:59:55 AM UTC 24 |
Oct 09 06:01:00 AM UTC 24 |
19790546625 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_perf.4217252740 |
|
|
Oct 09 05:47:16 AM UTC 24 |
Oct 09 06:01:01 AM UTC 24 |
16236181451 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1108644095 |
|
|
Oct 09 06:00:00 AM UTC 24 |
Oct 09 06:01:04 AM UTC 24 |
62138030879 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_stress_all.3245910377 |
|
|
Oct 09 05:36:54 AM UTC 24 |
Oct 09 06:01:06 AM UTC 24 |
122817901751 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.3569466663 |
|
|
Oct 09 05:47:19 AM UTC 24 |
Oct 09 06:01:11 AM UTC 24 |
96015278111 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/241.uart_fifo_reset.2558758414 |
|
|
Oct 09 06:00:02 AM UTC 24 |
Oct 09 06:01:12 AM UTC 24 |
295957803599 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/260.uart_fifo_reset.1565143065 |
|
|
Oct 09 06:00:32 AM UTC 24 |
Oct 09 06:01:14 AM UTC 24 |
90794297637 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/246.uart_fifo_reset.3612623618 |
|
|
Oct 09 06:00:09 AM UTC 24 |
Oct 09 06:01:17 AM UTC 24 |
206133799090 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/267.uart_fifo_reset.2154537614 |
|
|
Oct 09 06:00:47 AM UTC 24 |
Oct 09 06:01:18 AM UTC 24 |
53259332698 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1345302051 |
|
|
Oct 09 06:00:56 AM UTC 24 |
Oct 09 06:01:18 AM UTC 24 |
19254595484 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/261.uart_fifo_reset.1341107706 |
|
|
Oct 09 06:00:34 AM UTC 24 |
Oct 09 06:01:20 AM UTC 24 |
13043818596 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/268.uart_fifo_reset.2949911138 |
|
|
Oct 09 06:00:50 AM UTC 24 |
Oct 09 06:01:21 AM UTC 24 |
29310899430 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/153.uart_fifo_reset.1354716311 |
|
|
Oct 09 05:57:24 AM UTC 24 |
Oct 09 06:01:23 AM UTC 24 |
87433321864 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/237.uart_fifo_reset.2837363954 |
|
|
Oct 09 05:59:54 AM UTC 24 |
Oct 09 06:01:23 AM UTC 24 |
152880805448 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/263.uart_fifo_reset.81055482 |
|
|
Oct 09 06:00:40 AM UTC 24 |
Oct 09 06:01:28 AM UTC 24 |
17440422331 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/269.uart_fifo_reset.2320486780 |
|
|
Oct 09 06:00:52 AM UTC 24 |
Oct 09 06:01:28 AM UTC 24 |
10094533723 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/276.uart_fifo_reset.2653878945 |
|
|
Oct 09 06:01:01 AM UTC 24 |
Oct 09 06:01:30 AM UTC 24 |
10877780999 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/265.uart_fifo_reset.554061785 |
|
|
Oct 09 06:00:45 AM UTC 24 |
Oct 09 06:01:33 AM UTC 24 |
74095703009 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/244.uart_fifo_reset.3742676303 |
|
|
Oct 09 06:00:09 AM UTC 24 |
Oct 09 06:01:34 AM UTC 24 |
132992488254 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/145.uart_fifo_reset.2779604367 |
|
|
Oct 09 05:56:59 AM UTC 24 |
Oct 09 06:01:39 AM UTC 24 |
65548311072 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/256.uart_fifo_reset.758145141 |
|
|
Oct 09 06:00:25 AM UTC 24 |
Oct 09 06:01:42 AM UTC 24 |
25436235060 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/287.uart_fifo_reset.1856612798 |
|
|
Oct 09 06:01:25 AM UTC 24 |
Oct 09 06:01:44 AM UTC 24 |
26826257144 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/229.uart_fifo_reset.1406489736 |
|
|
Oct 09 05:59:38 AM UTC 24 |
Oct 09 06:01:44 AM UTC 24 |
104108585492 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/200.uart_fifo_reset.2228307819 |
|
|
Oct 09 05:58:29 AM UTC 24 |
Oct 09 06:04:05 AM UTC 24 |
164397615819 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/275.uart_fifo_reset.2775233049 |
|
|
Oct 09 06:01:01 AM UTC 24 |
Oct 09 06:01:45 AM UTC 24 |
59465878875 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/278.uart_fifo_reset.2474785957 |
|
|
Oct 09 06:01:08 AM UTC 24 |
Oct 09 06:01:48 AM UTC 24 |
68103064242 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1338300694 |
|
|
Oct 09 06:00:09 AM UTC 24 |
Oct 09 06:01:49 AM UTC 24 |
35792295955 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/279.uart_fifo_reset.1602832890 |
|
|
Oct 09 06:01:12 AM UTC 24 |
Oct 09 06:01:49 AM UTC 24 |
39906513087 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/158.uart_fifo_reset.1745732010 |
|
|
Oct 09 05:57:29 AM UTC 24 |
Oct 09 06:01:51 AM UTC 24 |
79573629012 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3242446882 |
|
|
Oct 09 06:00:46 AM UTC 24 |
Oct 09 06:01:51 AM UTC 24 |
31998440476 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/294.uart_fifo_reset.274297502 |
|
|
Oct 09 06:01:40 AM UTC 24 |
Oct 09 06:01:59 AM UTC 24 |
8573515531 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/295.uart_fifo_reset.4096493347 |
|
|
Oct 09 06:01:43 AM UTC 24 |
Oct 09 06:02:00 AM UTC 24 |
31290663629 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/272.uart_fifo_reset.3721860120 |
|
|
Oct 09 06:00:56 AM UTC 24 |
Oct 09 06:02:02 AM UTC 24 |
34012440501 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/249.uart_fifo_reset.3149846345 |
|
|
Oct 09 06:00:12 AM UTC 24 |
Oct 09 06:02:02 AM UTC 24 |
87168583844 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_stress_all.3821607891 |
|
|
Oct 09 05:37:25 AM UTC 24 |
Oct 09 06:02:03 AM UTC 24 |
605932797111 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/264.uart_fifo_reset.69605924 |
|
|
Oct 09 06:00:42 AM UTC 24 |
Oct 09 06:02:05 AM UTC 24 |
69874889837 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/291.uart_fifo_reset.3203376782 |
|
|
Oct 09 06:01:31 AM UTC 24 |
Oct 09 06:02:13 AM UTC 24 |
92453534762 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/251.uart_fifo_reset.1804657872 |
|
|
Oct 09 06:00:16 AM UTC 24 |
Oct 09 06:02:15 AM UTC 24 |
229533557892 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/280.uart_fifo_reset.3934482328 |
|
|
Oct 09 06:01:13 AM UTC 24 |
Oct 09 06:02:18 AM UTC 24 |
140989390873 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/120.uart_fifo_reset.1627668466 |
|
|
Oct 09 05:56:18 AM UTC 24 |
Oct 09 06:02:21 AM UTC 24 |
211107931939 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/259.uart_fifo_reset.3274366934 |
|
|
Oct 09 06:00:28 AM UTC 24 |
Oct 09 06:02:21 AM UTC 24 |
123424872510 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/207.uart_fifo_reset.3846792685 |
|
|
Oct 09 05:58:42 AM UTC 24 |
Oct 09 06:02:22 AM UTC 24 |
108004658792 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/273.uart_fifo_reset.561675791 |
|
|
Oct 09 06:00:59 AM UTC 24 |
Oct 09 06:02:26 AM UTC 24 |
107267660237 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/197.uart_fifo_reset.2735388062 |
|
|
Oct 09 05:58:25 AM UTC 24 |
Oct 09 06:02:29 AM UTC 24 |
131068093556 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/292.uart_fifo_reset.4128414538 |
|
|
Oct 09 06:01:34 AM UTC 24 |
Oct 09 06:02:40 AM UTC 24 |
164271743130 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/214.uart_fifo_reset.2789570593 |
|
|
Oct 09 05:58:58 AM UTC 24 |
Oct 09 06:02:42 AM UTC 24 |
96548340982 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/156.uart_fifo_reset.401598343 |
|
|
Oct 09 05:57:26 AM UTC 24 |
Oct 09 06:02:44 AM UTC 24 |
66010041473 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/274.uart_fifo_reset.912691352 |
|
|
Oct 09 06:01:00 AM UTC 24 |
Oct 09 06:02:54 AM UTC 24 |
94303189318 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/298.uart_fifo_reset.1120178206 |
|
|
Oct 09 06:01:47 AM UTC 24 |
Oct 09 06:02:54 AM UTC 24 |
166653537473 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/296.uart_fifo_reset.1403982794 |
|
|
Oct 09 06:01:44 AM UTC 24 |
Oct 09 06:03:10 AM UTC 24 |
108528102259 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/255.uart_fifo_reset.527518369 |
|
|
Oct 09 06:00:24 AM UTC 24 |
Oct 09 06:03:15 AM UTC 24 |
149513559474 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/286.uart_fifo_reset.1300725253 |
|
|
Oct 09 06:01:21 AM UTC 24 |
Oct 09 06:03:27 AM UTC 24 |
54969970580 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/222.uart_fifo_reset.1624580212 |
|
|
Oct 09 05:59:12 AM UTC 24 |
Oct 09 06:03:28 AM UTC 24 |
165855853144 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/289.uart_fifo_reset.911767622 |
|
|
Oct 09 06:01:29 AM UTC 24 |
Oct 09 06:03:31 AM UTC 24 |
60752398482 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/284.uart_fifo_reset.772629243 |
|
|
Oct 09 06:01:19 AM UTC 24 |
Oct 09 06:03:31 AM UTC 24 |
67895064176 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/191.uart_fifo_reset.1175152571 |
|
|
Oct 09 05:58:16 AM UTC 24 |
Oct 09 06:03:31 AM UTC 24 |
153160003380 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/270.uart_fifo_reset.2775412334 |
|
|
Oct 09 06:00:53 AM UTC 24 |
Oct 09 06:03:33 AM UTC 24 |
133618740203 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/247.uart_fifo_reset.1823007845 |
|
|
Oct 09 06:00:10 AM UTC 24 |
Oct 09 06:03:44 AM UTC 24 |
107620321860 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_stress_all.3963052296 |
|
|
Oct 09 05:26:32 AM UTC 24 |
Oct 09 06:03:44 AM UTC 24 |
647501419282 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/257.uart_fifo_reset.3408389406 |
|
|
Oct 09 06:00:25 AM UTC 24 |
Oct 09 06:03:46 AM UTC 24 |
184498618490 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/235.uart_fifo_reset.2079067126 |
|
|
Oct 09 05:59:50 AM UTC 24 |
Oct 09 06:03:51 AM UTC 24 |
123243136984 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/133.uart_fifo_reset.3358454084 |
|
|
Oct 09 05:56:41 AM UTC 24 |
Oct 09 06:03:57 AM UTC 24 |
176630491355 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/169.uart_fifo_reset.1359473451 |
|
|
Oct 09 05:57:42 AM UTC 24 |
Oct 09 06:03:58 AM UTC 24 |
102211474095 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3319497295 |
|
|
Oct 09 06:01:49 AM UTC 24 |
Oct 09 06:04:01 AM UTC 24 |
220044479363 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/232.uart_fifo_reset.3956650603 |
|
|
Oct 09 05:59:46 AM UTC 24 |
Oct 09 06:04:05 AM UTC 24 |
152524588015 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/290.uart_fifo_reset.1928173768 |
|
|
Oct 09 06:01:29 AM UTC 24 |
Oct 09 06:04:06 AM UTC 24 |
85448989278 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_stress_all.1438988756 |
|
|
Oct 09 05:48:49 AM UTC 24 |
Oct 09 06:04:15 AM UTC 24 |
234550331384 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/102.uart_fifo_reset.3284825350 |
|
|
Oct 09 05:55:42 AM UTC 24 |
Oct 09 06:04:17 AM UTC 24 |
125735799489 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/223.uart_fifo_reset.2204118228 |
|
|
Oct 09 05:59:12 AM UTC 24 |
Oct 09 06:04:19 AM UTC 24 |
128278470841 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/293.uart_fifo_reset.3637220491 |
|
|
Oct 09 06:01:35 AM UTC 24 |
Oct 09 06:04:20 AM UTC 24 |
174301056874 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2336762246 |
|
|
Oct 09 06:00:36 AM UTC 24 |
Oct 09 06:04:27 AM UTC 24 |
150697585085 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2721415274 |
|
|
Oct 09 05:58:38 AM UTC 24 |
Oct 09 06:04:34 AM UTC 24 |
124786003873 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/277.uart_fifo_reset.3160812329 |
|
|
Oct 09 06:01:05 AM UTC 24 |
Oct 09 06:04:45 AM UTC 24 |
130912936322 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/258.uart_fifo_reset.4182092641 |
|
|
Oct 09 06:00:26 AM UTC 24 |
Oct 09 06:04:52 AM UTC 24 |
101462974996 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/281.uart_fifo_reset.1378855043 |
|
|
Oct 09 06:01:15 AM UTC 24 |
Oct 09 06:05:05 AM UTC 24 |
127872761791 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/288.uart_fifo_reset.503327801 |
|
|
Oct 09 06:01:25 AM UTC 24 |
Oct 09 06:05:09 AM UTC 24 |
97012260493 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/282.uart_fifo_reset.735408574 |
|
|
Oct 09 06:01:18 AM UTC 24 |
Oct 09 06:05:17 AM UTC 24 |
111370318595 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/234.uart_fifo_reset.2932994170 |
|
|
Oct 09 05:59:50 AM UTC 24 |
Oct 09 06:05:42 AM UTC 24 |
77953276170 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/151.uart_fifo_reset.284778942 |
|
|
Oct 09 05:57:22 AM UTC 24 |
Oct 09 06:05:42 AM UTC 24 |
190489413696 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/283.uart_fifo_reset.1648273006 |
|
|
Oct 09 06:01:19 AM UTC 24 |
Oct 09 06:05:46 AM UTC 24 |
140759708245 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.1751320536 |
|
|
Oct 09 05:51:45 AM UTC 24 |
Oct 09 06:05:48 AM UTC 24 |
110641272798 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_perf.613274906 |
|
|
Oct 09 05:49:11 AM UTC 24 |
Oct 09 06:05:55 AM UTC 24 |
15341886387 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.3458188272 |
|
|
Oct 09 05:50:50 AM UTC 24 |
Oct 09 06:06:25 AM UTC 24 |
166656906466 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_perf.2716367132 |
|
|
Oct 09 05:39:24 AM UTC 24 |
Oct 09 06:06:27 AM UTC 24 |
27868608216 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_stress_all.204144011 |
|
|
Oct 09 05:41:36 AM UTC 24 |
Oct 09 06:07:15 AM UTC 24 |
597517356179 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/285.uart_fifo_reset.2575687452 |
|
|
Oct 09 06:01:20 AM UTC 24 |
Oct 09 06:07:17 AM UTC 24 |
170139697969 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_stress_all.2492367636 |
|
|
Oct 09 05:38:27 AM UTC 24 |
Oct 09 06:09:46 AM UTC 24 |
430728963050 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/297.uart_fifo_reset.1674969859 |
|
|
Oct 09 06:01:45 AM UTC 24 |
Oct 09 06:17:03 AM UTC 24 |
233457490806 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_stress_all.419523901 |
|
|
Oct 09 05:44:51 AM UTC 24 |
Oct 09 06:35:43 AM UTC 24 |
333275359273 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.1647036437 |
|
|
Oct 09 07:13:39 AM UTC 24 |
Oct 09 07:13:41 AM UTC 24 |
391496370 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.1802581242 |
|
|
Oct 09 07:13:39 AM UTC 24 |
Oct 09 07:13:41 AM UTC 24 |
16727588 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.3822729340 |
|
|
Oct 09 07:13:39 AM UTC 24 |
Oct 09 07:13:41 AM UTC 24 |
16661862 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1875897085 |
|
|
Oct 09 07:13:39 AM UTC 24 |
Oct 09 07:13:41 AM UTC 24 |
14598385 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.372127845 |
|
|
Oct 09 07:13:39 AM UTC 24 |
Oct 09 07:13:41 AM UTC 24 |
31025538 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2364559962 |
|
|
Oct 09 07:13:39 AM UTC 24 |
Oct 09 07:13:42 AM UTC 24 |
61919500 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3048256051 |
|
|
Oct 09 07:13:54 AM UTC 24 |
Oct 09 07:13:57 AM UTC 24 |
36832368 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.2497432213 |
|
|
Oct 09 07:13:40 AM UTC 24 |
Oct 09 07:13:42 AM UTC 24 |
53100325 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3145659478 |
|
|
Oct 09 07:13:41 AM UTC 24 |
Oct 09 07:13:42 AM UTC 24 |
22971991 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.1524897495 |
|
|
Oct 09 07:13:41 AM UTC 24 |
Oct 09 07:13:43 AM UTC 24 |
18061538 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.1528961314 |
|
|
Oct 09 07:13:41 AM UTC 24 |
Oct 09 07:13:43 AM UTC 24 |
48319613 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.2231245621 |
|
|
Oct 09 07:13:41 AM UTC 24 |
Oct 09 07:13:43 AM UTC 24 |
158533244 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.179615286 |
|
|
Oct 09 07:13:41 AM UTC 24 |
Oct 09 07:13:43 AM UTC 24 |
606510643 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3649887426 |
|
|
Oct 09 07:13:40 AM UTC 24 |
Oct 09 07:13:43 AM UTC 24 |
77371024 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.4066565047 |
|
|
Oct 09 07:13:41 AM UTC 24 |
Oct 09 07:13:43 AM UTC 24 |
139236990 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.2055501646 |
|
|
Oct 09 07:13:39 AM UTC 24 |
Oct 09 07:13:43 AM UTC 24 |
663865910 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.1028800617 |
|
|
Oct 09 07:13:41 AM UTC 24 |
Oct 09 07:13:44 AM UTC 24 |
125665453 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2500165271 |
|
|
Oct 09 07:13:42 AM UTC 24 |
Oct 09 07:13:44 AM UTC 24 |
15045010 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1387476192 |
|
|
Oct 09 07:13:42 AM UTC 24 |
Oct 09 07:13:44 AM UTC 24 |
29963646 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.3787294785 |
|
|
Oct 09 07:13:42 AM UTC 24 |
Oct 09 07:13:44 AM UTC 24 |
95347959 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2197143344 |
|
|
Oct 09 07:13:41 AM UTC 24 |
Oct 09 07:13:44 AM UTC 24 |
189735953 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.2982753860 |
|
|
Oct 09 07:13:42 AM UTC 24 |
Oct 09 07:13:44 AM UTC 24 |
53152251 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.148375495 |
|
|
Oct 09 07:13:42 AM UTC 24 |
Oct 09 07:13:44 AM UTC 24 |
61459723 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.278296206 |
|
|
Oct 09 07:13:42 AM UTC 24 |
Oct 09 07:13:45 AM UTC 24 |
81040286 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.739650959 |
|
|
Oct 09 07:13:42 AM UTC 24 |
Oct 09 07:13:45 AM UTC 24 |
1379383303 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.907925591 |
|
|
Oct 09 07:13:43 AM UTC 24 |
Oct 09 07:13:45 AM UTC 24 |
79425971 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.4288650629 |
|
|
Oct 09 07:13:44 AM UTC 24 |
Oct 09 07:13:45 AM UTC 24 |
52170153 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.3577435237 |
|
|
Oct 09 07:13:44 AM UTC 24 |
Oct 09 07:13:46 AM UTC 24 |
51164421 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2960020476 |
|
|
Oct 09 07:13:44 AM UTC 24 |
Oct 09 07:13:46 AM UTC 24 |
33099872 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.2011887397 |
|
|
Oct 09 07:13:42 AM UTC 24 |
Oct 09 07:13:46 AM UTC 24 |
109001044 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.132169626 |
|
|
Oct 09 07:13:44 AM UTC 24 |
Oct 09 07:13:46 AM UTC 24 |
42130709 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2121456134 |
|
|
Oct 09 07:13:44 AM UTC 24 |
Oct 09 07:13:46 AM UTC 24 |
21024174 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.1389784498 |
|
|
Oct 09 07:13:44 AM UTC 24 |
Oct 09 07:13:46 AM UTC 24 |
75178032 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2281041107 |
|
|
Oct 09 07:13:44 AM UTC 24 |
Oct 09 07:13:47 AM UTC 24 |
130882986 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.2749497428 |
|
|
Oct 09 07:13:51 AM UTC 24 |
Oct 09 07:13:53 AM UTC 24 |
54759161 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3817058111 |
|
|
Oct 09 07:13:45 AM UTC 24 |
Oct 09 07:13:47 AM UTC 24 |
28258391 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.4235787990 |
|
|
Oct 09 07:13:53 AM UTC 24 |
Oct 09 07:13:56 AM UTC 24 |
42787762 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.2245058128 |
|
|
Oct 09 07:13:45 AM UTC 24 |
Oct 09 07:13:47 AM UTC 24 |
54896282 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.535169987 |
|
|
Oct 09 07:13:53 AM UTC 24 |
Oct 09 07:13:56 AM UTC 24 |
22976656 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.2657682192 |
|
|
Oct 09 07:13:45 AM UTC 24 |
Oct 09 07:13:47 AM UTC 24 |
37977201 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.3406195931 |
|
|
Oct 09 07:13:44 AM UTC 24 |
Oct 09 07:13:47 AM UTC 24 |
107759605 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.163641548 |
|
|
Oct 09 07:13:45 AM UTC 24 |
Oct 09 07:13:47 AM UTC 24 |
36648163 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.711308095 |
|
|
Oct 09 07:13:45 AM UTC 24 |
Oct 09 07:13:47 AM UTC 24 |
14361323 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.1620836765 |
|
|
Oct 09 07:13:46 AM UTC 24 |
Oct 09 07:13:47 AM UTC 24 |
41670859 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.3148741233 |
|
|
Oct 09 07:13:45 AM UTC 24 |
Oct 09 07:13:48 AM UTC 24 |
97230304 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3067192398 |
|
|
Oct 09 07:13:45 AM UTC 24 |
Oct 09 07:13:49 AM UTC 24 |
497915636 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3101684180 |
|
|
Oct 09 07:13:47 AM UTC 24 |
Oct 09 07:13:49 AM UTC 24 |
69298218 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.2975528470 |
|
|
Oct 09 07:13:52 AM UTC 24 |
Oct 09 07:13:53 AM UTC 24 |
128775832 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3493336124 |
|
|
Oct 09 07:13:47 AM UTC 24 |
Oct 09 07:13:49 AM UTC 24 |
32543544 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.111789418 |
|
|
Oct 09 07:13:47 AM UTC 24 |
Oct 09 07:13:49 AM UTC 24 |
72916919 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2817883660 |
|
|
Oct 09 07:13:47 AM UTC 24 |
Oct 09 07:13:49 AM UTC 24 |
31611701 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.2663463818 |
|
|
Oct 09 07:13:47 AM UTC 24 |
Oct 09 07:13:49 AM UTC 24 |
29773583 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.3180779742 |
|
|
Oct 09 07:13:47 AM UTC 24 |
Oct 09 07:13:49 AM UTC 24 |
19691448 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3357229938 |
|
|
Oct 09 07:13:47 AM UTC 24 |
Oct 09 07:13:49 AM UTC 24 |
125739521 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3629090173 |
|
|
Oct 09 07:13:47 AM UTC 24 |
Oct 09 07:13:49 AM UTC 24 |
69258266 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3519067098 |
|
|
Oct 09 07:13:46 AM UTC 24 |
Oct 09 07:13:50 AM UTC 24 |
218902700 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3765845724 |
|
|
Oct 09 07:13:47 AM UTC 24 |
Oct 09 07:13:50 AM UTC 24 |
73377877 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.1862668011 |
|
|
Oct 09 07:13:47 AM UTC 24 |
Oct 09 07:13:50 AM UTC 24 |
626653211 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.162790928 |
|
|
Oct 09 07:13:47 AM UTC 24 |
Oct 09 07:13:50 AM UTC 24 |
185664064 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.453961434 |
|
|
Oct 09 07:13:49 AM UTC 24 |
Oct 09 07:13:51 AM UTC 24 |
10690162 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.1889572024 |
|
|
Oct 09 07:13:49 AM UTC 24 |
Oct 09 07:13:51 AM UTC 24 |
28377679 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.96229193 |
|
|
Oct 09 07:13:49 AM UTC 24 |
Oct 09 07:13:51 AM UTC 24 |
57848891 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.74499361 |
|
|
Oct 09 07:13:49 AM UTC 24 |
Oct 09 07:13:51 AM UTC 24 |
53047949 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.3404658978 |
|
|
Oct 09 07:13:49 AM UTC 24 |
Oct 09 07:13:51 AM UTC 24 |
101629892 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.2480017196 |
|
|
Oct 09 07:13:49 AM UTC 24 |
Oct 09 07:13:51 AM UTC 24 |
13907691 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.1880513386 |
|
|
Oct 09 07:13:49 AM UTC 24 |
Oct 09 07:13:52 AM UTC 24 |
497295086 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.1272289333 |
|
|
Oct 09 07:13:49 AM UTC 24 |
Oct 09 07:13:53 AM UTC 24 |
88984974 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.1015848698 |
|
|
Oct 09 07:13:51 AM UTC 24 |
Oct 09 07:13:53 AM UTC 24 |
35588538 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.794281358 |
|
|
Oct 09 07:13:51 AM UTC 24 |
Oct 09 07:13:53 AM UTC 24 |
95171052 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.70745753 |
|
|
Oct 09 07:13:51 AM UTC 24 |
Oct 09 07:13:53 AM UTC 24 |
23473965 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1277226801 |
|
|
Oct 09 07:13:51 AM UTC 24 |
Oct 09 07:13:53 AM UTC 24 |
69183878 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.1923760208 |
|
|
Oct 09 07:13:51 AM UTC 24 |
Oct 09 07:13:53 AM UTC 24 |
13855792 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.3999511835 |
|
|
Oct 09 07:13:52 AM UTC 24 |
Oct 09 07:13:53 AM UTC 24 |
16945801 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.448373795 |
|
|
Oct 09 07:13:51 AM UTC 24 |
Oct 09 07:13:53 AM UTC 24 |
73376750 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.3279610418 |
|
|
Oct 09 07:13:51 AM UTC 24 |
Oct 09 07:13:53 AM UTC 24 |
36945444 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.4076425760 |
|
|
Oct 09 07:13:51 AM UTC 24 |
Oct 09 07:13:54 AM UTC 24 |
167993665 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3388296549 |
|
|
Oct 09 07:13:52 AM UTC 24 |
Oct 09 07:13:54 AM UTC 24 |
175306093 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.482288065 |
|
|
Oct 09 07:13:51 AM UTC 24 |
Oct 09 07:13:55 AM UTC 24 |
71258410 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1279110814 |
|
|
Oct 09 07:13:54 AM UTC 24 |
Oct 09 07:13:56 AM UTC 24 |
101766150 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1349774522 |
|
|
Oct 09 07:13:54 AM UTC 24 |
Oct 09 07:13:55 AM UTC 24 |
33687618 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.978038204 |
|
|
Oct 09 07:13:54 AM UTC 24 |
Oct 09 07:13:56 AM UTC 24 |
55271148 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2923011515 |
|
|
Oct 09 07:13:53 AM UTC 24 |
Oct 09 07:13:55 AM UTC 24 |
15618126 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.62422108 |
|
|
Oct 09 07:13:54 AM UTC 24 |
Oct 09 07:13:55 AM UTC 24 |
13186490 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2595801885 |
|
|
Oct 09 07:13:54 AM UTC 24 |
Oct 09 07:13:55 AM UTC 24 |
112736242 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.1042892712 |
|
|
Oct 09 07:13:54 AM UTC 24 |
Oct 09 07:13:56 AM UTC 24 |
16496662 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.1572768400 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:58 AM UTC 24 |
21773745 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2740884973 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:58 AM UTC 24 |
42913442 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.2403427375 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:58 AM UTC 24 |
98363439 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3348455984 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:58 AM UTC 24 |
50835187 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.3290516914 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:58 AM UTC 24 |
21539754 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1002210819 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:58 AM UTC 24 |
40334585 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.84116177 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:58 AM UTC 24 |
36500836 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1662113251 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:58 AM UTC 24 |
113693991 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2320239655 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:58 AM UTC 24 |
70559857 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.392214041 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:59 AM UTC 24 |
136601360 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1905015112 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:59 AM UTC 24 |
34480278 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.618673121 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:59 AM UTC 24 |
49196058 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.993483230 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:13:59 AM UTC 24 |
106109697 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3797280563 |
|
|
Oct 09 07:13:56 AM UTC 24 |
Oct 09 07:14:00 AM UTC 24 |
208774870 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.882285217 |
|
|
Oct 09 07:13:59 AM UTC 24 |
Oct 09 07:14:01 AM UTC 24 |
108584457 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.1487955911 |
|
|
Oct 09 07:13:59 AM UTC 24 |
Oct 09 07:14:01 AM UTC 24 |
13913033 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.618245665 |
|
|
Oct 09 07:13:59 AM UTC 24 |
Oct 09 07:14:01 AM UTC 24 |
41361899 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.850824618 |
|
|
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16508526 ps |