| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.10 | 99.08 | 97.65 | 100.00 | 98.35 | 100.00 | 99.53 |
| T1258 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3162159240 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:01 AM UTC 24 | 38881437 ps | ||
| T1259 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.3856856405 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:01 AM UTC 24 | 61694379 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.358423158 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:02 AM UTC 24 | 51794896 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.335091083 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:02 AM UTC 24 | 53901612 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.1399536240 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:02 AM UTC 24 | 44223418 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.1844988851 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:02 AM UTC 24 | 14431387 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1900949787 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:02 AM UTC 24 | 23874337 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1853094801 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:02 AM UTC 24 | 83546914 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.1959160922 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:02 AM UTC 24 | 54422158 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.3043107234 | Oct 09 07:13:59 AM UTC 24 | Oct 09 07:14:02 AM UTC 24 | 243823392 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.1765275676 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:02 AM UTC 24 | 1760398650 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2428240699 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:02 AM UTC 24 | 25059845 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1980072159 | Oct 09 07:14:00 AM UTC 24 | Oct 09 07:14:03 AM UTC 24 | 38651050 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.720962059 | Oct 09 07:14:03 AM UTC 24 | Oct 09 07:14:05 AM UTC 24 | 13579387 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.2499170689 | Oct 09 07:14:03 AM UTC 24 | Oct 09 07:14:05 AM UTC 24 | 44185387 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2443425211 | Oct 09 07:14:03 AM UTC 24 | Oct 09 07:14:05 AM UTC 24 | 43204769 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.4051928661 | Oct 09 07:14:03 AM UTC 24 | Oct 09 07:14:05 AM UTC 24 | 67864089 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3233708720 | Oct 09 07:14:03 AM UTC 24 | Oct 09 07:14:05 AM UTC 24 | 11430249 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3515186594 | Oct 09 07:14:03 AM UTC 24 | Oct 09 07:14:05 AM UTC 24 | 89364072 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.1290336941 | Oct 09 07:14:03 AM UTC 24 | Oct 09 07:14:05 AM UTC 24 | 19965384 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3174407738 | Oct 09 07:14:03 AM UTC 24 | Oct 09 07:14:05 AM UTC 24 | 77946331 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.4115402327 | Oct 09 07:14:04 AM UTC 24 | Oct 09 07:14:05 AM UTC 24 | 18633310 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.576330865 | Oct 09 07:14:04 AM UTC 24 | Oct 09 07:14:05 AM UTC 24 | 44999324 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.2195723718 | Oct 09 07:14:03 AM UTC 24 | Oct 09 07:14:05 AM UTC 24 | 25457257 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.3825266948 | Oct 09 07:14:04 AM UTC 24 | Oct 09 07:14:06 AM UTC 24 | 13496167 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2657411203 | Oct 09 07:14:04 AM UTC 24 | Oct 09 07:14:06 AM UTC 24 | 136600963 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.1194909927 | Oct 09 07:14:03 AM UTC 24 | Oct 09 07:14:06 AM UTC 24 | 85278935 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.2687319792 | Oct 09 07:14:04 AM UTC 24 | Oct 09 07:14:06 AM UTC 24 | 60458699 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.147230956 | Oct 09 07:14:03 AM UTC 24 | Oct 09 07:14:06 AM UTC 24 | 111252393 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.3183195552 | Oct 09 07:14:04 AM UTC 24 | Oct 09 07:14:06 AM UTC 24 | 41235011 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3877693270 | Oct 09 07:14:04 AM UTC 24 | Oct 09 07:14:06 AM UTC 24 | 27696970 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.164213488 | Oct 09 07:14:07 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 15216791 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1335078645 | Oct 09 07:14:07 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 51119075 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1176433840 | Oct 09 07:14:07 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 108339035 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.4268860208 | Oct 09 07:14:07 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 11210484 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.4176224404 | Oct 09 07:14:07 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 15781715 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.2827213401 | Oct 09 07:14:07 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 53909575 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3875763896 | Oct 09 07:14:07 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 22081180 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3441324315 | Oct 09 07:14:07 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 54700898 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.293298267 | Oct 09 07:14:08 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 32218989 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2376706586 | Oct 09 07:14:08 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 12981876 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1513581735 | Oct 09 07:14:08 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 17786280 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.178419230 | Oct 09 07:14:08 AM UTC 24 | Oct 09 07:14:09 AM UTC 24 | 39179265 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.246014118 | Oct 09 07:14:08 AM UTC 24 | Oct 09 07:14:10 AM UTC 24 | 42416260 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.912877299 | Oct 09 07:14:08 AM UTC 24 | Oct 09 07:14:10 AM UTC 24 | 16246064 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.793714942 | Oct 09 07:14:08 AM UTC 24 | Oct 09 07:14:10 AM UTC 24 | 28439963 ps | ||
| T1297 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.3167060495 | Oct 09 07:14:08 AM UTC 24 | Oct 09 07:14:10 AM UTC 24 | 13581812 ps | ||
| T1298 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2252942109 | Oct 09 07:14:08 AM UTC 24 | Oct 09 07:14:10 AM UTC 24 | 14611252 ps | ||
| T1299 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.3413112079 | Oct 09 07:14:08 AM UTC 24 | Oct 09 07:14:10 AM UTC 24 | 13624655 ps | ||
| T1300 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3538143239 | Oct 09 07:14:13 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 14306332 ps | ||
| T1301 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1063485828 | Oct 09 07:14:13 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 22307164 ps | ||
| T1302 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.4057174314 | Oct 09 07:14:13 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 26684169 ps | ||
| T1303 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3952661115 | Oct 09 07:14:13 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 11788102 ps | ||
| T1304 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1852202483 | Oct 09 07:14:13 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 48887028 ps | ||
| T1305 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1549222635 | Oct 09 07:14:13 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 15084314 ps | ||
| T1306 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.367099859 | Oct 09 07:14:13 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 17865006 ps | ||
| T1307 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.3848663203 | Oct 09 07:14:13 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 15597686 ps | ||
| T1308 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.3893189322 | Oct 09 07:14:14 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 12736932 ps | ||
| T1309 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.3735285720 | Oct 09 07:14:14 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 23540358 ps | ||
| T1310 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.927363048 | Oct 09 07:14:14 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 42282184 ps | ||
| T1311 | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.1331290019 | Oct 09 07:14:14 AM UTC 24 | Oct 09 07:14:15 AM UTC 24 | 14409570 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_loopback.2366518009 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3001888550 ps |
| CPU time | 3.92 seconds |
| Started | Oct 09 05:26:14 AM UTC 24 |
| Finished | Oct 09 05:26:19 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366518009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2366518009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.2727720527 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9967300885 ps |
| CPU time | 33.08 seconds |
| Started | Oct 09 05:26:15 AM UTC 24 |
| Finished | Oct 09 05:26:49 AM UTC 24 |
| Peak memory | 225328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2727720527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_ with_rand_reset.2727720527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.1735355411 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 50125068997 ps |
| CPU time | 28.25 seconds |
| Started | Oct 09 05:26:12 AM UTC 24 |
| Finished | Oct 09 05:26:42 AM UTC 24 |
| Peak memory | 209296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735355411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1735355411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_stress_all.1647609186 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 396300485133 ps |
| CPU time | 529.79 seconds |
| Started | Oct 09 05:26:16 AM UTC 24 |
| Finished | Oct 09 05:35:12 AM UTC 24 |
| Peak memory | 229468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647609186 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1647609186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_stress_all.3237622991 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 346495017939 ps |
| CPU time | 352.25 seconds |
| Started | Oct 09 05:29:38 AM UTC 24 |
| Finished | Oct 09 05:35:34 AM UTC 24 |
| Peak memory | 222116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237622991 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3237622991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_intr.156351167 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 35559220819 ps |
| CPU time | 18.58 seconds |
| Started | Oct 09 05:26:12 AM UTC 24 |
| Finished | Oct 09 05:26:32 AM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156351167 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.156351167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.2120839309 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 16320777938 ps |
| CPU time | 63.7 seconds |
| Started | Oct 09 05:27:39 AM UTC 24 |
| Finished | Oct 09 05:28:45 AM UTC 24 |
| Peak memory | 222560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2120839309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_ with_rand_reset.2120839309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_stress_all.4241745075 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 592669515829 ps |
| CPU time | 534.93 seconds |
| Started | Oct 09 05:26:56 AM UTC 24 |
| Finished | Oct 09 05:35:58 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241745075 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.4241745075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.4294262015 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 122921394687 ps |
| CPU time | 106.4 seconds |
| Started | Oct 09 05:30:01 AM UTC 24 |
| Finished | Oct 09 05:31:49 AM UTC 24 |
| Peak memory | 204336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294262015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.4294262015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_fifo_full.1844079740 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 40281696075 ps |
| CPU time | 69.43 seconds |
| Started | Oct 09 05:27:21 AM UTC 24 |
| Finished | Oct 09 05:28:33 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844079740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1844079740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.416870578 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 111151791496 ps |
| CPU time | 101.71 seconds |
| Started | Oct 09 05:28:51 AM UTC 24 |
| Finished | Oct 09 05:30:35 AM UTC 24 |
| Peak memory | 203916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416870578 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.416870578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_stress_all.543754756 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 361662575404 ps |
| CPU time | 400 seconds |
| Started | Oct 09 05:29:21 AM UTC 24 |
| Finished | Oct 09 05:36:06 AM UTC 24 |
| Peak memory | 209408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543754756 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.543754756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_sec_cm.2205244493 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 98848442 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 05:26:17 AM UTC 24 |
| Finished | Oct 09 05:26:19 AM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205244493 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2205244493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.87616560 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 107728818811 ps |
| CPU time | 102.15 seconds |
| Started | Oct 09 05:31:47 AM UTC 24 |
| Finished | Oct 09 05:33:31 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87616560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.87616560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_stress_all.1079000547 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 237616429189 ps |
| CPU time | 262.98 seconds |
| Started | Oct 09 05:31:19 AM UTC 24 |
| Finished | Oct 09 05:35:46 AM UTC 24 |
| Peak memory | 203988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079000547 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1079000547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.3205372370 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 141589038659 ps |
| CPU time | 56.27 seconds |
| Started | Oct 09 05:26:37 AM UTC 24 |
| Finished | Oct 09 05:27:35 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205372370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3205372370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_stress_all.3917022316 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 124310211153 ps |
| CPU time | 346.76 seconds |
| Started | Oct 09 05:27:39 AM UTC 24 |
| Finished | Oct 09 05:33:31 AM UTC 24 |
| Peak memory | 209772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917022316 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3917022316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_fifo_reset.1871749652 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 55907643662 ps |
| CPU time | 110.03 seconds |
| Started | Oct 09 05:28:35 AM UTC 24 |
| Finished | Oct 09 05:30:27 AM UTC 24 |
| Peak memory | 209620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871749652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1871749652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.3739045453 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 93814057411 ps |
| CPU time | 168.43 seconds |
| Started | Oct 09 05:29:17 AM UTC 24 |
| Finished | Oct 09 05:32:08 AM UTC 24 |
| Peak memory | 206028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739045453 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3739045453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1875897085 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 14598385 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 07:13:39 AM UTC 24 |
| Finished | Oct 09 07:13:41 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875897085 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1875897085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.3248654564 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 10645530530 ps |
| CPU time | 64.87 seconds |
| Started | Oct 09 05:30:12 AM UTC 24 |
| Finished | Oct 09 05:31:19 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3248654564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all _with_rand_reset.3248654564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_perf.3989417392 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13782569665 ps |
| CPU time | 183.43 seconds |
| Started | Oct 09 05:26:14 AM UTC 24 |
| Finished | Oct 09 05:29:20 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989417392 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3989417392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.2045035085 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 15480604575 ps |
| CPU time | 118.18 seconds |
| Started | Oct 09 05:32:08 AM UTC 24 |
| Finished | Oct 09 05:34:08 AM UTC 24 |
| Peak memory | 222544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2045035085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all _with_rand_reset.2045035085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_tx_rx.504763709 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 92123817187 ps |
| CPU time | 201.41 seconds |
| Started | Oct 09 05:28:03 AM UTC 24 |
| Finished | Oct 09 05:31:28 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504763709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.504763709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.3050706338 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 87402540019 ps |
| CPU time | 111.07 seconds |
| Started | Oct 09 05:29:19 AM UTC 24 |
| Finished | Oct 09 05:31:12 AM UTC 24 |
| Peak memory | 226508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3050706338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_ with_rand_reset.3050706338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_noise_filter.2747498954 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 85226126752 ps |
| CPU time | 237.65 seconds |
| Started | Oct 09 05:26:24 AM UTC 24 |
| Finished | Oct 09 05:30:25 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747498954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2747498954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.1389784498 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 75178032 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 07:13:44 AM UTC 24 |
| Finished | Oct 09 07:13:46 AM UTC 24 |
| Peak memory | 201096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389784498 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1389784498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.1722506208 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 154162593308 ps |
| CPU time | 356.71 seconds |
| Started | Oct 09 05:30:28 AM UTC 24 |
| Finished | Oct 09 05:36:29 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722506208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1722506208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_fifo_full.1610454746 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 68904649105 ps |
| CPU time | 59.81 seconds |
| Started | Oct 09 05:34:22 AM UTC 24 |
| Finished | Oct 09 05:35:24 AM UTC 24 |
| Peak memory | 209512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610454746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1610454746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_perf.4155065716 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 20954861309 ps |
| CPU time | 259.52 seconds |
| Started | Oct 09 05:27:37 AM UTC 24 |
| Finished | Oct 09 05:32:00 AM UTC 24 |
| Peak memory | 209364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155065716 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.4155065716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_alert_test.921200671 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 36451662 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 05:26:17 AM UTC 24 |
| Finished | Oct 09 05:26:19 AM UTC 24 |
| Peak memory | 203344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921200671 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.921200671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_stress_all.3946869602 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 45673928299 ps |
| CPU time | 427.68 seconds |
| Started | Oct 09 05:28:26 AM UTC 24 |
| Finished | Oct 09 05:35:39 AM UTC 24 |
| Peak memory | 204088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946869602 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3946869602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_fifo_full.298415221 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 37497123783 ps |
| CPU time | 68.07 seconds |
| Started | Oct 09 05:26:36 AM UTC 24 |
| Finished | Oct 09 05:27:46 AM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298415221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.298415221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_fifo_reset.3472090600 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 73661445015 ps |
| CPU time | 47.39 seconds |
| Started | Oct 09 05:33:44 AM UTC 24 |
| Finished | Oct 09 05:34:33 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472090600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3472090600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.2456811775 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 45143645265 ps |
| CPU time | 126.9 seconds |
| Started | Oct 09 05:26:19 AM UTC 24 |
| Finished | Oct 09 05:28:29 AM UTC 24 |
| Peak memory | 209756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456811775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2456811775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_stress_all.158196447 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 315448600803 ps |
| CPU time | 252.63 seconds |
| Started | Oct 09 05:39:30 AM UTC 24 |
| Finished | Oct 09 05:43:47 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158196447 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.158196447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_noise_filter.3971102864 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 117840933982 ps |
| CPU time | 57.43 seconds |
| Started | Oct 09 05:26:12 AM UTC 24 |
| Finished | Oct 09 05:27:11 AM UTC 24 |
| Peak memory | 209756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971102864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3971102864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.4066565047 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 139236990 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 07:13:41 AM UTC 24 |
| Finished | Oct 09 07:13:43 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066565047 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.4066565047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.2514223448 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 141009493481 ps |
| CPU time | 85.7 seconds |
| Started | Oct 09 05:31:22 AM UTC 24 |
| Finished | Oct 09 05:32:50 AM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514223448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2514223448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_stress_all.1903488071 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 254040103838 ps |
| CPU time | 467.61 seconds |
| Started | Oct 09 05:36:02 AM UTC 24 |
| Finished | Oct 09 05:43:55 AM UTC 24 |
| Peak memory | 218460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903488071 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1903488071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1749330763 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7399333740 ps |
| CPU time | 110.53 seconds |
| Started | Oct 09 05:26:54 AM UTC 24 |
| Finished | Oct 09 05:28:47 AM UTC 24 |
| Peak memory | 222748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1749330763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_ with_rand_reset.1749330763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_tx_rx.2095193182 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 78019348263 ps |
| CPU time | 240.31 seconds |
| Started | Oct 09 05:27:42 AM UTC 24 |
| Finished | Oct 09 05:31:46 AM UTC 24 |
| Peak memory | 209892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095193182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2095193182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_perf.3868055779 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 27117800138 ps |
| CPU time | 233.71 seconds |
| Started | Oct 09 05:27:13 AM UTC 24 |
| Finished | Oct 09 05:31:10 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868055779 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3868055779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_fifo_reset.1943236971 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 94889412788 ps |
| CPU time | 34.36 seconds |
| Started | Oct 09 05:47:52 AM UTC 24 |
| Finished | Oct 09 05:48:28 AM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943236971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1943236971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.1006420333 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 50484667263 ps |
| CPU time | 103.32 seconds |
| Started | Oct 09 05:28:34 AM UTC 24 |
| Finished | Oct 09 05:30:20 AM UTC 24 |
| Peak memory | 209612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006420333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1006420333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.618673121 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 49196058 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:59 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618673121 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.618673121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2114195492 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 24218803603 ps |
| CPU time | 18.35 seconds |
| Started | Oct 09 05:26:11 AM UTC 24 |
| Finished | Oct 09 05:26:30 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114195492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2114195492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_stress_all.702544190 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 137292049138 ps |
| CPU time | 294.26 seconds |
| Started | Oct 09 05:32:37 AM UTC 24 |
| Finished | Oct 09 05:37:36 AM UTC 24 |
| Peak memory | 209412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702544190 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.702544190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_stress_all.3082036126 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 133955993256 ps |
| CPU time | 322.66 seconds |
| Started | Oct 09 05:34:56 AM UTC 24 |
| Finished | Oct 09 05:40:23 AM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082036126 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3082036126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/260.uart_fifo_reset.1565143065 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 90794297637 ps |
| CPU time | 40.44 seconds |
| Started | Oct 09 06:00:32 AM UTC 24 |
| Finished | Oct 09 06:01:14 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565143065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1565143065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/260.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_fifo_reset.2744796828 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 232487772792 ps |
| CPU time | 88.88 seconds |
| Started | Oct 09 05:37:12 AM UTC 24 |
| Finished | Oct 09 05:38:43 AM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744796828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2744796828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/298.uart_fifo_reset.1120178206 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 166653537473 ps |
| CPU time | 65.98 seconds |
| Started | Oct 09 06:01:47 AM UTC 24 |
| Finished | Oct 09 06:02:54 AM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120178206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1120178206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/298.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.1765275676 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1760398650 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:02 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765275676 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1765275676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_intr.2248522935 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 66395478632 ps |
| CPU time | 62.03 seconds |
| Started | Oct 09 05:31:28 AM UTC 24 |
| Finished | Oct 09 05:32:32 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248522935 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2248522935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_tx_rx.1630780459 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 75669530878 ps |
| CPU time | 80.48 seconds |
| Started | Oct 09 05:32:42 AM UTC 24 |
| Finished | Oct 09 05:34:04 AM UTC 24 |
| Peak memory | 209260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630780459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1630780459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_fifo_full.4120855692 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 206590165745 ps |
| CPU time | 207.72 seconds |
| Started | Oct 09 05:26:19 AM UTC 24 |
| Finished | Oct 09 05:29:51 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120855692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4120855692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.2000599031 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 50699653750 ps |
| CPU time | 31.4 seconds |
| Started | Oct 09 05:31:01 AM UTC 24 |
| Finished | Oct 09 05:31:33 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000599031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2000599031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/125.uart_fifo_reset.276718307 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 17198964926 ps |
| CPU time | 24.04 seconds |
| Started | Oct 09 05:56:30 AM UTC 24 |
| Finished | Oct 09 05:56:55 AM UTC 24 |
| Peak memory | 209696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276718307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.276718307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/125.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/53.uart_fifo_reset.2182471667 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 27050779770 ps |
| CPU time | 8.5 seconds |
| Started | Oct 09 05:52:06 AM UTC 24 |
| Finished | Oct 09 05:52:15 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182471667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2182471667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/53.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/109.uart_fifo_reset.2878504210 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 170212206756 ps |
| CPU time | 75.93 seconds |
| Started | Oct 09 05:56:03 AM UTC 24 |
| Finished | Oct 09 05:57:21 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878504210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2878504210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/109.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.3705916273 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 15268031484 ps |
| CPU time | 88.49 seconds |
| Started | Oct 09 05:31:13 AM UTC 24 |
| Finished | Oct 09 05:32:44 AM UTC 24 |
| Peak memory | 218452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3705916273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all _with_rand_reset.3705916273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_tx_rx.1026153287 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 37208748657 ps |
| CPU time | 104.7 seconds |
| Started | Oct 09 05:31:46 AM UTC 24 |
| Finished | Oct 09 05:33:33 AM UTC 24 |
| Peak memory | 209680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026153287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1026153287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.660316665 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 64468523509 ps |
| CPU time | 60.55 seconds |
| Started | Oct 09 05:32:30 AM UTC 24 |
| Finished | Oct 09 05:33:32 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660316665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.660316665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_noise_filter.2005179746 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 93512987034 ps |
| CPU time | 205.14 seconds |
| Started | Oct 09 05:26:43 AM UTC 24 |
| Finished | Oct 09 05:30:11 AM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005179746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2005179746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/270.uart_fifo_reset.2775412334 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 133618740203 ps |
| CPU time | 157.25 seconds |
| Started | Oct 09 06:00:53 AM UTC 24 |
| Finished | Oct 09 06:03:33 AM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775412334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2775412334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/270.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_fifo_reset.1801876873 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 24505240872 ps |
| CPU time | 48.01 seconds |
| Started | Oct 09 05:51:26 AM UTC 24 |
| Finished | Oct 09 05:52:15 AM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801876873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1801876873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/73.uart_fifo_reset.2804567609 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 62904369614 ps |
| CPU time | 161.47 seconds |
| Started | Oct 09 05:53:53 AM UTC 24 |
| Finished | Oct 09 05:56:38 AM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804567609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2804567609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/73.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_fifo_full.194285806 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 23656214117 ps |
| CPU time | 41.85 seconds |
| Started | Oct 09 05:29:48 AM UTC 24 |
| Finished | Oct 09 05:30:31 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194285806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.194285806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/139.uart_fifo_reset.2579704725 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 69129019321 ps |
| CPU time | 86.64 seconds |
| Started | Oct 09 05:56:53 AM UTC 24 |
| Finished | Oct 09 05:58:21 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579704725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2579704725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/139.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/140.uart_fifo_reset.2214341543 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 48681046780 ps |
| CPU time | 47.56 seconds |
| Started | Oct 09 05:56:54 AM UTC 24 |
| Finished | Oct 09 05:57:43 AM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214341543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2214341543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/140.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_tx_rx.1672066565 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 15123522529 ps |
| CPU time | 23.9 seconds |
| Started | Oct 09 05:33:12 AM UTC 24 |
| Finished | Oct 09 05:33:37 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672066565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1672066565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_fifo_reset.3720467933 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 212691472032 ps |
| CPU time | 172.22 seconds |
| Started | Oct 09 05:34:25 AM UTC 24 |
| Finished | Oct 09 05:37:22 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720467933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3720467933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/237.uart_fifo_reset.2837363954 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 152880805448 ps |
| CPU time | 87.95 seconds |
| Started | Oct 09 05:59:54 AM UTC 24 |
| Finished | Oct 09 06:01:23 AM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837363954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2837363954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/237.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/251.uart_fifo_reset.1804657872 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 229533557892 ps |
| CPU time | 116.5 seconds |
| Started | Oct 09 06:00:16 AM UTC 24 |
| Finished | Oct 09 06:02:15 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804657872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1804657872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/251.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1345302051 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 19254595484 ps |
| CPU time | 20.56 seconds |
| Started | Oct 09 06:00:56 AM UTC 24 |
| Finished | Oct 09 06:01:18 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345302051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1345302051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/271.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/273.uart_fifo_reset.561675791 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 107267660237 ps |
| CPU time | 84.53 seconds |
| Started | Oct 09 06:00:59 AM UTC 24 |
| Finished | Oct 09 06:02:26 AM UTC 24 |
| Peak memory | 209428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561675791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.561675791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/273.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/55.uart_fifo_reset.435618411 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 82174704560 ps |
| CPU time | 164.27 seconds |
| Started | Oct 09 05:52:17 AM UTC 24 |
| Finished | Oct 09 05:55:04 AM UTC 24 |
| Peak memory | 203992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435618411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.435618411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/55.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_fifo_full.967800568 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 18430894554 ps |
| CPU time | 25.32 seconds |
| Started | Oct 09 05:26:09 AM UTC 24 |
| Finished | Oct 09 05:26:36 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967800568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.967800568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_fifo_reset.2713382033 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 116487704301 ps |
| CPU time | 85.84 seconds |
| Started | Oct 09 05:29:50 AM UTC 24 |
| Finished | Oct 09 05:31:18 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713382033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2713382033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.2754773469 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 48500767922 ps |
| CPU time | 418.88 seconds |
| Started | Oct 09 05:30:11 AM UTC 24 |
| Finished | Oct 09 05:37:15 AM UTC 24 |
| Peak memory | 209608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754773469 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2754773469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/106.uart_fifo_reset.2632237185 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 54611126077 ps |
| CPU time | 29.06 seconds |
| Started | Oct 09 05:55:58 AM UTC 24 |
| Finished | Oct 09 05:56:28 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632237185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2632237185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/106.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_fifo_full.1172095383 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 168383450859 ps |
| CPU time | 238.33 seconds |
| Started | Oct 09 05:30:20 AM UTC 24 |
| Finished | Oct 09 05:34:22 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172095383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1172095383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/110.uart_fifo_reset.1289015679 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 60857987105 ps |
| CPU time | 35.86 seconds |
| Started | Oct 09 05:56:07 AM UTC 24 |
| Finished | Oct 09 05:56:44 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289015679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1289015679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/110.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/112.uart_fifo_reset.2076063638 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 94819072712 ps |
| CPU time | 18.21 seconds |
| Started | Oct 09 05:56:09 AM UTC 24 |
| Finished | Oct 09 05:56:29 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076063638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2076063638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/112.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/116.uart_fifo_reset.3591975164 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 48458293931 ps |
| CPU time | 38.63 seconds |
| Started | Oct 09 05:56:14 AM UTC 24 |
| Finished | Oct 09 05:56:54 AM UTC 24 |
| Peak memory | 209696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591975164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3591975164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/116.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.24730775 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 6334195336 ps |
| CPU time | 24.57 seconds |
| Started | Oct 09 05:31:05 AM UTC 24 |
| Finished | Oct 09 05:31:31 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24730775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.24730775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/136.uart_fifo_reset.2942245000 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 61027531229 ps |
| CPU time | 44.37 seconds |
| Started | Oct 09 05:56:50 AM UTC 24 |
| Finished | Oct 09 05:57:36 AM UTC 24 |
| Peak memory | 209820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942245000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2942245000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/136.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.2228368171 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 25556071107 ps |
| CPU time | 50.11 seconds |
| Started | Oct 09 05:31:58 AM UTC 24 |
| Finished | Oct 09 05:32:50 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228368171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2228368171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/142.uart_fifo_reset.1241464877 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 19540372888 ps |
| CPU time | 54.7 seconds |
| Started | Oct 09 05:56:56 AM UTC 24 |
| Finished | Oct 09 05:57:52 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241464877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1241464877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/142.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/170.uart_fifo_reset.585459298 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 18627815706 ps |
| CPU time | 40.88 seconds |
| Started | Oct 09 05:57:43 AM UTC 24 |
| Finished | Oct 09 05:58:26 AM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585459298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.585459298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/170.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/171.uart_fifo_reset.880269646 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 82475981008 ps |
| CPU time | 138.62 seconds |
| Started | Oct 09 05:57:44 AM UTC 24 |
| Finished | Oct 09 06:00:05 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880269646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.880269646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/171.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/198.uart_fifo_reset.267794537 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 80893626323 ps |
| CPU time | 123.26 seconds |
| Started | Oct 09 05:58:27 AM UTC 24 |
| Finished | Oct 09 06:00:32 AM UTC 24 |
| Peak memory | 203992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267794537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.267794537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/198.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/199.uart_fifo_reset.1108518738 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 37727674560 ps |
| CPU time | 27.7 seconds |
| Started | Oct 09 05:58:29 AM UTC 24 |
| Finished | Oct 09 05:58:58 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108518738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1108518738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/199.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3646519498 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 167137251592 ps |
| CPU time | 36.48 seconds |
| Started | Oct 09 05:58:33 AM UTC 24 |
| Finished | Oct 09 05:59:11 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646519498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3646519498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/202.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_fifo_reset.206227221 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 23405352378 ps |
| CPU time | 18.56 seconds |
| Started | Oct 09 05:35:32 AM UTC 24 |
| Finished | Oct 09 05:35:51 AM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206227221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.206227221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/211.uart_fifo_reset.2850098131 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 281455877289 ps |
| CPU time | 68.01 seconds |
| Started | Oct 09 05:58:50 AM UTC 24 |
| Finished | Oct 09 06:00:00 AM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850098131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2850098131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/211.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/213.uart_fifo_reset.4123871857 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 21191096090 ps |
| CPU time | 75.99 seconds |
| Started | Oct 09 05:58:57 AM UTC 24 |
| Finished | Oct 09 06:00:15 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123871857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.4123871857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/213.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/240.uart_fifo_reset.54147809 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 16696087548 ps |
| CPU time | 35.05 seconds |
| Started | Oct 09 06:00:01 AM UTC 24 |
| Finished | Oct 09 06:00:44 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54147809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.54147809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/240.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/275.uart_fifo_reset.2775233049 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 59465878875 ps |
| CPU time | 42.26 seconds |
| Started | Oct 09 06:01:01 AM UTC 24 |
| Finished | Oct 09 06:01:45 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775233049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2775233049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/275.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/278.uart_fifo_reset.2474785957 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 68103064242 ps |
| CPU time | 38.6 seconds |
| Started | Oct 09 06:01:08 AM UTC 24 |
| Finished | Oct 09 06:01:48 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474785957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2474785957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/278.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/71.uart_fifo_reset.2658365425 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 62472088607 ps |
| CPU time | 61.96 seconds |
| Started | Oct 09 05:53:49 AM UTC 24 |
| Finished | Oct 09 05:54:52 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658365425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2658365425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/71.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.372127845 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 31025538 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 07:13:39 AM UTC 24 |
| Finished | Oct 09 07:13:41 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372127845 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.372127845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.2055501646 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 663865910 ps |
| CPU time | 2.79 seconds |
| Started | Oct 09 07:13:39 AM UTC 24 |
| Finished | Oct 09 07:13:43 AM UTC 24 |
| Peak memory | 202252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055501646 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2055501646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.3822729340 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 16661862 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 07:13:39 AM UTC 24 |
| Finished | Oct 09 07:13:41 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822729340 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3822729340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3649887426 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 77371024 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 07:13:40 AM UTC 24 |
| Finished | Oct 09 07:13:43 AM UTC 24 |
| Peak memory | 203248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3649887426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r eset.3649887426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.1802581242 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 16727588 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 07:13:39 AM UTC 24 |
| Finished | Oct 09 07:13:41 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802581242 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1802581242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.2497432213 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 53100325 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 07:13:40 AM UTC 24 |
| Finished | Oct 09 07:13:42 AM UTC 24 |
| Peak memory | 200768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497432213 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.2497432213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2364559962 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 61919500 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 07:13:39 AM UTC 24 |
| Finished | Oct 09 07:13:42 AM UTC 24 |
| Peak memory | 200640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364559962 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2364559962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.1647036437 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 391496370 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 07:13:39 AM UTC 24 |
| Finished | Oct 09 07:13:41 AM UTC 24 |
| Peak memory | 201032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647036437 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1647036437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.1028800617 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 125665453 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 07:13:41 AM UTC 24 |
| Finished | Oct 09 07:13:44 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028800617 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1028800617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.1528961314 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 48319613 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 07:13:41 AM UTC 24 |
| Finished | Oct 09 07:13:43 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528961314 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1528961314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1387476192 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 29963646 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 07:13:42 AM UTC 24 |
| Finished | Oct 09 07:13:44 AM UTC 24 |
| Peak memory | 201200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1387476192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_r eset.1387476192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.1524897495 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 18061538 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 07:13:41 AM UTC 24 |
| Finished | Oct 09 07:13:43 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524897495 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1524897495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3145659478 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 22971991 ps |
| CPU time | 0.76 seconds |
| Started | Oct 09 07:13:41 AM UTC 24 |
| Finished | Oct 09 07:13:42 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145659478 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3145659478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.2231245621 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 158533244 ps |
| CPU time | 0.81 seconds |
| Started | Oct 09 07:13:41 AM UTC 24 |
| Finished | Oct 09 07:13:43 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231245621 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.2231245621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2197143344 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 189735953 ps |
| CPU time | 2.57 seconds |
| Started | Oct 09 07:13:41 AM UTC 24 |
| Finished | Oct 09 07:13:44 AM UTC 24 |
| Peak memory | 204028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197143344 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2197143344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.179615286 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 606510643 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 07:13:41 AM UTC 24 |
| Finished | Oct 09 07:13:43 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179615286 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.179615286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.978038204 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 55271148 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 07:13:54 AM UTC 24 |
| Finished | Oct 09 07:13:56 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=978038204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_r eset.978038204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1349774522 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 33687618 ps |
| CPU time | 0.53 seconds |
| Started | Oct 09 07:13:54 AM UTC 24 |
| Finished | Oct 09 07:13:55 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349774522 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1349774522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2923011515 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 15618126 ps |
| CPU time | 0.68 seconds |
| Started | Oct 09 07:13:53 AM UTC 24 |
| Finished | Oct 09 07:13:55 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923011515 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2923011515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2595801885 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 112736242 ps |
| CPU time | 0.78 seconds |
| Started | Oct 09 07:13:54 AM UTC 24 |
| Finished | Oct 09 07:13:55 AM UTC 24 |
| Peak memory | 201256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595801885 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.2595801885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.535169987 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 22976656 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 07:13:53 AM UTC 24 |
| Finished | Oct 09 07:13:56 AM UTC 24 |
| Peak memory | 203236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535169987 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.535169987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.4235787990 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 42787762 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 07:13:53 AM UTC 24 |
| Finished | Oct 09 07:13:56 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235787990 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.4235787990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3348455984 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 50835187 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:58 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3348455984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_ reset.3348455984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.1042892712 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 16496662 ps |
| CPU time | 0.68 seconds |
| Started | Oct 09 07:13:54 AM UTC 24 |
| Finished | Oct 09 07:13:56 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042892712 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1042892712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.62422108 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 13186490 ps |
| CPU time | 0.7 seconds |
| Started | Oct 09 07:13:54 AM UTC 24 |
| Finished | Oct 09 07:13:55 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62422108 -assert nopostproc +UVM_TESTNAME=uart_base_te st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.62422108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.2403427375 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 98363439 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:58 AM UTC 24 |
| Peak memory | 201256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403427375 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.2403427375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3048256051 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 36832368 ps |
| CPU time | 1.92 seconds |
| Started | Oct 09 07:13:54 AM UTC 24 |
| Finished | Oct 09 07:13:57 AM UTC 24 |
| Peak memory | 201156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048256051 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3048256051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1279110814 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 101766150 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 07:13:54 AM UTC 24 |
| Finished | Oct 09 07:13:56 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279110814 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1279110814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1662113251 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 113693991 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:58 AM UTC 24 |
| Peak memory | 201196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1662113251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_ reset.1662113251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.1572768400 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 21773745 ps |
| CPU time | 0.61 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:58 AM UTC 24 |
| Peak memory | 200808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572768400 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1572768400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2740884973 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 42913442 ps |
| CPU time | 0.73 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:58 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740884973 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2740884973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.3290516914 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 21539754 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:58 AM UTC 24 |
| Peak memory | 201196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290516914 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.3290516914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.993483230 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 106109697 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:59 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993483230 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.993483230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.392214041 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 136601360 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:59 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392214041 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.392214041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1905015112 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 34480278 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:59 AM UTC 24 |
| Peak memory | 201196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1905015112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_ reset.1905015112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.84116177 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 36500836 ps |
| CPU time | 0.72 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:58 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84116177 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.84116177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1002210819 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 40334585 ps |
| CPU time | 0.71 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:58 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002210819 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1002210819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2320239655 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 70559857 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:13:58 AM UTC 24 |
| Peak memory | 201256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320239655 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.2320239655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3797280563 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 208774870 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 07:13:56 AM UTC 24 |
| Finished | Oct 09 07:14:00 AM UTC 24 |
| Peak memory | 204416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797280563 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3797280563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.850824618 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 77127040 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 07:13:59 AM UTC 24 |
| Finished | Oct 09 07:14:01 AM UTC 24 |
| Peak memory | 201196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=850824618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_r eset.850824618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.1487955911 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 13913033 ps |
| CPU time | 0.7 seconds |
| Started | Oct 09 07:13:59 AM UTC 24 |
| Finished | Oct 09 07:14:01 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487955911 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1487955911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.882285217 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 108584457 ps |
| CPU time | 0.69 seconds |
| Started | Oct 09 07:13:59 AM UTC 24 |
| Finished | Oct 09 07:14:01 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882285217 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.882285217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.375010969 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 16508526 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 07:13:59 AM UTC 24 |
| Finished | Oct 09 07:14:01 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375010969 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.375010969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.3043107234 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 243823392 ps |
| CPU time | 1.86 seconds |
| Started | Oct 09 07:13:59 AM UTC 24 |
| Finished | Oct 09 07:14:02 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043107234 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3043107234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.618245665 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 41361899 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 07:13:59 AM UTC 24 |
| Finished | Oct 09 07:14:01 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618245665 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.618245665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1900949787 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 23874337 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:02 AM UTC 24 |
| Peak memory | 203244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1900949787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_ reset.1900949787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3162159240 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 38881437 ps |
| CPU time | 0.68 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:01 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162159240 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3162159240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.3856856405 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 61694379 ps |
| CPU time | 0.76 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:01 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856856405 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3856856405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.335091083 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 53901612 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:02 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335091083 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.335091083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.358423158 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 51794896 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:02 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358423158 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.358423158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1980072159 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 38651050 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:03 AM UTC 24 |
| Peak memory | 203244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1980072159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_ reset.1980072159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.1399536240 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 44223418 ps |
| CPU time | 0.73 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:02 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399536240 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1399536240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.1844988851 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 14431387 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:02 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844988851 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1844988851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1853094801 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 83546914 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:02 AM UTC 24 |
| Peak memory | 201256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853094801 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.1853094801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2428240699 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 25059845 ps |
| CPU time | 1.59 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:02 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428240699 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2428240699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.1959160922 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 54422158 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 07:14:00 AM UTC 24 |
| Finished | Oct 09 07:14:02 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959160922 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1959160922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3515186594 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 89364072 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 07:14:03 AM UTC 24 |
| Finished | Oct 09 07:14:05 AM UTC 24 |
| Peak memory | 201196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3515186594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_ reset.3515186594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2443425211 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 43204769 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 07:14:03 AM UTC 24 |
| Finished | Oct 09 07:14:05 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443425211 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2443425211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.2499170689 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 44185387 ps |
| CPU time | 0.74 seconds |
| Started | Oct 09 07:14:03 AM UTC 24 |
| Finished | Oct 09 07:14:05 AM UTC 24 |
| Peak memory | 201120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499170689 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2499170689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.720962059 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 13579387 ps |
| CPU time | 0.65 seconds |
| Started | Oct 09 07:14:03 AM UTC 24 |
| Finished | Oct 09 07:14:05 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720962059 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.720962059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3174407738 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 77946331 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 07:14:03 AM UTC 24 |
| Finished | Oct 09 07:14:05 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174407738 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3174407738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.4051928661 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 67864089 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 07:14:03 AM UTC 24 |
| Finished | Oct 09 07:14:05 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051928661 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4051928661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.576330865 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 44999324 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:14:04 AM UTC 24 |
| Finished | Oct 09 07:14:05 AM UTC 24 |
| Peak memory | 201196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=576330865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_r eset.576330865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.1290336941 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 19965384 ps |
| CPU time | 0.76 seconds |
| Started | Oct 09 07:14:03 AM UTC 24 |
| Finished | Oct 09 07:14:05 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290336941 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1290336941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3233708720 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 11430249 ps |
| CPU time | 0.72 seconds |
| Started | Oct 09 07:14:03 AM UTC 24 |
| Finished | Oct 09 07:14:05 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233708720 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3233708720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.2195723718 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 25457257 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 07:14:03 AM UTC 24 |
| Finished | Oct 09 07:14:05 AM UTC 24 |
| Peak memory | 201256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195723718 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.2195723718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.147230956 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 111252393 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 07:14:03 AM UTC 24 |
| Finished | Oct 09 07:14:06 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147230956 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.147230956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.1194909927 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 85278935 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 07:14:03 AM UTC 24 |
| Finished | Oct 09 07:14:06 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194909927 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1194909927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3877693270 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 27696970 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 07:14:04 AM UTC 24 |
| Finished | Oct 09 07:14:06 AM UTC 24 |
| Peak memory | 203244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3877693270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_ reset.3877693270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.4115402327 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 18633310 ps |
| CPU time | 0.65 seconds |
| Started | Oct 09 07:14:04 AM UTC 24 |
| Finished | Oct 09 07:14:05 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115402327 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.4115402327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.3825266948 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 13496167 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 07:14:04 AM UTC 24 |
| Finished | Oct 09 07:14:06 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825266948 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3825266948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2657411203 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 136600963 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 07:14:04 AM UTC 24 |
| Finished | Oct 09 07:14:06 AM UTC 24 |
| Peak memory | 201256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657411203 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.2657411203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.3183195552 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 41235011 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 07:14:04 AM UTC 24 |
| Finished | Oct 09 07:14:06 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183195552 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3183195552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.2687319792 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 60458699 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 07:14:04 AM UTC 24 |
| Finished | Oct 09 07:14:06 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687319792 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2687319792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.148375495 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 61459723 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 07:13:42 AM UTC 24 |
| Finished | Oct 09 07:13:44 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148375495 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.148375495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.739650959 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 1379383303 ps |
| CPU time | 1.67 seconds |
| Started | Oct 09 07:13:42 AM UTC 24 |
| Finished | Oct 09 07:13:45 AM UTC 24 |
| Peak memory | 201384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739650959 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.739650959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.3787294785 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 95347959 ps |
| CPU time | 0.79 seconds |
| Started | Oct 09 07:13:42 AM UTC 24 |
| Finished | Oct 09 07:13:44 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787294785 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3787294785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.132169626 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 42130709 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 07:13:44 AM UTC 24 |
| Finished | Oct 09 07:13:46 AM UTC 24 |
| Peak memory | 203184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=132169626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_re set.132169626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.2982753860 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 53152251 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 07:13:42 AM UTC 24 |
| Finished | Oct 09 07:13:44 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982753860 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2982753860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2500165271 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 15045010 ps |
| CPU time | 0.76 seconds |
| Started | Oct 09 07:13:42 AM UTC 24 |
| Finished | Oct 09 07:13:44 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500165271 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2500165271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.907925591 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 79425971 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 07:13:43 AM UTC 24 |
| Finished | Oct 09 07:13:45 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907925591 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.907925591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.2011887397 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 109001044 ps |
| CPU time | 2.58 seconds |
| Started | Oct 09 07:13:42 AM UTC 24 |
| Finished | Oct 09 07:13:46 AM UTC 24 |
| Peak memory | 202384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011887397 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2011887397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.278296206 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 81040286 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 07:13:42 AM UTC 24 |
| Finished | Oct 09 07:13:45 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278296206 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.278296206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.4268860208 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 11210484 ps |
| CPU time | 0.66 seconds |
| Started | Oct 09 07:14:07 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268860208 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.4268860208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1335078645 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 51119075 ps |
| CPU time | 0.64 seconds |
| Started | Oct 09 07:14:07 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335078645 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1335078645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1176433840 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 108339035 ps |
| CPU time | 0.64 seconds |
| Started | Oct 09 07:14:07 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176433840 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1176433840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.164213488 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 15216791 ps |
| CPU time | 0.53 seconds |
| Started | Oct 09 07:14:07 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164213488 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.164213488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3875763896 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 22081180 ps |
| CPU time | 0.73 seconds |
| Started | Oct 09 07:14:07 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875763896 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3875763896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.4176224404 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 15781715 ps |
| CPU time | 0.59 seconds |
| Started | Oct 09 07:14:07 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176224404 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.4176224404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3441324315 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 54700898 ps |
| CPU time | 0.62 seconds |
| Started | Oct 09 07:14:07 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441324315 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3441324315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.2827213401 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 53909575 ps |
| CPU time | 0.62 seconds |
| Started | Oct 09 07:14:07 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827213401 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2827213401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.293298267 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 32218989 ps |
| CPU time | 0.68 seconds |
| Started | Oct 09 07:14:08 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293298267 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.293298267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2376706586 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 12981876 ps |
| CPU time | 0.69 seconds |
| Started | Oct 09 07:14:08 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376706586 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2376706586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2121456134 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 21024174 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 07:13:44 AM UTC 24 |
| Finished | Oct 09 07:13:46 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121456134 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2121456134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2281041107 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 130882986 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 07:13:44 AM UTC 24 |
| Finished | Oct 09 07:13:47 AM UTC 24 |
| Peak memory | 201396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281041107 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2281041107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.3577435237 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 51164421 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:13:44 AM UTC 24 |
| Finished | Oct 09 07:13:46 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577435237 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3577435237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3817058111 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 28258391 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 07:13:45 AM UTC 24 |
| Finished | Oct 09 07:13:47 AM UTC 24 |
| Peak memory | 201200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3817058111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r eset.3817058111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2960020476 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 33099872 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 07:13:44 AM UTC 24 |
| Finished | Oct 09 07:13:46 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960020476 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2960020476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.4288650629 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 52170153 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 07:13:44 AM UTC 24 |
| Finished | Oct 09 07:13:45 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288650629 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.4288650629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.2245058128 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 54896282 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 07:13:45 AM UTC 24 |
| Finished | Oct 09 07:13:47 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245058128 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.2245058128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.3406195931 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 107759605 ps |
| CPU time | 2.52 seconds |
| Started | Oct 09 07:13:44 AM UTC 24 |
| Finished | Oct 09 07:13:47 AM UTC 24 |
| Peak memory | 202384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406195931 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3406195931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1513581735 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 17786280 ps |
| CPU time | 0.65 seconds |
| Started | Oct 09 07:14:08 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513581735 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1513581735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.912877299 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 16246064 ps |
| CPU time | 0.79 seconds |
| Started | Oct 09 07:14:08 AM UTC 24 |
| Finished | Oct 09 07:14:10 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912877299 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.912877299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2252942109 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 14611252 ps |
| CPU time | 0.67 seconds |
| Started | Oct 09 07:14:08 AM UTC 24 |
| Finished | Oct 09 07:14:10 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252942109 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2252942109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.793714942 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 28439963 ps |
| CPU time | 0.68 seconds |
| Started | Oct 09 07:14:08 AM UTC 24 |
| Finished | Oct 09 07:14:10 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793714942 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.793714942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.178419230 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 39179265 ps |
| CPU time | 0.63 seconds |
| Started | Oct 09 07:14:08 AM UTC 24 |
| Finished | Oct 09 07:14:09 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178419230 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.178419230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.3413112079 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 13624655 ps |
| CPU time | 0.63 seconds |
| Started | Oct 09 07:14:08 AM UTC 24 |
| Finished | Oct 09 07:14:10 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413112079 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3413112079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.246014118 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 42416260 ps |
| CPU time | 0.58 seconds |
| Started | Oct 09 07:14:08 AM UTC 24 |
| Finished | Oct 09 07:14:10 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246014118 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.246014118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.3167060495 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 13581812 ps |
| CPU time | 0.57 seconds |
| Started | Oct 09 07:14:08 AM UTC 24 |
| Finished | Oct 09 07:14:10 AM UTC 24 |
| Peak memory | 201120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167060495 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3167060495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3538143239 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 14306332 ps |
| CPU time | 0.56 seconds |
| Started | Oct 09 07:14:13 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538143239 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3538143239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.4057174314 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 26684169 ps |
| CPU time | 0.62 seconds |
| Started | Oct 09 07:14:13 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057174314 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4057174314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.1620836765 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 41670859 ps |
| CPU time | 0.79 seconds |
| Started | Oct 09 07:13:46 AM UTC 24 |
| Finished | Oct 09 07:13:47 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620836765 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1620836765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3519067098 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 218902700 ps |
| CPU time | 3.04 seconds |
| Started | Oct 09 07:13:46 AM UTC 24 |
| Finished | Oct 09 07:13:50 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519067098 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3519067098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.711308095 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 14361323 ps |
| CPU time | 0.78 seconds |
| Started | Oct 09 07:13:45 AM UTC 24 |
| Finished | Oct 09 07:13:47 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711308095 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.711308095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.111789418 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 72916919 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 07:13:47 AM UTC 24 |
| Finished | Oct 09 07:13:49 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=111789418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_re set.111789418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.163641548 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 36648163 ps |
| CPU time | 0.78 seconds |
| Started | Oct 09 07:13:45 AM UTC 24 |
| Finished | Oct 09 07:13:47 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163641548 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.163641548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.2657682192 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 37977201 ps |
| CPU time | 0.75 seconds |
| Started | Oct 09 07:13:45 AM UTC 24 |
| Finished | Oct 09 07:13:47 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657682192 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2657682192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3101684180 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 69298218 ps |
| CPU time | 0.91 seconds |
| Started | Oct 09 07:13:47 AM UTC 24 |
| Finished | Oct 09 07:13:49 AM UTC 24 |
| Peak memory | 201004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101684180 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.3101684180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3067192398 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 497915636 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 07:13:45 AM UTC 24 |
| Finished | Oct 09 07:13:49 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067192398 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3067192398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.3148741233 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 97230304 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 07:13:45 AM UTC 24 |
| Finished | Oct 09 07:13:48 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148741233 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3148741233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1063485828 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 22307164 ps |
| CPU time | 0.66 seconds |
| Started | Oct 09 07:14:13 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063485828 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1063485828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3952661115 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 11788102 ps |
| CPU time | 0.58 seconds |
| Started | Oct 09 07:14:13 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952661115 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3952661115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1549222635 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 15084314 ps |
| CPU time | 0.65 seconds |
| Started | Oct 09 07:14:13 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549222635 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1549222635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.3848663203 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 15597686 ps |
| CPU time | 0.66 seconds |
| Started | Oct 09 07:14:13 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848663203 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3848663203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1852202483 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 48887028 ps |
| CPU time | 0.6 seconds |
| Started | Oct 09 07:14:13 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852202483 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1852202483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.367099859 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 17865006 ps |
| CPU time | 0.68 seconds |
| Started | Oct 09 07:14:13 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367099859 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.367099859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.3735285720 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 23540358 ps |
| CPU time | 0.79 seconds |
| Started | Oct 09 07:14:14 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735285720 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3735285720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.3893189322 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 12736932 ps |
| CPU time | 0.67 seconds |
| Started | Oct 09 07:14:14 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893189322 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3893189322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.927363048 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 42282184 ps |
| CPU time | 0.67 seconds |
| Started | Oct 09 07:14:14 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927363048 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.927363048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.1331290019 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 14409570 ps |
| CPU time | 0.74 seconds |
| Started | Oct 09 07:14:14 AM UTC 24 |
| Finished | Oct 09 07:14:15 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331290019 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1331290019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3629090173 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 69258266 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 07:13:47 AM UTC 24 |
| Finished | Oct 09 07:13:49 AM UTC 24 |
| Peak memory | 201200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3629090173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r eset.3629090173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2817883660 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 31611701 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:13:47 AM UTC 24 |
| Finished | Oct 09 07:13:49 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817883660 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2817883660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3493336124 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 32543544 ps |
| CPU time | 0.74 seconds |
| Started | Oct 09 07:13:47 AM UTC 24 |
| Finished | Oct 09 07:13:49 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493336124 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3493336124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.2663463818 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 29773583 ps |
| CPU time | 0.73 seconds |
| Started | Oct 09 07:13:47 AM UTC 24 |
| Finished | Oct 09 07:13:49 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663463818 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.2663463818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.162790928 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 185664064 ps |
| CPU time | 2.19 seconds |
| Started | Oct 09 07:13:47 AM UTC 24 |
| Finished | Oct 09 07:13:50 AM UTC 24 |
| Peak memory | 204440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162790928 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.162790928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3357229938 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 125739521 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 07:13:47 AM UTC 24 |
| Finished | Oct 09 07:13:49 AM UTC 24 |
| Peak memory | 200948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357229938 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3357229938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.96229193 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 57848891 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 07:13:49 AM UTC 24 |
| Finished | Oct 09 07:13:51 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=96229193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.96229193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.453961434 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 10690162 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 07:13:49 AM UTC 24 |
| Finished | Oct 09 07:13:51 AM UTC 24 |
| Peak memory | 201064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453961434 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.453961434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.3180779742 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 19691448 ps |
| CPU time | 0.69 seconds |
| Started | Oct 09 07:13:47 AM UTC 24 |
| Finished | Oct 09 07:13:49 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180779742 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3180779742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.1889572024 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 28377679 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 07:13:49 AM UTC 24 |
| Finished | Oct 09 07:13:51 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889572024 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.1889572024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.1862668011 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 626653211 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 07:13:47 AM UTC 24 |
| Finished | Oct 09 07:13:50 AM UTC 24 |
| Peak memory | 201188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862668011 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1862668011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3765845724 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 73377877 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 07:13:47 AM UTC 24 |
| Finished | Oct 09 07:13:50 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765845724 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3765845724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.794281358 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 95171052 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 07:13:51 AM UTC 24 |
| Finished | Oct 09 07:13:53 AM UTC 24 |
| Peak memory | 201136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=794281358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_re set.794281358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.2480017196 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 13907691 ps |
| CPU time | 0.87 seconds |
| Started | Oct 09 07:13:49 AM UTC 24 |
| Finished | Oct 09 07:13:51 AM UTC 24 |
| Peak memory | 201132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480017196 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2480017196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.74499361 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 53047949 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 07:13:49 AM UTC 24 |
| Finished | Oct 09 07:13:51 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74499361 -assert nopostproc +UVM_TESTNAME=uart_base_te st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.74499361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.3404658978 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 101629892 ps |
| CPU time | 0.64 seconds |
| Started | Oct 09 07:13:49 AM UTC 24 |
| Finished | Oct 09 07:13:51 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404658978 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.3404658978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.1272289333 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 88984974 ps |
| CPU time | 2.61 seconds |
| Started | Oct 09 07:13:49 AM UTC 24 |
| Finished | Oct 09 07:13:53 AM UTC 24 |
| Peak memory | 204432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272289333 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1272289333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.1880513386 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 497295086 ps |
| CPU time | 1.86 seconds |
| Started | Oct 09 07:13:49 AM UTC 24 |
| Finished | Oct 09 07:13:52 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880513386 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1880513386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1277226801 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 69183878 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 07:13:51 AM UTC 24 |
| Finished | Oct 09 07:13:53 AM UTC 24 |
| Peak memory | 201200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1277226801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r eset.1277226801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.70745753 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 23473965 ps |
| CPU time | 0.81 seconds |
| Started | Oct 09 07:13:51 AM UTC 24 |
| Finished | Oct 09 07:13:53 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70745753 -assert nopostproc +UVM_TESTNAME=uart_base _test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.70745753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.1015848698 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 35588538 ps |
| CPU time | 0.51 seconds |
| Started | Oct 09 07:13:51 AM UTC 24 |
| Finished | Oct 09 07:13:53 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015848698 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1015848698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.3279610418 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 36945444 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 07:13:51 AM UTC 24 |
| Finished | Oct 09 07:13:53 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279610418 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.3279610418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.482288065 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 71258410 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 07:13:51 AM UTC 24 |
| Finished | Oct 09 07:13:55 AM UTC 24 |
| Peak memory | 202356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482288065 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.482288065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.2749497428 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 54759161 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 07:13:51 AM UTC 24 |
| Finished | Oct 09 07:13:53 AM UTC 24 |
| Peak memory | 201108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749497428 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2749497428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3388296549 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 175306093 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 07:13:52 AM UTC 24 |
| Finished | Oct 09 07:13:54 AM UTC 24 |
| Peak memory | 203248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3388296549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r eset.3388296549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.2975528470 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 128775832 ps |
| CPU time | 0.76 seconds |
| Started | Oct 09 07:13:52 AM UTC 24 |
| Finished | Oct 09 07:13:53 AM UTC 24 |
| Peak memory | 201192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975528470 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2975528470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.1923760208 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 13855792 ps |
| CPU time | 0.79 seconds |
| Started | Oct 09 07:13:51 AM UTC 24 |
| Finished | Oct 09 07:13:53 AM UTC 24 |
| Peak memory | 201124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923760208 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1923760208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.3999511835 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 16945801 ps |
| CPU time | 0.69 seconds |
| Started | Oct 09 07:13:52 AM UTC 24 |
| Finished | Oct 09 07:13:53 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999511835 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.3999511835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.448373795 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 73376750 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 07:13:51 AM UTC 24 |
| Finished | Oct 09 07:13:53 AM UTC 24 |
| Peak memory | 201184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448373795 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.448373795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.4076425760 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 167993665 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 07:13:51 AM UTC 24 |
| Finished | Oct 09 07:13:54 AM UTC 24 |
| Peak memory | 201128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076425760 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.4076425760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.3167279224 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 84965450858 ps |
| CPU time | 223.22 seconds |
| Started | Oct 09 05:26:10 AM UTC 24 |
| Finished | Oct 09 05:29:56 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167279224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3167279224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.2026968292 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 73381407888 ps |
| CPU time | 409.18 seconds |
| Started | Oct 09 05:26:15 AM UTC 24 |
| Finished | Oct 09 05:33:10 AM UTC 24 |
| Peak memory | 213144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026968292 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2026968292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_rx_oversample.2138744565 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3007157712 ps |
| CPU time | 10.66 seconds |
| Started | Oct 09 05:26:11 AM UTC 24 |
| Finished | Oct 09 05:26:23 AM UTC 24 |
| Peak memory | 204076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138744565 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2138744565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.2468559536 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3868193688 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 05:26:12 AM UTC 24 |
| Finished | Oct 09 05:26:15 AM UTC 24 |
| Peak memory | 203280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468559536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2468559536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_smoke.4175880677 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 128703199 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 05:26:08 AM UTC 24 |
| Finished | Oct 09 05:26:11 AM UTC 24 |
| Peak memory | 203224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175880677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.uart_smoke.4175880677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.2397512834 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 662608463 ps |
| CPU time | 4.11 seconds |
| Started | Oct 09 05:26:14 AM UTC 24 |
| Finished | Oct 09 05:26:19 AM UTC 24 |
| Peak memory | 208976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397512834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2397512834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_tx_rx.56248091 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8930781968 ps |
| CPU time | 9.15 seconds |
| Started | Oct 09 05:26:08 AM UTC 24 |
| Finished | Oct 09 05:26:19 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56248091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.56248091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/0.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_alert_test.1888104734 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 24465973 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:26:33 AM UTC 24 |
| Finished | Oct 09 05:26:35 AM UTC 24 |
| Peak memory | 203408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888104734 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1888104734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_fifo_reset.1467976521 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 70352770244 ps |
| CPU time | 172.47 seconds |
| Started | Oct 09 05:26:21 AM UTC 24 |
| Finished | Oct 09 05:29:16 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467976521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1467976521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_intr.2955626495 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 57168231456 ps |
| CPU time | 10.9 seconds |
| Started | Oct 09 05:26:24 AM UTC 24 |
| Finished | Oct 09 05:26:36 AM UTC 24 |
| Peak memory | 205840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955626495 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2955626495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.3836392832 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 328359341835 ps |
| CPU time | 593.83 seconds |
| Started | Oct 09 05:26:31 AM UTC 24 |
| Finished | Oct 09 05:36:32 AM UTC 24 |
| Peak memory | 209436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836392832 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3836392832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_loopback.2139075300 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6221080313 ps |
| CPU time | 25.28 seconds |
| Started | Oct 09 05:26:29 AM UTC 24 |
| Finished | Oct 09 05:26:56 AM UTC 24 |
| Peak memory | 204336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139075300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2139075300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_perf.4242443679 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 5818747790 ps |
| CPU time | 348.22 seconds |
| Started | Oct 09 05:26:31 AM UTC 24 |
| Finished | Oct 09 05:32:24 AM UTC 24 |
| Peak memory | 205512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242443679 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.4242443679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_rx_oversample.4171357610 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1271821742 ps |
| CPU time | 6.55 seconds |
| Started | Oct 09 05:26:22 AM UTC 24 |
| Finished | Oct 09 05:26:29 AM UTC 24 |
| Peak memory | 204268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171357610 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.4171357610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.3721771728 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 136882917884 ps |
| CPU time | 209.12 seconds |
| Started | Oct 09 05:26:27 AM UTC 24 |
| Finished | Oct 09 05:30:00 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721771728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3721771728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.2006215348 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2615193202 ps |
| CPU time | 6.05 seconds |
| Started | Oct 09 05:26:25 AM UTC 24 |
| Finished | Oct 09 05:26:32 AM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006215348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2006215348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_sec_cm.661359655 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 62679116 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 05:26:33 AM UTC 24 |
| Finished | Oct 09 05:26:35 AM UTC 24 |
| Peak memory | 235556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661359655 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.661359655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_smoke.1030982096 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 451993352 ps |
| CPU time | 3.83 seconds |
| Started | Oct 09 05:26:19 AM UTC 24 |
| Finished | Oct 09 05:26:24 AM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030982096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1030982096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_stress_all.3963052296 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 647501419282 ps |
| CPU time | 2207.77 seconds |
| Started | Oct 09 05:26:32 AM UTC 24 |
| Finished | Oct 09 06:03:44 AM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963052296 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3963052296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.3470722436 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5045686791 ps |
| CPU time | 171.61 seconds |
| Started | Oct 09 05:26:32 AM UTC 24 |
| Finished | Oct 09 05:29:26 AM UTC 24 |
| Peak memory | 218472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3470722436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_ with_rand_reset.3470722436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.3336594126 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6783150275 ps |
| CPU time | 31.17 seconds |
| Started | Oct 09 05:26:27 AM UTC 24 |
| Finished | Oct 09 05:27:00 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336594126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3336594126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_tx_rx.917284360 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 5917931269 ps |
| CPU time | 22.96 seconds |
| Started | Oct 09 05:26:19 AM UTC 24 |
| Finished | Oct 09 05:26:44 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917284360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.917284360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/1.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_alert_test.1470967084 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 47187341 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 05:30:14 AM UTC 24 |
| Finished | Oct 09 05:30:16 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470967084 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1470967084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.2468417943 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 162119142211 ps |
| CPU time | 89.67 seconds |
| Started | Oct 09 05:29:48 AM UTC 24 |
| Finished | Oct 09 05:31:20 AM UTC 24 |
| Peak memory | 209292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468417943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2468417943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_intr.696823433 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 16078341888 ps |
| CPU time | 8.67 seconds |
| Started | Oct 09 05:29:56 AM UTC 24 |
| Finished | Oct 09 05:30:06 AM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696823433 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.696823433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_loopback.1278731485 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 7483852468 ps |
| CPU time | 11.41 seconds |
| Started | Oct 09 05:30:10 AM UTC 24 |
| Finished | Oct 09 05:30:23 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278731485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1278731485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_noise_filter.830879552 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 106555851356 ps |
| CPU time | 42.51 seconds |
| Started | Oct 09 05:29:57 AM UTC 24 |
| Finished | Oct 09 05:30:42 AM UTC 24 |
| Peak memory | 209772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830879552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.830879552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_perf.4249523089 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 15069344242 ps |
| CPU time | 361.72 seconds |
| Started | Oct 09 05:30:11 AM UTC 24 |
| Finished | Oct 09 05:36:17 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249523089 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4249523089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_rx_oversample.2691667117 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 6103604019 ps |
| CPU time | 54.24 seconds |
| Started | Oct 09 05:29:51 AM UTC 24 |
| Finished | Oct 09 05:30:47 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691667117 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2691667117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.1394439813 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 49822552241 ps |
| CPU time | 102.49 seconds |
| Started | Oct 09 05:29:58 AM UTC 24 |
| Finished | Oct 09 05:31:42 AM UTC 24 |
| Peak memory | 204116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394439813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1394439813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_smoke.3068219846 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 629173597 ps |
| CPU time | 2.64 seconds |
| Started | Oct 09 05:29:46 AM UTC 24 |
| Finished | Oct 09 05:29:50 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068219846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3068219846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_stress_all.2697536060 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 17897344584 ps |
| CPU time | 36.9 seconds |
| Started | Oct 09 05:30:13 AM UTC 24 |
| Finished | Oct 09 05:30:51 AM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697536060 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2697536060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.303547904 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 6494337468 ps |
| CPU time | 17.08 seconds |
| Started | Oct 09 05:30:07 AM UTC 24 |
| Finished | Oct 09 05:30:25 AM UTC 24 |
| Peak memory | 204076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303547904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.303547904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_tx_rx.1678671012 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 72130809999 ps |
| CPU time | 58.33 seconds |
| Started | Oct 09 05:29:47 AM UTC 24 |
| Finished | Oct 09 05:30:47 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678671012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1678671012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/10.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/100.uart_fifo_reset.3446090197 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 84911022893 ps |
| CPU time | 116.12 seconds |
| Started | Oct 09 05:55:40 AM UTC 24 |
| Finished | Oct 09 05:57:39 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446090197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3446090197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/100.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/101.uart_fifo_reset.4185997030 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 14886262125 ps |
| CPU time | 29.62 seconds |
| Started | Oct 09 05:55:41 AM UTC 24 |
| Finished | Oct 09 05:56:12 AM UTC 24 |
| Peak memory | 208480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185997030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.4185997030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/101.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/102.uart_fifo_reset.3284825350 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 125735799489 ps |
| CPU time | 508.15 seconds |
| Started | Oct 09 05:55:42 AM UTC 24 |
| Finished | Oct 09 06:04:17 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284825350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3284825350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/102.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/103.uart_fifo_reset.1116746236 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 21211316439 ps |
| CPU time | 24.13 seconds |
| Started | Oct 09 05:55:51 AM UTC 24 |
| Finished | Oct 09 05:56:16 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116746236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1116746236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/103.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/104.uart_fifo_reset.3309480342 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 86704652642 ps |
| CPU time | 154.86 seconds |
| Started | Oct 09 05:55:55 AM UTC 24 |
| Finished | Oct 09 05:58:33 AM UTC 24 |
| Peak memory | 203988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309480342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3309480342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/104.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/105.uart_fifo_reset.1655161696 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 75978312420 ps |
| CPU time | 41.11 seconds |
| Started | Oct 09 05:55:55 AM UTC 24 |
| Finished | Oct 09 05:56:38 AM UTC 24 |
| Peak memory | 209460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655161696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1655161696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/105.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/107.uart_fifo_reset.2564691268 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 28897941637 ps |
| CPU time | 49.9 seconds |
| Started | Oct 09 05:56:01 AM UTC 24 |
| Finished | Oct 09 05:56:52 AM UTC 24 |
| Peak memory | 209764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564691268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2564691268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/107.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/108.uart_fifo_reset.1454842840 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 102320249762 ps |
| CPU time | 119.24 seconds |
| Started | Oct 09 05:56:03 AM UTC 24 |
| Finished | Oct 09 05:58:05 AM UTC 24 |
| Peak memory | 209268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454842840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1454842840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/108.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_alert_test.102828827 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 31869714 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:30:43 AM UTC 24 |
| Finished | Oct 09 05:30:45 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102828827 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.102828827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.1334091190 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 18493712856 ps |
| CPU time | 40.72 seconds |
| Started | Oct 09 05:30:22 AM UTC 24 |
| Finished | Oct 09 05:31:04 AM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334091190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1334091190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_fifo_reset.1739390958 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 85316867598 ps |
| CPU time | 84.85 seconds |
| Started | Oct 09 05:30:23 AM UTC 24 |
| Finished | Oct 09 05:31:50 AM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739390958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1739390958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_intr.1211261025 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 22967396990 ps |
| CPU time | 20.17 seconds |
| Started | Oct 09 05:30:26 AM UTC 24 |
| Finished | Oct 09 05:30:47 AM UTC 24 |
| Peak memory | 204200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211261025 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1211261025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.1066274234 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 152041087501 ps |
| CPU time | 1014.48 seconds |
| Started | Oct 09 05:30:36 AM UTC 24 |
| Finished | Oct 09 05:47:43 AM UTC 24 |
| Peak memory | 207444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066274234 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1066274234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_loopback.268165742 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1779388682 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 05:30:30 AM UTC 24 |
| Finished | Oct 09 05:30:35 AM UTC 24 |
| Peak memory | 205544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268165742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 11.uart_loopback.268165742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_noise_filter.2617147460 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 108366904488 ps |
| CPU time | 198.99 seconds |
| Started | Oct 09 05:30:26 AM UTC 24 |
| Finished | Oct 09 05:33:48 AM UTC 24 |
| Peak memory | 209716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617147460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2617147460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_perf.3526109573 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 6005305768 ps |
| CPU time | 92.74 seconds |
| Started | Oct 09 05:30:32 AM UTC 24 |
| Finished | Oct 09 05:32:07 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526109573 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3526109573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_rx_oversample.923789984 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 5399638304 ps |
| CPU time | 69.51 seconds |
| Started | Oct 09 05:30:24 AM UTC 24 |
| Finished | Oct 09 05:31:35 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923789984 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.923789984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.1474105248 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 6842781935 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 05:30:26 AM UTC 24 |
| Finished | Oct 09 05:30:29 AM UTC 24 |
| Peak memory | 203340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474105248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1474105248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_smoke.1088079446 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 685867111 ps |
| CPU time | 2.26 seconds |
| Started | Oct 09 05:30:17 AM UTC 24 |
| Finished | Oct 09 05:30:21 AM UTC 24 |
| Peak memory | 203944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088079446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1088079446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_stress_all.3332495470 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 53055947363 ps |
| CPU time | 43.65 seconds |
| Started | Oct 09 05:30:42 AM UTC 24 |
| Finished | Oct 09 05:31:27 AM UTC 24 |
| Peak memory | 209756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332495470 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3332495470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.3737843325 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1217965192 ps |
| CPU time | 15.58 seconds |
| Started | Oct 09 05:30:36 AM UTC 24 |
| Finished | Oct 09 05:30:53 AM UTC 24 |
| Peak memory | 224788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3737843325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all _with_rand_reset.3737843325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.2209389902 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 7737428005 ps |
| CPU time | 17.38 seconds |
| Started | Oct 09 05:30:30 AM UTC 24 |
| Finished | Oct 09 05:30:49 AM UTC 24 |
| Peak memory | 203920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209389902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2209389902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_tx_rx.1089250796 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 37283055120 ps |
| CPU time | 139.48 seconds |
| Started | Oct 09 05:30:20 AM UTC 24 |
| Finished | Oct 09 05:32:43 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089250796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1089250796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/11.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/111.uart_fifo_reset.318581357 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 24865913681 ps |
| CPU time | 80.29 seconds |
| Started | Oct 09 05:56:07 AM UTC 24 |
| Finished | Oct 09 05:57:29 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318581357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.318581357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/111.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/113.uart_fifo_reset.1380326216 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 165683123045 ps |
| CPU time | 174.5 seconds |
| Started | Oct 09 05:56:11 AM UTC 24 |
| Finished | Oct 09 05:59:09 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380326216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1380326216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/113.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/114.uart_fifo_reset.2667411395 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 134492900105 ps |
| CPU time | 89.68 seconds |
| Started | Oct 09 05:56:12 AM UTC 24 |
| Finished | Oct 09 05:57:44 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667411395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2667411395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/114.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/115.uart_fifo_reset.2525324900 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 38050996610 ps |
| CPU time | 25.42 seconds |
| Started | Oct 09 05:56:13 AM UTC 24 |
| Finished | Oct 09 05:56:39 AM UTC 24 |
| Peak memory | 208400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525324900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2525324900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/115.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/117.uart_fifo_reset.80788831 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 47495364291 ps |
| CPU time | 23.2 seconds |
| Started | Oct 09 05:56:16 AM UTC 24 |
| Finished | Oct 09 05:56:41 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80788831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.80788831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/117.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/118.uart_fifo_reset.4001238424 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 38175871907 ps |
| CPU time | 64 seconds |
| Started | Oct 09 05:56:17 AM UTC 24 |
| Finished | Oct 09 05:57:23 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001238424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4001238424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/118.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/119.uart_fifo_reset.3529385218 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 19149630817 ps |
| CPU time | 40.52 seconds |
| Started | Oct 09 05:56:17 AM UTC 24 |
| Finished | Oct 09 05:56:59 AM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529385218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3529385218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/119.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_alert_test.4017522053 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 39433854 ps |
| CPU time | 0.8 seconds |
| Started | Oct 09 05:31:20 AM UTC 24 |
| Finished | Oct 09 05:31:22 AM UTC 24 |
| Peak memory | 203464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017522053 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4017522053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_fifo_full.2706630818 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 114042600110 ps |
| CPU time | 227.83 seconds |
| Started | Oct 09 05:30:48 AM UTC 24 |
| Finished | Oct 09 05:34:40 AM UTC 24 |
| Peak memory | 209740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706630818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2706630818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_fifo_reset.1239725397 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 58454543240 ps |
| CPU time | 32.61 seconds |
| Started | Oct 09 05:30:50 AM UTC 24 |
| Finished | Oct 09 05:31:24 AM UTC 24 |
| Peak memory | 209756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239725397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1239725397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_intr.2845228644 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1831028597 ps |
| CPU time | 2.81 seconds |
| Started | Oct 09 05:30:52 AM UTC 24 |
| Finished | Oct 09 05:30:57 AM UTC 24 |
| Peak memory | 203664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845228644 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2845228644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.3746863093 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 63466375188 ps |
| CPU time | 391.24 seconds |
| Started | Oct 09 05:31:11 AM UTC 24 |
| Finished | Oct 09 05:37:47 AM UTC 24 |
| Peak memory | 206440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746863093 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3746863093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_loopback.3886788300 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 7485260807 ps |
| CPU time | 13.55 seconds |
| Started | Oct 09 05:31:05 AM UTC 24 |
| Finished | Oct 09 05:31:20 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886788300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3886788300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_noise_filter.4128030969 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 67980843171 ps |
| CPU time | 40.16 seconds |
| Started | Oct 09 05:30:54 AM UTC 24 |
| Finished | Oct 09 05:31:37 AM UTC 24 |
| Peak memory | 209700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128030969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.4128030969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_perf.2452643496 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 9993463362 ps |
| CPU time | 475.02 seconds |
| Started | Oct 09 05:31:05 AM UTC 24 |
| Finished | Oct 09 05:39:07 AM UTC 24 |
| Peak memory | 204400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452643496 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2452643496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_rx_oversample.2629205626 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 5932886895 ps |
| CPU time | 34.18 seconds |
| Started | Oct 09 05:30:50 AM UTC 24 |
| Finished | Oct 09 05:31:26 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629205626 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2629205626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.183706766 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3750624956 ps |
| CPU time | 5.67 seconds |
| Started | Oct 09 05:30:57 AM UTC 24 |
| Finished | Oct 09 05:31:04 AM UTC 24 |
| Peak memory | 204124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183706766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.183706766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_smoke.2028756450 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 280939644 ps |
| CPU time | 1.97 seconds |
| Started | Oct 09 05:30:46 AM UTC 24 |
| Finished | Oct 09 05:30:49 AM UTC 24 |
| Peak memory | 203360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028756450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2028756450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_tx_rx.47091315 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 54146137441 ps |
| CPU time | 37.26 seconds |
| Started | Oct 09 05:30:48 AM UTC 24 |
| Finished | Oct 09 05:31:27 AM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47091315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.47091315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/120.uart_fifo_reset.1627668466 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 211107931939 ps |
| CPU time | 357.14 seconds |
| Started | Oct 09 05:56:18 AM UTC 24 |
| Finished | Oct 09 06:02:21 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627668466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1627668466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/120.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/121.uart_fifo_reset.371037709 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 85874054707 ps |
| CPU time | 68.91 seconds |
| Started | Oct 09 05:56:20 AM UTC 24 |
| Finished | Oct 09 05:57:31 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371037709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.371037709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/121.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/122.uart_fifo_reset.1108177165 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 143966500492 ps |
| CPU time | 25.09 seconds |
| Started | Oct 09 05:56:23 AM UTC 24 |
| Finished | Oct 09 05:56:50 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108177165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1108177165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/122.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/123.uart_fifo_reset.4072986305 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 246008067324 ps |
| CPU time | 34.84 seconds |
| Started | Oct 09 05:56:28 AM UTC 24 |
| Finished | Oct 09 05:57:05 AM UTC 24 |
| Peak memory | 203928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072986305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.4072986305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/123.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/124.uart_fifo_reset.1092775115 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 172641712908 ps |
| CPU time | 51.41 seconds |
| Started | Oct 09 05:56:28 AM UTC 24 |
| Finished | Oct 09 05:57:21 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092775115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1092775115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/124.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/126.uart_fifo_reset.3669054871 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 164882599700 ps |
| CPU time | 95.16 seconds |
| Started | Oct 09 05:56:30 AM UTC 24 |
| Finished | Oct 09 05:58:07 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669054871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3669054871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/126.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/127.uart_fifo_reset.3705962407 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 81078256161 ps |
| CPU time | 52.31 seconds |
| Started | Oct 09 05:56:30 AM UTC 24 |
| Finished | Oct 09 05:57:24 AM UTC 24 |
| Peak memory | 209540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705962407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3705962407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/127.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/128.uart_fifo_reset.3334095102 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 16695155072 ps |
| CPU time | 23.58 seconds |
| Started | Oct 09 05:56:31 AM UTC 24 |
| Finished | Oct 09 05:56:55 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334095102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3334095102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/128.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/129.uart_fifo_reset.1091206903 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 36133286790 ps |
| CPU time | 78.94 seconds |
| Started | Oct 09 05:56:37 AM UTC 24 |
| Finished | Oct 09 05:57:58 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091206903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1091206903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/129.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_alert_test.1129154166 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 20828145 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 05:31:43 AM UTC 24 |
| Finished | Oct 09 05:31:44 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129154166 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1129154166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_fifo_full.3980370380 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 39818550919 ps |
| CPU time | 79.51 seconds |
| Started | Oct 09 05:31:21 AM UTC 24 |
| Finished | Oct 09 05:32:43 AM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980370380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3980370380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_fifo_reset.2918536582 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 32027810722 ps |
| CPU time | 19.96 seconds |
| Started | Oct 09 05:31:25 AM UTC 24 |
| Finished | Oct 09 05:31:46 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918536582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2918536582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.1899931565 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 107460116704 ps |
| CPU time | 567.5 seconds |
| Started | Oct 09 05:31:38 AM UTC 24 |
| Finished | Oct 09 05:41:13 AM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899931565 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1899931565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_loopback.3656754410 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 9499610407 ps |
| CPU time | 8.46 seconds |
| Started | Oct 09 05:31:34 AM UTC 24 |
| Finished | Oct 09 05:31:44 AM UTC 24 |
| Peak memory | 207896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656754410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3656754410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_noise_filter.3131790768 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 67451441735 ps |
| CPU time | 21.11 seconds |
| Started | Oct 09 05:31:28 AM UTC 24 |
| Finished | Oct 09 05:31:50 AM UTC 24 |
| Peak memory | 209968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131790768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3131790768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_perf.1078519711 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4780578563 ps |
| CPU time | 175.65 seconds |
| Started | Oct 09 05:31:36 AM UTC 24 |
| Finished | Oct 09 05:34:35 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078519711 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1078519711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_rx_oversample.1761205119 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 6402951904 ps |
| CPU time | 60.9 seconds |
| Started | Oct 09 05:31:27 AM UTC 24 |
| Finished | Oct 09 05:32:29 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761205119 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1761205119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.3986342714 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 50621302071 ps |
| CPU time | 53.28 seconds |
| Started | Oct 09 05:31:29 AM UTC 24 |
| Finished | Oct 09 05:32:24 AM UTC 24 |
| Peak memory | 204196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986342714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3986342714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.929575115 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 40304112028 ps |
| CPU time | 34.44 seconds |
| Started | Oct 09 05:31:28 AM UTC 24 |
| Finished | Oct 09 05:32:04 AM UTC 24 |
| Peak memory | 203740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929575115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.929575115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_smoke.777205442 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 6032428237 ps |
| CPU time | 17.02 seconds |
| Started | Oct 09 05:31:20 AM UTC 24 |
| Finished | Oct 09 05:31:38 AM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777205442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 13.uart_smoke.777205442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_stress_all.2629881317 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 47188977063 ps |
| CPU time | 386.14 seconds |
| Started | Oct 09 05:31:43 AM UTC 24 |
| Finished | Oct 09 05:38:14 AM UTC 24 |
| Peak memory | 209548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629881317 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2629881317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.3891552785 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3191097836 ps |
| CPU time | 26.39 seconds |
| Started | Oct 09 05:31:39 AM UTC 24 |
| Finished | Oct 09 05:32:07 AM UTC 24 |
| Peak memory | 218736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3891552785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all _with_rand_reset.3891552785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.627639199 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1302864640 ps |
| CPU time | 9.62 seconds |
| Started | Oct 09 05:31:31 AM UTC 24 |
| Finished | Oct 09 05:31:42 AM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627639199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.627639199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_tx_rx.2335141019 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 222779934181 ps |
| CPU time | 73.06 seconds |
| Started | Oct 09 05:31:21 AM UTC 24 |
| Finished | Oct 09 05:32:36 AM UTC 24 |
| Peak memory | 209696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335141019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2335141019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/13.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/130.uart_fifo_reset.552308280 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 18839466782 ps |
| CPU time | 59.48 seconds |
| Started | Oct 09 05:56:38 AM UTC 24 |
| Finished | Oct 09 05:57:39 AM UTC 24 |
| Peak memory | 209648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552308280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.552308280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/130.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/131.uart_fifo_reset.455717639 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 45269041057 ps |
| CPU time | 54.23 seconds |
| Started | Oct 09 05:56:39 AM UTC 24 |
| Finished | Oct 09 05:57:35 AM UTC 24 |
| Peak memory | 209412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455717639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.455717639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/131.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/132.uart_fifo_reset.1534729022 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 17847395409 ps |
| CPU time | 46.36 seconds |
| Started | Oct 09 05:56:40 AM UTC 24 |
| Finished | Oct 09 05:57:28 AM UTC 24 |
| Peak memory | 209764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534729022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1534729022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/132.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/133.uart_fifo_reset.3358454084 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 176630491355 ps |
| CPU time | 430.1 seconds |
| Started | Oct 09 05:56:41 AM UTC 24 |
| Finished | Oct 09 06:03:57 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358454084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3358454084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/133.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/134.uart_fifo_reset.1527271331 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 82470353197 ps |
| CPU time | 87.73 seconds |
| Started | Oct 09 05:56:44 AM UTC 24 |
| Finished | Oct 09 05:58:14 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527271331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1527271331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/134.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/135.uart_fifo_reset.3425946384 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 78017396924 ps |
| CPU time | 30.43 seconds |
| Started | Oct 09 05:56:45 AM UTC 24 |
| Finished | Oct 09 05:57:17 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425946384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3425946384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/135.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/137.uart_fifo_reset.62536768 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 40210080988 ps |
| CPU time | 33.44 seconds |
| Started | Oct 09 05:56:51 AM UTC 24 |
| Finished | Oct 09 05:57:25 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62536768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.62536768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/137.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_alert_test.1872065401 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 31791659 ps |
| CPU time | 0.81 seconds |
| Started | Oct 09 05:32:08 AM UTC 24 |
| Finished | Oct 09 05:32:10 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872065401 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1872065401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_fifo_full.116877814 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 23672917455 ps |
| CPU time | 16.76 seconds |
| Started | Oct 09 05:31:47 AM UTC 24 |
| Finished | Oct 09 05:32:05 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116877814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.116877814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_fifo_reset.3040955711 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 5612909554 ps |
| CPU time | 18.44 seconds |
| Started | Oct 09 05:31:48 AM UTC 24 |
| Finished | Oct 09 05:32:08 AM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040955711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3040955711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_intr.3399800021 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 20346628323 ps |
| CPU time | 15.46 seconds |
| Started | Oct 09 05:31:50 AM UTC 24 |
| Finished | Oct 09 05:32:07 AM UTC 24 |
| Peak memory | 203996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399800021 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3399800021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.4018892420 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 156385353171 ps |
| CPU time | 201.66 seconds |
| Started | Oct 09 05:32:06 AM UTC 24 |
| Finished | Oct 09 05:35:31 AM UTC 24 |
| Peak memory | 209736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018892420 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4018892420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_loopback.3557174440 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 7375951225 ps |
| CPU time | 14.89 seconds |
| Started | Oct 09 05:32:05 AM UTC 24 |
| Finished | Oct 09 05:32:21 AM UTC 24 |
| Peak memory | 203936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557174440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3557174440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_noise_filter.4037483552 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 158057314644 ps |
| CPU time | 84.82 seconds |
| Started | Oct 09 05:31:50 AM UTC 24 |
| Finished | Oct 09 05:33:17 AM UTC 24 |
| Peak memory | 220408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037483552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.4037483552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_perf.2954490101 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4016339775 ps |
| CPU time | 60.98 seconds |
| Started | Oct 09 05:32:06 AM UTC 24 |
| Finished | Oct 09 05:33:08 AM UTC 24 |
| Peak memory | 203928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954490101 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2954490101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_rx_oversample.3695566515 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2760238498 ps |
| CPU time | 28.73 seconds |
| Started | Oct 09 05:31:49 AM UTC 24 |
| Finished | Oct 09 05:32:19 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695566515 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3695566515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.3863716469 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4788077021 ps |
| CPU time | 5.27 seconds |
| Started | Oct 09 05:31:51 AM UTC 24 |
| Finished | Oct 09 05:31:58 AM UTC 24 |
| Peak memory | 203924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863716469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3863716469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_smoke.1413102872 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 139326508 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 05:31:45 AM UTC 24 |
| Finished | Oct 09 05:31:47 AM UTC 24 |
| Peak memory | 203344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413102872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1413102872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_stress_all.4261832949 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 146412185383 ps |
| CPU time | 471.68 seconds |
| Started | Oct 09 05:32:08 AM UTC 24 |
| Finished | Oct 09 05:40:06 AM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261832949 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.4261832949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.3297293714 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1146487499 ps |
| CPU time | 2.63 seconds |
| Started | Oct 09 05:32:02 AM UTC 24 |
| Finished | Oct 09 05:32:05 AM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297293714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3297293714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/14.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/141.uart_fifo_reset.1379490954 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 15793374658 ps |
| CPU time | 36.4 seconds |
| Started | Oct 09 05:56:55 AM UTC 24 |
| Finished | Oct 09 05:57:33 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379490954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1379490954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/141.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/143.uart_fifo_reset.3886152656 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 26472175597 ps |
| CPU time | 23.09 seconds |
| Started | Oct 09 05:56:56 AM UTC 24 |
| Finished | Oct 09 05:57:20 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886152656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3886152656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/143.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/144.uart_fifo_reset.4145573638 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 25087567284 ps |
| CPU time | 67.63 seconds |
| Started | Oct 09 05:56:56 AM UTC 24 |
| Finished | Oct 09 05:58:06 AM UTC 24 |
| Peak memory | 209768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145573638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.4145573638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/144.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/145.uart_fifo_reset.2779604367 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 65548311072 ps |
| CPU time | 275.7 seconds |
| Started | Oct 09 05:56:59 AM UTC 24 |
| Finished | Oct 09 06:01:39 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779604367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2779604367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/145.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/146.uart_fifo_reset.1774934971 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 86243049168 ps |
| CPU time | 35.4 seconds |
| Started | Oct 09 05:57:05 AM UTC 24 |
| Finished | Oct 09 05:57:42 AM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774934971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1774934971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/146.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/147.uart_fifo_reset.1432403746 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 232633798852 ps |
| CPU time | 59.58 seconds |
| Started | Oct 09 05:57:05 AM UTC 24 |
| Finished | Oct 09 05:58:07 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432403746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1432403746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/147.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/148.uart_fifo_reset.1030620772 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 19768431110 ps |
| CPU time | 59.16 seconds |
| Started | Oct 09 05:57:14 AM UTC 24 |
| Finished | Oct 09 05:58:14 AM UTC 24 |
| Peak memory | 209360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030620772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1030620772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/148.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/149.uart_fifo_reset.4114386727 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 15809211597 ps |
| CPU time | 7.94 seconds |
| Started | Oct 09 05:57:18 AM UTC 24 |
| Finished | Oct 09 05:57:27 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114386727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4114386727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/149.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_alert_test.3212356676 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 11413550 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 05:32:38 AM UTC 24 |
| Finished | Oct 09 05:32:40 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212356676 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3212356676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_fifo_full.2610055141 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 54725401567 ps |
| CPU time | 29.2 seconds |
| Started | Oct 09 05:32:10 AM UTC 24 |
| Finished | Oct 09 05:32:41 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610055141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2610055141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.1682552877 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 59533252107 ps |
| CPU time | 32.29 seconds |
| Started | Oct 09 05:32:13 AM UTC 24 |
| Finished | Oct 09 05:32:47 AM UTC 24 |
| Peak memory | 209596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682552877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1682552877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_fifo_reset.3526526598 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 82037182826 ps |
| CPU time | 151.27 seconds |
| Started | Oct 09 05:32:20 AM UTC 24 |
| Finished | Oct 09 05:34:54 AM UTC 24 |
| Peak memory | 209704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526526598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3526526598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_intr.3516634452 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 6708832995 ps |
| CPU time | 6.23 seconds |
| Started | Oct 09 05:32:25 AM UTC 24 |
| Finished | Oct 09 05:32:32 AM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516634452 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3516634452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.1559676493 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 172039915810 ps |
| CPU time | 400.37 seconds |
| Started | Oct 09 05:32:33 AM UTC 24 |
| Finished | Oct 09 05:39:19 AM UTC 24 |
| Peak memory | 204312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559676493 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1559676493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_loopback.1227370941 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 4808824639 ps |
| CPU time | 4.44 seconds |
| Started | Oct 09 05:32:32 AM UTC 24 |
| Finished | Oct 09 05:32:38 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227370941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1227370941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_noise_filter.3653230850 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 40984682085 ps |
| CPU time | 79.01 seconds |
| Started | Oct 09 05:32:25 AM UTC 24 |
| Finished | Oct 09 05:33:45 AM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653230850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3653230850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_perf.3012078193 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 17873797352 ps |
| CPU time | 43.83 seconds |
| Started | Oct 09 05:32:32 AM UTC 24 |
| Finished | Oct 09 05:33:18 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012078193 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3012078193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_rx_oversample.3237462405 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1397983207 ps |
| CPU time | 1.74 seconds |
| Started | Oct 09 05:32:22 AM UTC 24 |
| Finished | Oct 09 05:32:24 AM UTC 24 |
| Peak memory | 203272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237462405 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3237462405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.564928824 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 83563023658 ps |
| CPU time | 40.43 seconds |
| Started | Oct 09 05:32:26 AM UTC 24 |
| Finished | Oct 09 05:33:08 AM UTC 24 |
| Peak memory | 204060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564928824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.564928824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_smoke.398141347 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 486107685 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 05:32:09 AM UTC 24 |
| Finished | Oct 09 05:32:12 AM UTC 24 |
| Peak memory | 203352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398141347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 15.uart_smoke.398141347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.3573806619 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 10254862000 ps |
| CPU time | 47.45 seconds |
| Started | Oct 09 05:32:36 AM UTC 24 |
| Finished | Oct 09 05:33:25 AM UTC 24 |
| Peak memory | 218400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3573806619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all _with_rand_reset.3573806619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.4131618884 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 8508562935 ps |
| CPU time | 10.62 seconds |
| Started | Oct 09 05:32:31 AM UTC 24 |
| Finished | Oct 09 05:32:43 AM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131618884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.4131618884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_tx_rx.2529029749 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 71865729799 ps |
| CPU time | 38.58 seconds |
| Started | Oct 09 05:32:09 AM UTC 24 |
| Finished | Oct 09 05:32:49 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529029749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2529029749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/15.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/150.uart_fifo_reset.1262618929 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 120022914183 ps |
| CPU time | 179.28 seconds |
| Started | Oct 09 05:57:22 AM UTC 24 |
| Finished | Oct 09 06:00:24 AM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262618929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1262618929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/150.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/151.uart_fifo_reset.284778942 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 190489413696 ps |
| CPU time | 494.1 seconds |
| Started | Oct 09 05:57:22 AM UTC 24 |
| Finished | Oct 09 06:05:42 AM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284778942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.284778942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/151.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/152.uart_fifo_reset.3718682447 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 113018786865 ps |
| CPU time | 50.77 seconds |
| Started | Oct 09 05:57:23 AM UTC 24 |
| Finished | Oct 09 05:58:15 AM UTC 24 |
| Peak memory | 209448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718682447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3718682447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/152.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/153.uart_fifo_reset.1354716311 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 87433321864 ps |
| CPU time | 235.26 seconds |
| Started | Oct 09 05:57:24 AM UTC 24 |
| Finished | Oct 09 06:01:23 AM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354716311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1354716311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/153.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/154.uart_fifo_reset.166245991 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 61372498925 ps |
| CPU time | 37.47 seconds |
| Started | Oct 09 05:57:24 AM UTC 24 |
| Finished | Oct 09 05:58:03 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166245991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.166245991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/154.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/155.uart_fifo_reset.4068384664 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 106637837049 ps |
| CPU time | 41.75 seconds |
| Started | Oct 09 05:57:25 AM UTC 24 |
| Finished | Oct 09 05:58:08 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068384664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4068384664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/155.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/156.uart_fifo_reset.401598343 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 66010041473 ps |
| CPU time | 312.96 seconds |
| Started | Oct 09 05:57:26 AM UTC 24 |
| Finished | Oct 09 06:02:44 AM UTC 24 |
| Peak memory | 209688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401598343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.401598343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/156.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/157.uart_fifo_reset.2040472512 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 284375088439 ps |
| CPU time | 161.03 seconds |
| Started | Oct 09 05:57:27 AM UTC 24 |
| Finished | Oct 09 06:00:11 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040472512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2040472512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/157.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/158.uart_fifo_reset.1745732010 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 79573629012 ps |
| CPU time | 257.92 seconds |
| Started | Oct 09 05:57:29 AM UTC 24 |
| Finished | Oct 09 06:01:51 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745732010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1745732010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/158.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/159.uart_fifo_reset.2970344000 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 19181947733 ps |
| CPU time | 46.28 seconds |
| Started | Oct 09 05:57:30 AM UTC 24 |
| Finished | Oct 09 05:58:18 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970344000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2970344000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/159.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_alert_test.3754422788 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 19749899 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 05:33:09 AM UTC 24 |
| Finished | Oct 09 05:33:11 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754422788 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3754422788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_fifo_full.2591321162 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 15959073286 ps |
| CPU time | 34.7 seconds |
| Started | Oct 09 05:32:44 AM UTC 24 |
| Finished | Oct 09 05:33:20 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591321162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2591321162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.2285504599 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 76524023118 ps |
| CPU time | 59.86 seconds |
| Started | Oct 09 05:32:44 AM UTC 24 |
| Finished | Oct 09 05:33:45 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285504599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2285504599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_fifo_reset.218178377 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 59303282152 ps |
| CPU time | 28.25 seconds |
| Started | Oct 09 05:32:44 AM UTC 24 |
| Finished | Oct 09 05:33:14 AM UTC 24 |
| Peak memory | 209620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218178377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.218178377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_intr.1610230809 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 23506237025 ps |
| CPU time | 47.93 seconds |
| Started | Oct 09 05:32:48 AM UTC 24 |
| Finished | Oct 09 05:33:38 AM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610230809 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1610230809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.1323166966 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 75568393589 ps |
| CPU time | 218.38 seconds |
| Started | Oct 09 05:33:00 AM UTC 24 |
| Finished | Oct 09 05:36:41 AM UTC 24 |
| Peak memory | 204256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323166966 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1323166966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_loopback.3464858581 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1834258285 ps |
| CPU time | 3.17 seconds |
| Started | Oct 09 05:32:58 AM UTC 24 |
| Finished | Oct 09 05:33:03 AM UTC 24 |
| Peak memory | 208656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464858581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3464858581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_noise_filter.1719014590 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 12029309197 ps |
| CPU time | 22.11 seconds |
| Started | Oct 09 05:32:50 AM UTC 24 |
| Finished | Oct 09 05:33:14 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719014590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1719014590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_perf.3419128423 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 9336765693 ps |
| CPU time | 136.06 seconds |
| Started | Oct 09 05:33:00 AM UTC 24 |
| Finished | Oct 09 05:35:18 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419128423 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3419128423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_rx_oversample.1216109572 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3159024570 ps |
| CPU time | 8.33 seconds |
| Started | Oct 09 05:32:45 AM UTC 24 |
| Finished | Oct 09 05:32:55 AM UTC 24 |
| Peak memory | 204392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216109572 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1216109572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.630752316 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 171510992165 ps |
| CPU time | 137.6 seconds |
| Started | Oct 09 05:32:51 AM UTC 24 |
| Finished | Oct 09 05:35:12 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630752316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.630752316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.255776826 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 5632346171 ps |
| CPU time | 4.81 seconds |
| Started | Oct 09 05:32:51 AM UTC 24 |
| Finished | Oct 09 05:32:57 AM UTC 24 |
| Peak memory | 203740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255776826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.255776826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_smoke.3927618571 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 5447345749 ps |
| CPU time | 16.02 seconds |
| Started | Oct 09 05:32:42 AM UTC 24 |
| Finished | Oct 09 05:32:59 AM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927618571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3927618571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_stress_all.3162418907 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 209701842490 ps |
| CPU time | 893.21 seconds |
| Started | Oct 09 05:33:09 AM UTC 24 |
| Finished | Oct 09 05:48:13 AM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162418907 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3162418907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.390559106 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3278307412 ps |
| CPU time | 38.63 seconds |
| Started | Oct 09 05:33:04 AM UTC 24 |
| Finished | Oct 09 05:33:44 AM UTC 24 |
| Peak memory | 222620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=390559106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all_ with_rand_reset.390559106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.2095148338 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1263670374 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 05:32:55 AM UTC 24 |
| Finished | Oct 09 05:32:59 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095148338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2095148338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/16.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/160.uart_fifo_reset.4041562065 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 119419139908 ps |
| CPU time | 56.54 seconds |
| Started | Oct 09 05:57:32 AM UTC 24 |
| Finished | Oct 09 05:58:30 AM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041562065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.4041562065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/160.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/161.uart_fifo_reset.1288014857 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 14732756655 ps |
| CPU time | 26.17 seconds |
| Started | Oct 09 05:57:34 AM UTC 24 |
| Finished | Oct 09 05:58:02 AM UTC 24 |
| Peak memory | 209136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288014857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1288014857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/161.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/162.uart_fifo_reset.2705015214 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 34284191276 ps |
| CPU time | 68.08 seconds |
| Started | Oct 09 05:57:36 AM UTC 24 |
| Finished | Oct 09 05:58:46 AM UTC 24 |
| Peak memory | 209168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705015214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2705015214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/162.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/163.uart_fifo_reset.409470300 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 176921776734 ps |
| CPU time | 26.83 seconds |
| Started | Oct 09 05:57:36 AM UTC 24 |
| Finished | Oct 09 05:58:04 AM UTC 24 |
| Peak memory | 203952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409470300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.409470300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/163.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/164.uart_fifo_reset.1150654403 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 48770456727 ps |
| CPU time | 25.18 seconds |
| Started | Oct 09 05:57:37 AM UTC 24 |
| Finished | Oct 09 05:58:04 AM UTC 24 |
| Peak memory | 209388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150654403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1150654403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/164.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/165.uart_fifo_reset.2071946507 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 29322825889 ps |
| CPU time | 68.41 seconds |
| Started | Oct 09 05:57:37 AM UTC 24 |
| Finished | Oct 09 05:58:47 AM UTC 24 |
| Peak memory | 209428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071946507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2071946507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/165.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/166.uart_fifo_reset.784528395 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 151722543460 ps |
| CPU time | 146.61 seconds |
| Started | Oct 09 05:57:39 AM UTC 24 |
| Finished | Oct 09 06:00:08 AM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784528395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.784528395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/166.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/167.uart_fifo_reset.3038713923 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 117716647435 ps |
| CPU time | 33.41 seconds |
| Started | Oct 09 05:57:39 AM UTC 24 |
| Finished | Oct 09 05:58:14 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038713923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3038713923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/167.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/168.uart_fifo_reset.1507573101 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 44525045498 ps |
| CPU time | 34.32 seconds |
| Started | Oct 09 05:57:40 AM UTC 24 |
| Finished | Oct 09 05:58:16 AM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507573101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1507573101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/168.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/169.uart_fifo_reset.1359473451 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 102211474095 ps |
| CPU time | 371.05 seconds |
| Started | Oct 09 05:57:42 AM UTC 24 |
| Finished | Oct 09 06:03:58 AM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359473451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1359473451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/169.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_alert_test.1298363933 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 35571757 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 05:33:40 AM UTC 24 |
| Finished | Oct 09 05:33:42 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298363933 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1298363933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_fifo_full.1504743297 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 39050409504 ps |
| CPU time | 72.53 seconds |
| Started | Oct 09 05:33:14 AM UTC 24 |
| Finished | Oct 09 05:34:29 AM UTC 24 |
| Peak memory | 208860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504743297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1504743297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.2029947712 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 131951493933 ps |
| CPU time | 180.36 seconds |
| Started | Oct 09 05:33:14 AM UTC 24 |
| Finished | Oct 09 05:36:18 AM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029947712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2029947712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_fifo_reset.1831271422 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 36157149539 ps |
| CPU time | 113.1 seconds |
| Started | Oct 09 05:33:17 AM UTC 24 |
| Finished | Oct 09 05:35:13 AM UTC 24 |
| Peak memory | 204084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831271422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1831271422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_intr.1857339974 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 304609812038 ps |
| CPU time | 274.11 seconds |
| Started | Oct 09 05:33:21 AM UTC 24 |
| Finished | Oct 09 05:37:58 AM UTC 24 |
| Peak memory | 207824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857339974 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1857339974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.734492742 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 215879249449 ps |
| CPU time | 514.04 seconds |
| Started | Oct 09 05:33:38 AM UTC 24 |
| Finished | Oct 09 05:42:19 AM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734492742 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.734492742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_loopback.2079253600 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 6019430337 ps |
| CPU time | 7.07 seconds |
| Started | Oct 09 05:33:33 AM UTC 24 |
| Finished | Oct 09 05:33:41 AM UTC 24 |
| Peak memory | 204120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079253600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2079253600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_noise_filter.3319068506 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 252234790628 ps |
| CPU time | 84.02 seconds |
| Started | Oct 09 05:33:27 AM UTC 24 |
| Finished | Oct 09 05:34:53 AM UTC 24 |
| Peak memory | 209708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319068506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3319068506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_perf.3145835159 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 11483408193 ps |
| CPU time | 157.22 seconds |
| Started | Oct 09 05:33:33 AM UTC 24 |
| Finished | Oct 09 05:36:13 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145835159 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3145835159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_rx_oversample.2424087904 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 3244425141 ps |
| CPU time | 19.62 seconds |
| Started | Oct 09 05:33:18 AM UTC 24 |
| Finished | Oct 09 05:33:39 AM UTC 24 |
| Peak memory | 204316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424087904 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2424087904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.2805416395 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 113456458765 ps |
| CPU time | 190.37 seconds |
| Started | Oct 09 05:33:32 AM UTC 24 |
| Finished | Oct 09 05:36:45 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805416395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2805416395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.812053834 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3193948233 ps |
| CPU time | 8.03 seconds |
| Started | Oct 09 05:33:30 AM UTC 24 |
| Finished | Oct 09 05:33:39 AM UTC 24 |
| Peak memory | 204124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812053834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.812053834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_smoke.2335164753 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 5369694775 ps |
| CPU time | 28.76 seconds |
| Started | Oct 09 05:33:11 AM UTC 24 |
| Finished | Oct 09 05:33:41 AM UTC 24 |
| Peak memory | 203996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335164753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2335164753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_stress_all.3678311667 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 194408250540 ps |
| CPU time | 187.52 seconds |
| Started | Oct 09 05:33:39 AM UTC 24 |
| Finished | Oct 09 05:36:50 AM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678311667 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3678311667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.2376038187 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 13244395418 ps |
| CPU time | 97.28 seconds |
| Started | Oct 09 05:33:38 AM UTC 24 |
| Finished | Oct 09 05:35:18 AM UTC 24 |
| Peak memory | 222144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2376038187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all _with_rand_reset.2376038187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.3247117758 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 937002582 ps |
| CPU time | 6.69 seconds |
| Started | Oct 09 05:33:32 AM UTC 24 |
| Finished | Oct 09 05:33:40 AM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247117758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3247117758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/17.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/172.uart_fifo_reset.3546376410 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 36412697127 ps |
| CPU time | 13.97 seconds |
| Started | Oct 09 05:57:45 AM UTC 24 |
| Finished | Oct 09 05:58:00 AM UTC 24 |
| Peak memory | 209696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546376410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3546376410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/172.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/173.uart_fifo_reset.2625261389 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 18542445191 ps |
| CPU time | 37.98 seconds |
| Started | Oct 09 05:57:54 AM UTC 24 |
| Finished | Oct 09 05:58:33 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625261389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2625261389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/173.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/174.uart_fifo_reset.3683377505 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 92529253441 ps |
| CPU time | 95.86 seconds |
| Started | Oct 09 05:57:59 AM UTC 24 |
| Finished | Oct 09 05:59:37 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683377505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3683377505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/174.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/175.uart_fifo_reset.683699729 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 286747982694 ps |
| CPU time | 120.89 seconds |
| Started | Oct 09 05:58:01 AM UTC 24 |
| Finished | Oct 09 06:00:04 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683699729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.683699729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/175.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/176.uart_fifo_reset.3001780909 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 73815006566 ps |
| CPU time | 171.88 seconds |
| Started | Oct 09 05:58:03 AM UTC 24 |
| Finished | Oct 09 06:00:58 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001780909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3001780909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/176.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/177.uart_fifo_reset.2471137325 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 181432965856 ps |
| CPU time | 106.63 seconds |
| Started | Oct 09 05:58:04 AM UTC 24 |
| Finished | Oct 09 05:59:53 AM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471137325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2471137325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/177.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/178.uart_fifo_reset.596149330 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 79814121142 ps |
| CPU time | 38.08 seconds |
| Started | Oct 09 05:58:04 AM UTC 24 |
| Finished | Oct 09 05:58:44 AM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596149330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.596149330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/178.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/179.uart_fifo_reset.308530582 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 65664564299 ps |
| CPU time | 97.83 seconds |
| Started | Oct 09 05:58:05 AM UTC 24 |
| Finished | Oct 09 05:59:45 AM UTC 24 |
| Peak memory | 209544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308530582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.308530582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/179.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_alert_test.217064500 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 14084200 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 05:34:19 AM UTC 24 |
| Finished | Oct 09 05:34:22 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217064500 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.217064500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_fifo_full.946168429 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 48935213346 ps |
| CPU time | 36.21 seconds |
| Started | Oct 09 05:33:43 AM UTC 24 |
| Finished | Oct 09 05:34:20 AM UTC 24 |
| Peak memory | 209632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946168429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.946168429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.2451454974 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 167713240182 ps |
| CPU time | 169.82 seconds |
| Started | Oct 09 05:33:43 AM UTC 24 |
| Finished | Oct 09 05:36:35 AM UTC 24 |
| Peak memory | 209640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451454974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2451454974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_intr.900869515 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 24268327469 ps |
| CPU time | 24.1 seconds |
| Started | Oct 09 05:33:46 AM UTC 24 |
| Finished | Oct 09 05:34:11 AM UTC 24 |
| Peak memory | 209404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900869515 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.900869515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.3524175908 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 64442770638 ps |
| CPU time | 677.58 seconds |
| Started | Oct 09 05:34:10 AM UTC 24 |
| Finished | Oct 09 05:45:37 AM UTC 24 |
| Peak memory | 207384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524175908 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3524175908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_loopback.1813401837 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 5417717220 ps |
| CPU time | 18.72 seconds |
| Started | Oct 09 05:33:59 AM UTC 24 |
| Finished | Oct 09 05:34:18 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813401837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1813401837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_noise_filter.3124392131 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 91001520617 ps |
| CPU time | 129.17 seconds |
| Started | Oct 09 05:33:46 AM UTC 24 |
| Finished | Oct 09 05:35:58 AM UTC 24 |
| Peak memory | 209700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124392131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3124392131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_perf.223129202 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 21911963376 ps |
| CPU time | 1046.95 seconds |
| Started | Oct 09 05:34:05 AM UTC 24 |
| Finished | Oct 09 05:51:43 AM UTC 24 |
| Peak memory | 212872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223129202 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.223129202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1105363031 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 7032260468 ps |
| CPU time | 84.23 seconds |
| Started | Oct 09 05:33:45 AM UTC 24 |
| Finished | Oct 09 05:35:11 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105363031 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1105363031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.2982041787 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 134834504640 ps |
| CPU time | 235.98 seconds |
| Started | Oct 09 05:33:48 AM UTC 24 |
| Finished | Oct 09 05:37:48 AM UTC 24 |
| Peak memory | 208940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982041787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2982041787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.1984708302 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1724890370 ps |
| CPU time | 2.79 seconds |
| Started | Oct 09 05:33:48 AM UTC 24 |
| Finished | Oct 09 05:33:52 AM UTC 24 |
| Peak memory | 203988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984708302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1984708302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_smoke.1561206644 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 279429464 ps |
| CPU time | 1.6 seconds |
| Started | Oct 09 05:33:41 AM UTC 24 |
| Finished | Oct 09 05:33:43 AM UTC 24 |
| Peak memory | 203360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561206644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1561206644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_stress_all.362708632 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 392039288952 ps |
| CPU time | 56.61 seconds |
| Started | Oct 09 05:34:12 AM UTC 24 |
| Finished | Oct 09 05:35:10 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362708632 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.362708632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.3189476853 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3491234198 ps |
| CPU time | 40.03 seconds |
| Started | Oct 09 05:34:10 AM UTC 24 |
| Finished | Oct 09 05:34:51 AM UTC 24 |
| Peak memory | 222684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3189476853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all _with_rand_reset.3189476853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.4203028243 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 499699142 ps |
| CPU time | 3.08 seconds |
| Started | Oct 09 05:33:53 AM UTC 24 |
| Finished | Oct 09 05:33:58 AM UTC 24 |
| Peak memory | 204276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203028243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4203028243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_tx_rx.1014955561 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 35419977037 ps |
| CPU time | 37.73 seconds |
| Started | Oct 09 05:33:42 AM UTC 24 |
| Finished | Oct 09 05:34:21 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014955561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1014955561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/18.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/180.uart_fifo_reset.1602382882 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 11814476096 ps |
| CPU time | 21.5 seconds |
| Started | Oct 09 05:58:05 AM UTC 24 |
| Finished | Oct 09 05:58:28 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602382882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1602382882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/180.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/181.uart_fifo_reset.627331021 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 466938414355 ps |
| CPU time | 78.12 seconds |
| Started | Oct 09 05:58:06 AM UTC 24 |
| Finished | Oct 09 05:59:26 AM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627331021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.627331021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/181.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/182.uart_fifo_reset.1960127362 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 35175798723 ps |
| CPU time | 50.55 seconds |
| Started | Oct 09 05:58:07 AM UTC 24 |
| Finished | Oct 09 05:59:00 AM UTC 24 |
| Peak memory | 209152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960127362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1960127362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/182.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/183.uart_fifo_reset.604618412 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 17597629537 ps |
| CPU time | 28.63 seconds |
| Started | Oct 09 05:58:08 AM UTC 24 |
| Finished | Oct 09 05:58:37 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604618412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.604618412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/183.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/184.uart_fifo_reset.4208286972 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 15158846323 ps |
| CPU time | 47.51 seconds |
| Started | Oct 09 05:58:10 AM UTC 24 |
| Finished | Oct 09 05:58:59 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208286972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.4208286972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/184.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/185.uart_fifo_reset.1755667496 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 5188009790 ps |
| CPU time | 17.06 seconds |
| Started | Oct 09 05:58:10 AM UTC 24 |
| Finished | Oct 09 05:58:28 AM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755667496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1755667496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/185.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/186.uart_fifo_reset.2134021402 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 12070077627 ps |
| CPU time | 43.5 seconds |
| Started | Oct 09 05:58:13 AM UTC 24 |
| Finished | Oct 09 05:58:58 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134021402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2134021402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/186.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/187.uart_fifo_reset.2732593831 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 135248421845 ps |
| CPU time | 39.61 seconds |
| Started | Oct 09 05:58:15 AM UTC 24 |
| Finished | Oct 09 05:58:56 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732593831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2732593831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/187.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/188.uart_fifo_reset.3427540614 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 37385999506 ps |
| CPU time | 44.58 seconds |
| Started | Oct 09 05:58:15 AM UTC 24 |
| Finished | Oct 09 05:59:01 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427540614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3427540614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/188.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/189.uart_fifo_reset.1383057915 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 125113085262 ps |
| CPU time | 24.25 seconds |
| Started | Oct 09 05:58:15 AM UTC 24 |
| Finished | Oct 09 05:58:41 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383057915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1383057915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/189.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_alert_test.1703450631 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 185908940 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:34:59 AM UTC 24 |
| Finished | Oct 09 05:35:00 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703450631 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1703450631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.3272816430 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 62182320497 ps |
| CPU time | 99.28 seconds |
| Started | Oct 09 05:34:23 AM UTC 24 |
| Finished | Oct 09 05:36:05 AM UTC 24 |
| Peak memory | 209688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272816430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3272816430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_intr.2331956519 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 20836189542 ps |
| CPU time | 22.36 seconds |
| Started | Oct 09 05:34:34 AM UTC 24 |
| Finished | Oct 09 05:34:57 AM UTC 24 |
| Peak memory | 204316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331956519 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2331956519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.1358694963 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 189668510601 ps |
| CPU time | 305.38 seconds |
| Started | Oct 09 05:34:52 AM UTC 24 |
| Finished | Oct 09 05:40:02 AM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358694963 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1358694963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_loopback.1031347885 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 3128138889 ps |
| CPU time | 11.27 seconds |
| Started | Oct 09 05:34:52 AM UTC 24 |
| Finished | Oct 09 05:35:05 AM UTC 24 |
| Peak memory | 209048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031347885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1031347885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_noise_filter.913294104 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 14403035879 ps |
| CPU time | 28.21 seconds |
| Started | Oct 09 05:34:36 AM UTC 24 |
| Finished | Oct 09 05:35:05 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913294104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.913294104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_perf.2455092087 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 12110171622 ps |
| CPU time | 508.07 seconds |
| Started | Oct 09 05:34:52 AM UTC 24 |
| Finished | Oct 09 05:43:27 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455092087 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2455092087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_rx_oversample.3248877777 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2441396581 ps |
| CPU time | 7.11 seconds |
| Started | Oct 09 05:34:30 AM UTC 24 |
| Finished | Oct 09 05:34:38 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248877777 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3248877777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.39826785 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 30805462503 ps |
| CPU time | 32.81 seconds |
| Started | Oct 09 05:34:41 AM UTC 24 |
| Finished | Oct 09 05:35:15 AM UTC 24 |
| Peak memory | 209440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39826785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.39826785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.11433960 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2444264320 ps |
| CPU time | 7.59 seconds |
| Started | Oct 09 05:34:39 AM UTC 24 |
| Finished | Oct 09 05:34:48 AM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11433960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.11433960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_smoke.3053190461 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 629021838 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 05:34:21 AM UTC 24 |
| Finished | Oct 09 05:34:24 AM UTC 24 |
| Peak memory | 203944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053190461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3053190461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.2913271674 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 39437677509 ps |
| CPU time | 171.03 seconds |
| Started | Oct 09 05:34:53 AM UTC 24 |
| Finished | Oct 09 05:37:47 AM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2913271674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all _with_rand_reset.2913271674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.2216577280 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 844736068 ps |
| CPU time | 2.33 seconds |
| Started | Oct 09 05:34:48 AM UTC 24 |
| Finished | Oct 09 05:34:51 AM UTC 24 |
| Peak memory | 208044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216577280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2216577280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_tx_rx.1068051038 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 16243725077 ps |
| CPU time | 38.87 seconds |
| Started | Oct 09 05:34:22 AM UTC 24 |
| Finished | Oct 09 05:35:03 AM UTC 24 |
| Peak memory | 209540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068051038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1068051038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/19.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/190.uart_fifo_reset.1294600145 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 18394299539 ps |
| CPU time | 7.61 seconds |
| Started | Oct 09 05:58:15 AM UTC 24 |
| Finished | Oct 09 05:58:24 AM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294600145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1294600145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/190.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/191.uart_fifo_reset.1175152571 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 153160003380 ps |
| CPU time | 310.55 seconds |
| Started | Oct 09 05:58:16 AM UTC 24 |
| Finished | Oct 09 06:03:31 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175152571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1175152571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/191.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/192.uart_fifo_reset.1190096493 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 49117226950 ps |
| CPU time | 115.01 seconds |
| Started | Oct 09 05:58:17 AM UTC 24 |
| Finished | Oct 09 06:00:15 AM UTC 24 |
| Peak memory | 209544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190096493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1190096493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/192.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3063736294 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 15578224226 ps |
| CPU time | 30.14 seconds |
| Started | Oct 09 05:58:17 AM UTC 24 |
| Finished | Oct 09 05:58:49 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063736294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3063736294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/193.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/194.uart_fifo_reset.4170555948 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 104133992367 ps |
| CPU time | 98.06 seconds |
| Started | Oct 09 05:58:18 AM UTC 24 |
| Finished | Oct 09 05:59:58 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170555948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.4170555948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/194.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/195.uart_fifo_reset.3198083699 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 377266186637 ps |
| CPU time | 85.26 seconds |
| Started | Oct 09 05:58:20 AM UTC 24 |
| Finished | Oct 09 05:59:47 AM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198083699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3198083699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/195.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/196.uart_fifo_reset.1798365082 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 38100317391 ps |
| CPU time | 58.78 seconds |
| Started | Oct 09 05:58:23 AM UTC 24 |
| Finished | Oct 09 05:59:23 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798365082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1798365082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/196.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/197.uart_fifo_reset.2735388062 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 131068093556 ps |
| CPU time | 240.45 seconds |
| Started | Oct 09 05:58:25 AM UTC 24 |
| Finished | Oct 09 06:02:29 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735388062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2735388062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/197.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_alert_test.1833514087 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 37066024 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 05:26:58 AM UTC 24 |
| Finished | Oct 09 05:27:00 AM UTC 24 |
| Peak memory | 203408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833514087 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1833514087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_fifo_reset.4038686334 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 60757301818 ps |
| CPU time | 45.5 seconds |
| Started | Oct 09 05:26:37 AM UTC 24 |
| Finished | Oct 09 05:27:24 AM UTC 24 |
| Peak memory | 203928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038686334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4038686334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_intr.2115138115 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 5099119101 ps |
| CPU time | 4.94 seconds |
| Started | Oct 09 05:26:43 AM UTC 24 |
| Finished | Oct 09 05:26:49 AM UTC 24 |
| Peak memory | 207888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115138115 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2115138115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.2678069660 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 138675846507 ps |
| CPU time | 1249.52 seconds |
| Started | Oct 09 05:26:52 AM UTC 24 |
| Finished | Oct 09 05:47:57 AM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678069660 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2678069660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_loopback.2598141735 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1446619482 ps |
| CPU time | 2.03 seconds |
| Started | Oct 09 05:26:50 AM UTC 24 |
| Finished | Oct 09 05:26:53 AM UTC 24 |
| Peak memory | 203864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598141735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2598141735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_perf.3897737172 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 16583450746 ps |
| CPU time | 1084.3 seconds |
| Started | Oct 09 05:26:50 AM UTC 24 |
| Finished | Oct 09 05:45:07 AM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897737172 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3897737172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_rx_oversample.1543687527 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1728461149 ps |
| CPU time | 3.07 seconds |
| Started | Oct 09 05:26:39 AM UTC 24 |
| Finished | Oct 09 05:26:44 AM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543687527 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1543687527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.2674198572 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 19538261847 ps |
| CPU time | 53.12 seconds |
| Started | Oct 09 05:26:45 AM UTC 24 |
| Finished | Oct 09 05:27:39 AM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674198572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2674198572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.3524703368 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3156849694 ps |
| CPU time | 9.47 seconds |
| Started | Oct 09 05:26:45 AM UTC 24 |
| Finished | Oct 09 05:26:55 AM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524703368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3524703368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_sec_cm.2301334990 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 130161472 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 05:26:56 AM UTC 24 |
| Finished | Oct 09 05:26:59 AM UTC 24 |
| Peak memory | 235568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301334990 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2301334990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_smoke.1809654101 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 734542046 ps |
| CPU time | 5.52 seconds |
| Started | Oct 09 05:26:35 AM UTC 24 |
| Finished | Oct 09 05:26:42 AM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809654101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1809654101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.3574027404 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8471280205 ps |
| CPU time | 13.49 seconds |
| Started | Oct 09 05:26:50 AM UTC 24 |
| Finished | Oct 09 05:27:04 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574027404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3574027404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_tx_rx.3432709524 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 32730262816 ps |
| CPU time | 35.5 seconds |
| Started | Oct 09 05:26:36 AM UTC 24 |
| Finished | Oct 09 05:27:13 AM UTC 24 |
| Peak memory | 204404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432709524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3432709524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/2.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_alert_test.847744400 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 19390895 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:35:22 AM UTC 24 |
| Finished | Oct 09 05:35:24 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847744400 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.847744400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_fifo_full.272949709 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 28356415640 ps |
| CPU time | 47.7 seconds |
| Started | Oct 09 05:35:05 AM UTC 24 |
| Finished | Oct 09 05:35:54 AM UTC 24 |
| Peak memory | 206056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272949709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.272949709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.2650933161 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 90015766344 ps |
| CPU time | 181.68 seconds |
| Started | Oct 09 05:35:06 AM UTC 24 |
| Finished | Oct 09 05:38:11 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650933161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2650933161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_fifo_reset.2990632045 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 108700895525 ps |
| CPU time | 108.79 seconds |
| Started | Oct 09 05:35:06 AM UTC 24 |
| Finished | Oct 09 05:36:57 AM UTC 24 |
| Peak memory | 209544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990632045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2990632045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_intr.2205180175 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 22330066754 ps |
| CPU time | 50 seconds |
| Started | Oct 09 05:35:12 AM UTC 24 |
| Finished | Oct 09 05:36:04 AM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205180175 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2205180175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.4059094123 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 137663118765 ps |
| CPU time | 563.91 seconds |
| Started | Oct 09 05:35:19 AM UTC 24 |
| Finished | Oct 09 05:44:50 AM UTC 24 |
| Peak memory | 209428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059094123 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4059094123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_loopback.1041361581 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 7656964820 ps |
| CPU time | 17.9 seconds |
| Started | Oct 09 05:35:16 AM UTC 24 |
| Finished | Oct 09 05:35:35 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041361581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1041361581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_noise_filter.422000614 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 120910066990 ps |
| CPU time | 186.18 seconds |
| Started | Oct 09 05:35:12 AM UTC 24 |
| Finished | Oct 09 05:38:22 AM UTC 24 |
| Peak memory | 220348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422000614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.422000614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_perf.1897149001 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 18910905266 ps |
| CPU time | 131.06 seconds |
| Started | Oct 09 05:35:17 AM UTC 24 |
| Finished | Oct 09 05:37:31 AM UTC 24 |
| Peak memory | 204136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897149001 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1897149001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_rx_oversample.627155460 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 2629988552 ps |
| CPU time | 4.12 seconds |
| Started | Oct 09 05:35:11 AM UTC 24 |
| Finished | Oct 09 05:35:16 AM UTC 24 |
| Peak memory | 204076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627155460 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.627155460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.2164350306 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 158558865227 ps |
| CPU time | 88.25 seconds |
| Started | Oct 09 05:35:14 AM UTC 24 |
| Finished | Oct 09 05:36:44 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164350306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2164350306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.3634531239 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 32454336406 ps |
| CPU time | 7.55 seconds |
| Started | Oct 09 05:35:12 AM UTC 24 |
| Finished | Oct 09 05:35:21 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634531239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3634531239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_smoke.459964169 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 102173715 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 05:35:02 AM UTC 24 |
| Finished | Oct 09 05:35:04 AM UTC 24 |
| Peak memory | 203340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459964169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 20.uart_smoke.459964169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_stress_all.2655848348 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 141937722394 ps |
| CPU time | 394.53 seconds |
| Started | Oct 09 05:35:22 AM UTC 24 |
| Finished | Oct 09 05:42:02 AM UTC 24 |
| Peak memory | 204060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655848348 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2655848348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.1225020991 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 6219444583 ps |
| CPU time | 40.36 seconds |
| Started | Oct 09 05:35:19 AM UTC 24 |
| Finished | Oct 09 05:36:01 AM UTC 24 |
| Peak memory | 222876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1225020991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all _with_rand_reset.1225020991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.1913083341 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 7057025882 ps |
| CPU time | 30 seconds |
| Started | Oct 09 05:35:14 AM UTC 24 |
| Finished | Oct 09 05:35:45 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913083341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1913083341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_tx_rx.3723858649 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 46726166300 ps |
| CPU time | 16.33 seconds |
| Started | Oct 09 05:35:04 AM UTC 24 |
| Finished | Oct 09 05:35:21 AM UTC 24 |
| Peak memory | 209236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723858649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3723858649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/20.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/200.uart_fifo_reset.2228307819 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 164397615819 ps |
| CPU time | 330.96 seconds |
| Started | Oct 09 05:58:29 AM UTC 24 |
| Finished | Oct 09 06:04:05 AM UTC 24 |
| Peak memory | 209404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228307819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2228307819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/200.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/201.uart_fifo_reset.3788667437 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 19313658380 ps |
| CPU time | 42.47 seconds |
| Started | Oct 09 05:58:31 AM UTC 24 |
| Finished | Oct 09 05:59:15 AM UTC 24 |
| Peak memory | 209548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788667437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3788667437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/201.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/203.uart_fifo_reset.1399898884 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 22983886488 ps |
| CPU time | 42.82 seconds |
| Started | Oct 09 05:58:34 AM UTC 24 |
| Finished | Oct 09 05:59:19 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399898884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1399898884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/203.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/204.uart_fifo_reset.2047513566 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 52226772515 ps |
| CPU time | 91.61 seconds |
| Started | Oct 09 05:58:34 AM UTC 24 |
| Finished | Oct 09 06:00:08 AM UTC 24 |
| Peak memory | 204248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047513566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2047513566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/204.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/205.uart_fifo_reset.1141214116 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 22950767838 ps |
| CPU time | 13.27 seconds |
| Started | Oct 09 05:58:38 AM UTC 24 |
| Finished | Oct 09 05:58:53 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141214116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1141214116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/205.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2721415274 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 124786003873 ps |
| CPU time | 350.96 seconds |
| Started | Oct 09 05:58:38 AM UTC 24 |
| Finished | Oct 09 06:04:34 AM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721415274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2721415274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/206.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/207.uart_fifo_reset.3846792685 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 108004658792 ps |
| CPU time | 217.15 seconds |
| Started | Oct 09 05:58:42 AM UTC 24 |
| Finished | Oct 09 06:02:22 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846792685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3846792685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/207.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/208.uart_fifo_reset.495071214 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 252066051190 ps |
| CPU time | 57.73 seconds |
| Started | Oct 09 05:58:45 AM UTC 24 |
| Finished | Oct 09 05:59:45 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495071214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.495071214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/208.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/209.uart_fifo_reset.2534398707 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 46906816838 ps |
| CPU time | 19.68 seconds |
| Started | Oct 09 05:58:47 AM UTC 24 |
| Finished | Oct 09 05:59:08 AM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534398707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2534398707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/209.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_alert_test.1094054589 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 42616871 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:36:05 AM UTC 24 |
| Finished | Oct 09 05:36:07 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094054589 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1094054589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_fifo_full.3274854809 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 128723530560 ps |
| CPU time | 174.41 seconds |
| Started | Oct 09 05:35:28 AM UTC 24 |
| Finished | Oct 09 05:38:26 AM UTC 24 |
| Peak memory | 209756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274854809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3274854809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.1387455955 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 19342308438 ps |
| CPU time | 30.57 seconds |
| Started | Oct 09 05:35:32 AM UTC 24 |
| Finished | Oct 09 05:36:03 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387455955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1387455955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_intr.1837985268 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 154003630847 ps |
| CPU time | 292.53 seconds |
| Started | Oct 09 05:35:36 AM UTC 24 |
| Finished | Oct 09 05:40:32 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837985268 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1837985268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.2767909355 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 82949329907 ps |
| CPU time | 580.77 seconds |
| Started | Oct 09 05:35:58 AM UTC 24 |
| Finished | Oct 09 05:45:47 AM UTC 24 |
| Peak memory | 205576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767909355 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2767909355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_loopback.2016977439 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 6828576192 ps |
| CPU time | 10.58 seconds |
| Started | Oct 09 05:35:55 AM UTC 24 |
| Finished | Oct 09 05:36:08 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016977439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2016977439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_noise_filter.3722696441 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 81565739707 ps |
| CPU time | 34.08 seconds |
| Started | Oct 09 05:35:40 AM UTC 24 |
| Finished | Oct 09 05:36:15 AM UTC 24 |
| Peak memory | 209764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722696441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3722696441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_perf.3463896015 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 13386853235 ps |
| CPU time | 832.93 seconds |
| Started | Oct 09 05:35:58 AM UTC 24 |
| Finished | Oct 09 05:50:02 AM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463896015 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3463896015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_rx_oversample.3686344224 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 5059755875 ps |
| CPU time | 62.31 seconds |
| Started | Oct 09 05:35:35 AM UTC 24 |
| Finished | Oct 09 05:36:39 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686344224 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3686344224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.2724956506 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 70954510756 ps |
| CPU time | 33.93 seconds |
| Started | Oct 09 05:35:47 AM UTC 24 |
| Finished | Oct 09 05:36:22 AM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724956506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2724956506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.3716922564 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 4883668035 ps |
| CPU time | 18.66 seconds |
| Started | Oct 09 05:35:46 AM UTC 24 |
| Finished | Oct 09 05:36:06 AM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716922564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3716922564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_smoke.2456407277 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 291955681 ps |
| CPU time | 2.07 seconds |
| Started | Oct 09 05:35:24 AM UTC 24 |
| Finished | Oct 09 05:35:27 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456407277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2456407277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.2721121226 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1412455944 ps |
| CPU time | 9.9 seconds |
| Started | Oct 09 05:35:59 AM UTC 24 |
| Finished | Oct 09 05:36:10 AM UTC 24 |
| Peak memory | 209100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2721121226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all _with_rand_reset.2721121226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.4144385315 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 4346639468 ps |
| CPU time | 4.3 seconds |
| Started | Oct 09 05:35:52 AM UTC 24 |
| Finished | Oct 09 05:35:58 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144385315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4144385315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_tx_rx.2531217872 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 51025928610 ps |
| CPU time | 109.41 seconds |
| Started | Oct 09 05:35:25 AM UTC 24 |
| Finished | Oct 09 05:37:17 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531217872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2531217872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/21.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/210.uart_fifo_reset.913017341 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 185403316180 ps |
| CPU time | 90.19 seconds |
| Started | Oct 09 05:58:48 AM UTC 24 |
| Finished | Oct 09 06:00:20 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913017341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.913017341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/210.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/212.uart_fifo_reset.2127554268 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 155486128387 ps |
| CPU time | 72.4 seconds |
| Started | Oct 09 05:58:54 AM UTC 24 |
| Finished | Oct 09 06:00:08 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127554268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2127554268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/212.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/214.uart_fifo_reset.2789570593 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 96548340982 ps |
| CPU time | 220.2 seconds |
| Started | Oct 09 05:58:58 AM UTC 24 |
| Finished | Oct 09 06:02:42 AM UTC 24 |
| Peak memory | 204132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789570593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2789570593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/214.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/215.uart_fifo_reset.3084052583 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 105279606158 ps |
| CPU time | 113.44 seconds |
| Started | Oct 09 05:58:59 AM UTC 24 |
| Finished | Oct 09 06:00:55 AM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084052583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3084052583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/215.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/216.uart_fifo_reset.1722009099 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 101954367306 ps |
| CPU time | 89.05 seconds |
| Started | Oct 09 05:58:59 AM UTC 24 |
| Finished | Oct 09 06:00:31 AM UTC 24 |
| Peak memory | 209760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722009099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1722009099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/216.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/217.uart_fifo_reset.1280525734 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 154085959757 ps |
| CPU time | 81.05 seconds |
| Started | Oct 09 05:59:01 AM UTC 24 |
| Finished | Oct 09 06:00:24 AM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280525734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1280525734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/217.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/218.uart_fifo_reset.3534291045 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 46548467651 ps |
| CPU time | 17.29 seconds |
| Started | Oct 09 05:59:02 AM UTC 24 |
| Finished | Oct 09 05:59:20 AM UTC 24 |
| Peak memory | 209620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534291045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3534291045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/218.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/219.uart_fifo_reset.3582389570 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 59365599333 ps |
| CPU time | 38.42 seconds |
| Started | Oct 09 05:59:09 AM UTC 24 |
| Finished | Oct 09 05:59:49 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582389570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3582389570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/219.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_alert_test.1035858507 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 13621647 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 05:36:30 AM UTC 24 |
| Finished | Oct 09 05:36:32 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035858507 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1035858507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_fifo_full.475966624 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 96546613517 ps |
| CPU time | 70.7 seconds |
| Started | Oct 09 05:36:07 AM UTC 24 |
| Finished | Oct 09 05:37:20 AM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475966624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.475966624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.3550321701 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 179410805314 ps |
| CPU time | 326.19 seconds |
| Started | Oct 09 05:36:07 AM UTC 24 |
| Finished | Oct 09 05:41:38 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550321701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3550321701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_fifo_reset.2175236274 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 112594657152 ps |
| CPU time | 57.08 seconds |
| Started | Oct 09 05:36:07 AM UTC 24 |
| Finished | Oct 09 05:37:06 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175236274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2175236274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.3302655114 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 113105475794 ps |
| CPU time | 911.97 seconds |
| Started | Oct 09 05:36:22 AM UTC 24 |
| Finished | Oct 09 05:51:45 AM UTC 24 |
| Peak memory | 209672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302655114 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3302655114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_loopback.3139003632 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 228622925 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 05:36:19 AM UTC 24 |
| Finished | Oct 09 05:36:21 AM UTC 24 |
| Peak memory | 203280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139003632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3139003632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_noise_filter.1830599088 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 51002172360 ps |
| CPU time | 81.5 seconds |
| Started | Oct 09 05:36:10 AM UTC 24 |
| Finished | Oct 09 05:37:34 AM UTC 24 |
| Peak memory | 218856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830599088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1830599088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_perf.1280638985 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 16329899151 ps |
| CPU time | 1265.08 seconds |
| Started | Oct 09 05:36:21 AM UTC 24 |
| Finished | Oct 09 05:57:41 AM UTC 24 |
| Peak memory | 207464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280638985 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1280638985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_rx_oversample.3324055640 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 7135358578 ps |
| CPU time | 62.54 seconds |
| Started | Oct 09 05:36:08 AM UTC 24 |
| Finished | Oct 09 05:37:13 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324055640 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3324055640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.2565140615 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 8774283566 ps |
| CPU time | 24.67 seconds |
| Started | Oct 09 05:36:17 AM UTC 24 |
| Finished | Oct 09 05:36:43 AM UTC 24 |
| Peak memory | 207896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565140615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2565140615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.2260951186 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3848614321 ps |
| CPU time | 4.73 seconds |
| Started | Oct 09 05:36:13 AM UTC 24 |
| Finished | Oct 09 05:36:20 AM UTC 24 |
| Peak memory | 203924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260951186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2260951186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_smoke.3799247694 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 483748795 ps |
| CPU time | 3.43 seconds |
| Started | Oct 09 05:36:05 AM UTC 24 |
| Finished | Oct 09 05:36:09 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799247694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3799247694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_stress_all.2629813483 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 220592367869 ps |
| CPU time | 95.77 seconds |
| Started | Oct 09 05:36:25 AM UTC 24 |
| Finished | Oct 09 05:38:03 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629813483 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2629813483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.1336696956 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2786412120 ps |
| CPU time | 23.42 seconds |
| Started | Oct 09 05:36:23 AM UTC 24 |
| Finished | Oct 09 05:36:48 AM UTC 24 |
| Peak memory | 219684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1336696956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all _with_rand_reset.1336696956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.3341243791 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1451530041 ps |
| CPU time | 4.76 seconds |
| Started | Oct 09 05:36:19 AM UTC 24 |
| Finished | Oct 09 05:36:25 AM UTC 24 |
| Peak memory | 204020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341243791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3341243791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/22.uart_tx_rx.4168810410 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 58418635333 ps |
| CPU time | 136.6 seconds |
| Started | Oct 09 05:36:06 AM UTC 24 |
| Finished | Oct 09 05:38:25 AM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168810410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.4168810410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/220.uart_fifo_reset.3771838766 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 137951343069 ps |
| CPU time | 95.8 seconds |
| Started | Oct 09 05:59:10 AM UTC 24 |
| Finished | Oct 09 06:00:49 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771838766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3771838766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/220.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/221.uart_fifo_reset.1524157829 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 44477089005 ps |
| CPU time | 81.31 seconds |
| Started | Oct 09 05:59:11 AM UTC 24 |
| Finished | Oct 09 06:00:35 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524157829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1524157829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/221.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/222.uart_fifo_reset.1624580212 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 165855853144 ps |
| CPU time | 251.79 seconds |
| Started | Oct 09 05:59:12 AM UTC 24 |
| Finished | Oct 09 06:03:28 AM UTC 24 |
| Peak memory | 209544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624580212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1624580212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/222.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/223.uart_fifo_reset.2204118228 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 128278470841 ps |
| CPU time | 302.46 seconds |
| Started | Oct 09 05:59:12 AM UTC 24 |
| Finished | Oct 09 06:04:19 AM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204118228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2204118228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/223.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/224.uart_fifo_reset.3473202527 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 54217456280 ps |
| CPU time | 23.75 seconds |
| Started | Oct 09 05:59:16 AM UTC 24 |
| Finished | Oct 09 05:59:41 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473202527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3473202527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/224.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/225.uart_fifo_reset.2338197310 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 28059341725 ps |
| CPU time | 83.66 seconds |
| Started | Oct 09 05:59:19 AM UTC 24 |
| Finished | Oct 09 06:00:45 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338197310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2338197310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/225.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/226.uart_fifo_reset.501367968 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 19611934378 ps |
| CPU time | 63.54 seconds |
| Started | Oct 09 05:59:21 AM UTC 24 |
| Finished | Oct 09 06:00:27 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501367968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.501367968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/226.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/227.uart_fifo_reset.1562087903 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 31132874614 ps |
| CPU time | 28.04 seconds |
| Started | Oct 09 05:59:24 AM UTC 24 |
| Finished | Oct 09 05:59:53 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562087903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1562087903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/227.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/228.uart_fifo_reset.19423945 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 59311705304 ps |
| CPU time | 32.48 seconds |
| Started | Oct 09 05:59:28 AM UTC 24 |
| Finished | Oct 09 06:00:02 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19423945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.19423945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/228.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/229.uart_fifo_reset.1406489736 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 104108585492 ps |
| CPU time | 124.31 seconds |
| Started | Oct 09 05:59:38 AM UTC 24 |
| Finished | Oct 09 06:01:44 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406489736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1406489736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/229.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_alert_test.2223637089 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 33043383 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 05:36:58 AM UTC 24 |
| Finished | Oct 09 05:37:00 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223637089 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2223637089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_fifo_full.3402815851 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 45099624884 ps |
| CPU time | 50.87 seconds |
| Started | Oct 09 05:36:36 AM UTC 24 |
| Finished | Oct 09 05:37:29 AM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402815851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3402815851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.2094105747 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 109318178183 ps |
| CPU time | 204.17 seconds |
| Started | Oct 09 05:36:38 AM UTC 24 |
| Finished | Oct 09 05:40:05 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094105747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2094105747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_fifo_reset.2072141629 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 88701940782 ps |
| CPU time | 97.01 seconds |
| Started | Oct 09 05:36:40 AM UTC 24 |
| Finished | Oct 09 05:38:19 AM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072141629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2072141629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_intr.3380686067 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2656746166 ps |
| CPU time | 5.75 seconds |
| Started | Oct 09 05:36:44 AM UTC 24 |
| Finished | Oct 09 05:36:51 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380686067 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3380686067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.2177417607 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 131438114208 ps |
| CPU time | 1090.3 seconds |
| Started | Oct 09 05:36:51 AM UTC 24 |
| Finished | Oct 09 05:55:15 AM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177417607 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2177417607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_loopback.2680974291 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 152651416 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 05:36:49 AM UTC 24 |
| Finished | Oct 09 05:36:52 AM UTC 24 |
| Peak memory | 203280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680974291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2680974291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_noise_filter.2202824881 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 150157714402 ps |
| CPU time | 80.95 seconds |
| Started | Oct 09 05:36:44 AM UTC 24 |
| Finished | Oct 09 05:38:07 AM UTC 24 |
| Peak memory | 209704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202824881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2202824881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_perf.3989149733 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 4690840171 ps |
| CPU time | 265.55 seconds |
| Started | Oct 09 05:36:51 AM UTC 24 |
| Finished | Oct 09 05:41:21 AM UTC 24 |
| Peak memory | 204276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989149733 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3989149733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_rx_oversample.1544529741 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4029345867 ps |
| CPU time | 33 seconds |
| Started | Oct 09 05:36:43 AM UTC 24 |
| Finished | Oct 09 05:37:17 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544529741 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1544529741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.31232015 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 6002261046 ps |
| CPU time | 14.65 seconds |
| Started | Oct 09 05:36:46 AM UTC 24 |
| Finished | Oct 09 05:37:02 AM UTC 24 |
| Peak memory | 209344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31232015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.31232015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.1497044759 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1939702711 ps |
| CPU time | 2.55 seconds |
| Started | Oct 09 05:36:45 AM UTC 24 |
| Finished | Oct 09 05:36:49 AM UTC 24 |
| Peak memory | 203988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497044759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1497044759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_smoke.476526392 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 745729828 ps |
| CPU time | 3.6 seconds |
| Started | Oct 09 05:36:32 AM UTC 24 |
| Finished | Oct 09 05:36:37 AM UTC 24 |
| Peak memory | 204076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476526392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 23.uart_smoke.476526392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_stress_all.3245910377 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 122817901751 ps |
| CPU time | 1435.41 seconds |
| Started | Oct 09 05:36:54 AM UTC 24 |
| Finished | Oct 09 06:01:06 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245910377 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3245910377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.3913023623 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 10415681675 ps |
| CPU time | 81 seconds |
| Started | Oct 09 05:36:53 AM UTC 24 |
| Finished | Oct 09 05:38:15 AM UTC 24 |
| Peak memory | 220696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3913023623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all _with_rand_reset.3913023623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.204539023 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2041079893 ps |
| CPU time | 3.37 seconds |
| Started | Oct 09 05:36:48 AM UTC 24 |
| Finished | Oct 09 05:36:53 AM UTC 24 |
| Peak memory | 203936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204539023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.204539023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/23.uart_tx_rx.1592062552 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 16564156911 ps |
| CPU time | 36.04 seconds |
| Started | Oct 09 05:36:33 AM UTC 24 |
| Finished | Oct 09 05:37:11 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592062552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1592062552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/23.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/230.uart_fifo_reset.829731516 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 23952249734 ps |
| CPU time | 40.71 seconds |
| Started | Oct 09 05:59:42 AM UTC 24 |
| Finished | Oct 09 06:00:24 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829731516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.829731516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/230.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/231.uart_fifo_reset.4163940467 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 84434442224 ps |
| CPU time | 36.81 seconds |
| Started | Oct 09 05:59:46 AM UTC 24 |
| Finished | Oct 09 06:00:24 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163940467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.4163940467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/231.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/232.uart_fifo_reset.3956650603 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 152524588015 ps |
| CPU time | 255.19 seconds |
| Started | Oct 09 05:59:46 AM UTC 24 |
| Finished | Oct 09 06:04:05 AM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956650603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3956650603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/232.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2979676450 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 17637885659 ps |
| CPU time | 57.95 seconds |
| Started | Oct 09 05:59:47 AM UTC 24 |
| Finished | Oct 09 06:00:47 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979676450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2979676450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/233.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/234.uart_fifo_reset.2932994170 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 77953276170 ps |
| CPU time | 346.58 seconds |
| Started | Oct 09 05:59:50 AM UTC 24 |
| Finished | Oct 09 06:05:42 AM UTC 24 |
| Peak memory | 207388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932994170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2932994170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/234.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/235.uart_fifo_reset.2079067126 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 123243136984 ps |
| CPU time | 236.78 seconds |
| Started | Oct 09 05:59:50 AM UTC 24 |
| Finished | Oct 09 06:03:51 AM UTC 24 |
| Peak memory | 209616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079067126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2079067126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/235.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/236.uart_fifo_reset.256271553 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 21675200712 ps |
| CPU time | 26.85 seconds |
| Started | Oct 09 05:59:54 AM UTC 24 |
| Finished | Oct 09 06:00:22 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256271553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.256271553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/236.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/238.uart_fifo_reset.1769093591 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 19790546625 ps |
| CPU time | 63.59 seconds |
| Started | Oct 09 05:59:55 AM UTC 24 |
| Finished | Oct 09 06:01:00 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769093591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1769093591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/238.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1108644095 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 62138030879 ps |
| CPU time | 62.06 seconds |
| Started | Oct 09 06:00:00 AM UTC 24 |
| Finished | Oct 09 06:01:04 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108644095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1108644095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/239.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_alert_test.3686021527 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 12451230 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 05:37:29 AM UTC 24 |
| Finished | Oct 09 05:37:31 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686021527 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3686021527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_fifo_full.1619969228 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 91508167067 ps |
| CPU time | 38.61 seconds |
| Started | Oct 09 05:37:06 AM UTC 24 |
| Finished | Oct 09 05:37:46 AM UTC 24 |
| Peak memory | 203996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619969228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1619969228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.3910236392 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 189953169292 ps |
| CPU time | 99.5 seconds |
| Started | Oct 09 05:37:07 AM UTC 24 |
| Finished | Oct 09 05:38:49 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910236392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3910236392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_intr.191992672 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 24107852259 ps |
| CPU time | 22.85 seconds |
| Started | Oct 09 05:37:15 AM UTC 24 |
| Finished | Oct 09 05:37:40 AM UTC 24 |
| Peak memory | 209156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191992672 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.191992672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.3453317485 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 149307740811 ps |
| CPU time | 364.23 seconds |
| Started | Oct 09 05:37:24 AM UTC 24 |
| Finished | Oct 09 05:43:34 AM UTC 24 |
| Peak memory | 206108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453317485 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3453317485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_loopback.1450200910 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 3366375412 ps |
| CPU time | 8.77 seconds |
| Started | Oct 09 05:37:23 AM UTC 24 |
| Finished | Oct 09 05:37:33 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450200910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1450200910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_perf.2721772562 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 6938591846 ps |
| CPU time | 484.97 seconds |
| Started | Oct 09 05:37:24 AM UTC 24 |
| Finished | Oct 09 05:45:35 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721772562 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2721772562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_rx_oversample.3978916107 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 7137514269 ps |
| CPU time | 16.41 seconds |
| Started | Oct 09 05:37:13 AM UTC 24 |
| Finished | Oct 09 05:37:31 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978916107 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3978916107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.1626712758 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 38039722153 ps |
| CPU time | 82.46 seconds |
| Started | Oct 09 05:37:20 AM UTC 24 |
| Finished | Oct 09 05:38:44 AM UTC 24 |
| Peak memory | 209348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626712758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1626712758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.4206142696 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 38381158107 ps |
| CPU time | 4.28 seconds |
| Started | Oct 09 05:37:19 AM UTC 24 |
| Finished | Oct 09 05:37:24 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206142696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.4206142696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_smoke.3977806146 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 957669887 ps |
| CPU time | 2.93 seconds |
| Started | Oct 09 05:37:01 AM UTC 24 |
| Finished | Oct 09 05:37:05 AM UTC 24 |
| Peak memory | 204016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977806146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3977806146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_stress_all.3821607891 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 605932797111 ps |
| CPU time | 1462.25 seconds |
| Started | Oct 09 05:37:25 AM UTC 24 |
| Finished | Oct 09 06:02:03 AM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821607891 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3821607891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.3889329422 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3161140333 ps |
| CPU time | 24.88 seconds |
| Started | Oct 09 05:37:25 AM UTC 24 |
| Finished | Oct 09 05:37:52 AM UTC 24 |
| Peak memory | 220424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3889329422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all _with_rand_reset.3889329422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.721897624 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1116281810 ps |
| CPU time | 2.36 seconds |
| Started | Oct 09 05:37:21 AM UTC 24 |
| Finished | Oct 09 05:37:24 AM UTC 24 |
| Peak memory | 204280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721897624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.721897624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_tx_rx.3594204215 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 11387290511 ps |
| CPU time | 18.88 seconds |
| Started | Oct 09 05:37:03 AM UTC 24 |
| Finished | Oct 09 05:37:23 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594204215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3594204215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/241.uart_fifo_reset.2558758414 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 295957803599 ps |
| CPU time | 62.66 seconds |
| Started | Oct 09 06:00:02 AM UTC 24 |
| Finished | Oct 09 06:01:12 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558758414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2558758414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/241.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/242.uart_fifo_reset.285369409 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 12581959075 ps |
| CPU time | 30.22 seconds |
| Started | Oct 09 06:00:03 AM UTC 24 |
| Finished | Oct 09 06:00:39 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285369409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.285369409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/242.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1338300694 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 35792295955 ps |
| CPU time | 97.1 seconds |
| Started | Oct 09 06:00:09 AM UTC 24 |
| Finished | Oct 09 06:01:49 AM UTC 24 |
| Peak memory | 209540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338300694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1338300694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/243.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/244.uart_fifo_reset.3742676303 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 132992488254 ps |
| CPU time | 82.85 seconds |
| Started | Oct 09 06:00:09 AM UTC 24 |
| Finished | Oct 09 06:01:34 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742676303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3742676303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/244.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/245.uart_fifo_reset.2522188518 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 18834738037 ps |
| CPU time | 43.7 seconds |
| Started | Oct 09 06:00:09 AM UTC 24 |
| Finished | Oct 09 06:00:55 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522188518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2522188518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/245.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/246.uart_fifo_reset.3612623618 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 206133799090 ps |
| CPU time | 66.12 seconds |
| Started | Oct 09 06:00:09 AM UTC 24 |
| Finished | Oct 09 06:01:17 AM UTC 24 |
| Peak memory | 209504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612623618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3612623618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/246.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/247.uart_fifo_reset.1823007845 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 107620321860 ps |
| CPU time | 210.63 seconds |
| Started | Oct 09 06:00:10 AM UTC 24 |
| Finished | Oct 09 06:03:44 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823007845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1823007845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/247.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3639776614 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 7854397599 ps |
| CPU time | 15.16 seconds |
| Started | Oct 09 06:00:10 AM UTC 24 |
| Finished | Oct 09 06:00:26 AM UTC 24 |
| Peak memory | 203936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639776614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3639776614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/248.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/249.uart_fifo_reset.3149846345 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 87168583844 ps |
| CPU time | 107.94 seconds |
| Started | Oct 09 06:00:12 AM UTC 24 |
| Finished | Oct 09 06:02:02 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149846345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3149846345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/249.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_alert_test.590370604 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 41913031 ps |
| CPU time | 0.77 seconds |
| Started | Oct 09 05:37:55 AM UTC 24 |
| Finished | Oct 09 05:37:57 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590370604 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.590370604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_fifo_full.2354733748 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 113240419631 ps |
| CPU time | 122.99 seconds |
| Started | Oct 09 05:37:33 AM UTC 24 |
| Finished | Oct 09 05:39:38 AM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354733748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2354733748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.4117665822 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 28893533185 ps |
| CPU time | 49.86 seconds |
| Started | Oct 09 05:37:34 AM UTC 24 |
| Finished | Oct 09 05:38:25 AM UTC 24 |
| Peak memory | 209612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117665822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.4117665822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_fifo_reset.1186822386 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 156269458782 ps |
| CPU time | 89.84 seconds |
| Started | Oct 09 05:37:35 AM UTC 24 |
| Finished | Oct 09 05:39:07 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186822386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1186822386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_intr.3085167524 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 32310129984 ps |
| CPU time | 56.96 seconds |
| Started | Oct 09 05:37:36 AM UTC 24 |
| Finished | Oct 09 05:38:35 AM UTC 24 |
| Peak memory | 207888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085167524 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3085167524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.4010786915 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 113010849040 ps |
| CPU time | 301.98 seconds |
| Started | Oct 09 05:37:52 AM UTC 24 |
| Finished | Oct 09 05:42:58 AM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010786915 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.4010786915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_loopback.2764091144 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 2687846556 ps |
| CPU time | 3.75 seconds |
| Started | Oct 09 05:37:48 AM UTC 24 |
| Finished | Oct 09 05:37:53 AM UTC 24 |
| Peak memory | 208152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764091144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2764091144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_noise_filter.1468994997 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 18339622676 ps |
| CPU time | 51.05 seconds |
| Started | Oct 09 05:37:40 AM UTC 24 |
| Finished | Oct 09 05:38:33 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468994997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1468994997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_perf.3605647344 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 16096635879 ps |
| CPU time | 211.97 seconds |
| Started | Oct 09 05:37:48 AM UTC 24 |
| Finished | Oct 09 05:41:24 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605647344 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3605647344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_rx_oversample.1008200409 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2268373493 ps |
| CPU time | 9.15 seconds |
| Started | Oct 09 05:37:35 AM UTC 24 |
| Finished | Oct 09 05:37:45 AM UTC 24 |
| Peak memory | 204392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008200409 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1008200409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.3974130597 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 30590043263 ps |
| CPU time | 100.9 seconds |
| Started | Oct 09 05:37:47 AM UTC 24 |
| Finished | Oct 09 05:39:30 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974130597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3974130597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.758781533 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2297494257 ps |
| CPU time | 3.04 seconds |
| Started | Oct 09 05:37:46 AM UTC 24 |
| Finished | Oct 09 05:37:50 AM UTC 24 |
| Peak memory | 203804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758781533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.758781533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_smoke.806616272 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 474820669 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 05:37:31 AM UTC 24 |
| Finished | Oct 09 05:37:34 AM UTC 24 |
| Peak memory | 202976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806616272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 25.uart_smoke.806616272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_stress_all.329301949 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 182181263022 ps |
| CPU time | 444.07 seconds |
| Started | Oct 09 05:37:54 AM UTC 24 |
| Finished | Oct 09 05:45:23 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329301949 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.329301949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.266258792 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 30972100531 ps |
| CPU time | 68.48 seconds |
| Started | Oct 09 05:37:53 AM UTC 24 |
| Finished | Oct 09 05:39:03 AM UTC 24 |
| Peak memory | 222748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=266258792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all_ with_rand_reset.266258792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.4114331431 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 10386161728 ps |
| CPU time | 17.94 seconds |
| Started | Oct 09 05:37:48 AM UTC 24 |
| Finished | Oct 09 05:38:08 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114331431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4114331431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_tx_rx.2299298243 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 43728717418 ps |
| CPU time | 88.02 seconds |
| Started | Oct 09 05:37:31 AM UTC 24 |
| Finished | Oct 09 05:39:01 AM UTC 24 |
| Peak memory | 209164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299298243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2299298243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/25.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1096365564 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 37251239067 ps |
| CPU time | 41.45 seconds |
| Started | Oct 09 06:00:16 AM UTC 24 |
| Finished | Oct 09 06:00:59 AM UTC 24 |
| Peak memory | 209408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096365564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1096365564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/250.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/252.uart_fifo_reset.1005133037 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 106228332951 ps |
| CPU time | 29.82 seconds |
| Started | Oct 09 06:00:21 AM UTC 24 |
| Finished | Oct 09 06:00:52 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005133037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1005133037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/252.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/253.uart_fifo_reset.3108009142 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 10319366665 ps |
| CPU time | 17.88 seconds |
| Started | Oct 09 06:00:22 AM UTC 24 |
| Finished | Oct 09 06:00:41 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108009142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3108009142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/253.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/254.uart_fifo_reset.52525046 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 31611661535 ps |
| CPU time | 25.03 seconds |
| Started | Oct 09 06:00:24 AM UTC 24 |
| Finished | Oct 09 06:00:51 AM UTC 24 |
| Peak memory | 209548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52525046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.52525046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/254.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/255.uart_fifo_reset.527518369 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 149513559474 ps |
| CPU time | 167.72 seconds |
| Started | Oct 09 06:00:24 AM UTC 24 |
| Finished | Oct 09 06:03:15 AM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527518369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.527518369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/255.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/256.uart_fifo_reset.758145141 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 25436235060 ps |
| CPU time | 75 seconds |
| Started | Oct 09 06:00:25 AM UTC 24 |
| Finished | Oct 09 06:01:42 AM UTC 24 |
| Peak memory | 209408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758145141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.758145141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/256.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/257.uart_fifo_reset.3408389406 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 184498618490 ps |
| CPU time | 197.54 seconds |
| Started | Oct 09 06:00:25 AM UTC 24 |
| Finished | Oct 09 06:03:46 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408389406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3408389406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/257.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/258.uart_fifo_reset.4182092641 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 101462974996 ps |
| CPU time | 261.82 seconds |
| Started | Oct 09 06:00:26 AM UTC 24 |
| Finished | Oct 09 06:04:52 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182092641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.4182092641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/258.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/259.uart_fifo_reset.3274366934 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 123424872510 ps |
| CPU time | 111.39 seconds |
| Started | Oct 09 06:00:28 AM UTC 24 |
| Finished | Oct 09 06:02:21 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274366934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3274366934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/259.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_alert_test.3299777759 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 42560356 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 05:38:28 AM UTC 24 |
| Finished | Oct 09 05:38:29 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299777759 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3299777759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_fifo_full.3684522100 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 151028185002 ps |
| CPU time | 269.79 seconds |
| Started | Oct 09 05:38:02 AM UTC 24 |
| Finished | Oct 09 05:42:36 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684522100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3684522100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.3788029337 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 110906749327 ps |
| CPU time | 41.97 seconds |
| Started | Oct 09 05:38:04 AM UTC 24 |
| Finished | Oct 09 05:38:48 AM UTC 24 |
| Peak memory | 209652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788029337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3788029337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_fifo_reset.2515392565 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 42801494463 ps |
| CPU time | 58.37 seconds |
| Started | Oct 09 05:38:07 AM UTC 24 |
| Finished | Oct 09 05:39:07 AM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515392565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2515392565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.408615455 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 101745853071 ps |
| CPU time | 171.06 seconds |
| Started | Oct 09 05:38:25 AM UTC 24 |
| Finished | Oct 09 05:41:19 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408615455 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.408615455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_loopback.453045345 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 5447910943 ps |
| CPU time | 5.6 seconds |
| Started | Oct 09 05:38:23 AM UTC 24 |
| Finished | Oct 09 05:38:30 AM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453045345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 26.uart_loopback.453045345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_noise_filter.40504858 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 74766782245 ps |
| CPU time | 40 seconds |
| Started | Oct 09 05:38:15 AM UTC 24 |
| Finished | Oct 09 05:38:56 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40504858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.40504858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_perf.739064832 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 18996897846 ps |
| CPU time | 616.74 seconds |
| Started | Oct 09 05:38:23 AM UTC 24 |
| Finished | Oct 09 05:48:48 AM UTC 24 |
| Peak memory | 204060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739064832 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.739064832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_rx_oversample.4205440025 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2614933894 ps |
| CPU time | 6.76 seconds |
| Started | Oct 09 05:38:08 AM UTC 24 |
| Finished | Oct 09 05:38:16 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205440025 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4205440025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.2122019721 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 106311868683 ps |
| CPU time | 98.87 seconds |
| Started | Oct 09 05:38:17 AM UTC 24 |
| Finished | Oct 09 05:39:58 AM UTC 24 |
| Peak memory | 209504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122019721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2122019721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.3319576575 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 3473723443 ps |
| CPU time | 4.46 seconds |
| Started | Oct 09 05:38:17 AM UTC 24 |
| Finished | Oct 09 05:38:22 AM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319576575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3319576575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_smoke.4239699749 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 247598753 ps |
| CPU time | 1.9 seconds |
| Started | Oct 09 05:37:58 AM UTC 24 |
| Finished | Oct 09 05:38:01 AM UTC 24 |
| Peak memory | 203408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239699749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.uart_smoke.4239699749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_stress_all.2492367636 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 430728963050 ps |
| CPU time | 1858.31 seconds |
| Started | Oct 09 05:38:27 AM UTC 24 |
| Finished | Oct 09 06:09:46 AM UTC 24 |
| Peak memory | 223312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492367636 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2492367636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.2942992020 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 10470213843 ps |
| CPU time | 47.5 seconds |
| Started | Oct 09 05:38:27 AM UTC 24 |
| Finished | Oct 09 05:39:17 AM UTC 24 |
| Peak memory | 226464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2942992020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all _with_rand_reset.2942992020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.3980505685 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 433226241 ps |
| CPU time | 2.31 seconds |
| Started | Oct 09 05:38:21 AM UTC 24 |
| Finished | Oct 09 05:38:24 AM UTC 24 |
| Peak memory | 203740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980505685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3980505685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_tx_rx.1878073853 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 87274854074 ps |
| CPU time | 76.51 seconds |
| Started | Oct 09 05:37:59 AM UTC 24 |
| Finished | Oct 09 05:39:17 AM UTC 24 |
| Peak memory | 206064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878073853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1878073853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/261.uart_fifo_reset.1341107706 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 13043818596 ps |
| CPU time | 44.51 seconds |
| Started | Oct 09 06:00:34 AM UTC 24 |
| Finished | Oct 09 06:01:20 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341107706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1341107706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/261.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2336762246 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 150697585085 ps |
| CPU time | 227.78 seconds |
| Started | Oct 09 06:00:36 AM UTC 24 |
| Finished | Oct 09 06:04:27 AM UTC 24 |
| Peak memory | 209512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336762246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2336762246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/262.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/263.uart_fifo_reset.81055482 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 17440422331 ps |
| CPU time | 46.1 seconds |
| Started | Oct 09 06:00:40 AM UTC 24 |
| Finished | Oct 09 06:01:28 AM UTC 24 |
| Peak memory | 209768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81055482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.81055482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/263.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/264.uart_fifo_reset.69605924 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 69874889837 ps |
| CPU time | 81.16 seconds |
| Started | Oct 09 06:00:42 AM UTC 24 |
| Finished | Oct 09 06:02:05 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69605924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.69605924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/264.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/265.uart_fifo_reset.554061785 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 74095703009 ps |
| CPU time | 46.16 seconds |
| Started | Oct 09 06:00:45 AM UTC 24 |
| Finished | Oct 09 06:01:33 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554061785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.554061785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/265.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3242446882 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 31998440476 ps |
| CPU time | 63.27 seconds |
| Started | Oct 09 06:00:46 AM UTC 24 |
| Finished | Oct 09 06:01:51 AM UTC 24 |
| Peak memory | 209740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242446882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3242446882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/266.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/267.uart_fifo_reset.2154537614 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 53259332698 ps |
| CPU time | 28.86 seconds |
| Started | Oct 09 06:00:47 AM UTC 24 |
| Finished | Oct 09 06:01:18 AM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154537614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2154537614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/267.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/268.uart_fifo_reset.2949911138 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 29310899430 ps |
| CPU time | 29.91 seconds |
| Started | Oct 09 06:00:50 AM UTC 24 |
| Finished | Oct 09 06:01:21 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949911138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2949911138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/268.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/269.uart_fifo_reset.2320486780 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 10094533723 ps |
| CPU time | 34.85 seconds |
| Started | Oct 09 06:00:52 AM UTC 24 |
| Finished | Oct 09 06:01:28 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320486780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2320486780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/269.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_alert_test.3168470871 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 11054465 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 05:39:02 AM UTC 24 |
| Finished | Oct 09 05:39:04 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168470871 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3168470871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_fifo_full.1135362357 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 72442697524 ps |
| CPU time | 172.89 seconds |
| Started | Oct 09 05:38:32 AM UTC 24 |
| Finished | Oct 09 05:41:28 AM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135362357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1135362357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.1162695109 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 45776287885 ps |
| CPU time | 49.23 seconds |
| Started | Oct 09 05:38:32 AM UTC 24 |
| Finished | Oct 09 05:39:23 AM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162695109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1162695109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_fifo_reset.1649489887 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 33025352682 ps |
| CPU time | 35.92 seconds |
| Started | Oct 09 05:38:34 AM UTC 24 |
| Finished | Oct 09 05:39:11 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649489887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1649489887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_intr.3018436242 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 72349973098 ps |
| CPU time | 149.21 seconds |
| Started | Oct 09 05:38:39 AM UTC 24 |
| Finished | Oct 09 05:41:11 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018436242 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3018436242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.1811759454 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 224623987237 ps |
| CPU time | 334.54 seconds |
| Started | Oct 09 05:38:57 AM UTC 24 |
| Finished | Oct 09 05:44:36 AM UTC 24 |
| Peak memory | 209548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811759454 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1811759454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_loopback.2552048609 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 779152529 ps |
| CPU time | 5.09 seconds |
| Started | Oct 09 05:38:50 AM UTC 24 |
| Finished | Oct 09 05:38:56 AM UTC 24 |
| Peak memory | 203736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552048609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2552048609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_noise_filter.1439373703 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 24299579340 ps |
| CPU time | 47.7 seconds |
| Started | Oct 09 05:38:42 AM UTC 24 |
| Finished | Oct 09 05:39:31 AM UTC 24 |
| Peak memory | 209704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439373703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1439373703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_perf.2885109514 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 14194782661 ps |
| CPU time | 201 seconds |
| Started | Oct 09 05:38:57 AM UTC 24 |
| Finished | Oct 09 05:42:21 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885109514 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2885109514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_rx_oversample.1793393363 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 1975044425 ps |
| CPU time | 4.85 seconds |
| Started | Oct 09 05:38:35 AM UTC 24 |
| Finished | Oct 09 05:38:41 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793393363 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1793393363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.3303508396 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 28589190118 ps |
| CPU time | 48.92 seconds |
| Started | Oct 09 05:38:45 AM UTC 24 |
| Finished | Oct 09 05:39:36 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303508396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3303508396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.4176132277 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2032651769 ps |
| CPU time | 10.31 seconds |
| Started | Oct 09 05:38:44 AM UTC 24 |
| Finished | Oct 09 05:38:56 AM UTC 24 |
| Peak memory | 203988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176132277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.4176132277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_smoke.2497990797 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 841244799 ps |
| CPU time | 7.03 seconds |
| Started | Oct 09 05:38:31 AM UTC 24 |
| Finished | Oct 09 05:38:39 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497990797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2497990797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_stress_all.1179387602 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 140061824454 ps |
| CPU time | 380.41 seconds |
| Started | Oct 09 05:38:59 AM UTC 24 |
| Finished | Oct 09 05:45:25 AM UTC 24 |
| Peak memory | 208092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179387602 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1179387602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.4192246201 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3395344714 ps |
| CPU time | 44.07 seconds |
| Started | Oct 09 05:38:57 AM UTC 24 |
| Finished | Oct 09 05:39:43 AM UTC 24 |
| Peak memory | 218708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4192246201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all _with_rand_reset.4192246201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.602932416 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 6541093529 ps |
| CPU time | 21.33 seconds |
| Started | Oct 09 05:38:49 AM UTC 24 |
| Finished | Oct 09 05:39:11 AM UTC 24 |
| Peak memory | 204088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602932416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.602932416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_tx_rx.947851264 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 68779477801 ps |
| CPU time | 161.09 seconds |
| Started | Oct 09 05:38:31 AM UTC 24 |
| Finished | Oct 09 05:41:14 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947851264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.947851264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/27.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/272.uart_fifo_reset.3721860120 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 34012440501 ps |
| CPU time | 64.53 seconds |
| Started | Oct 09 06:00:56 AM UTC 24 |
| Finished | Oct 09 06:02:02 AM UTC 24 |
| Peak memory | 209240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721860120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3721860120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/272.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/274.uart_fifo_reset.912691352 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 94303189318 ps |
| CPU time | 111.4 seconds |
| Started | Oct 09 06:01:00 AM UTC 24 |
| Finished | Oct 09 06:02:54 AM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912691352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.912691352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/274.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/276.uart_fifo_reset.2653878945 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 10877780999 ps |
| CPU time | 27.54 seconds |
| Started | Oct 09 06:01:01 AM UTC 24 |
| Finished | Oct 09 06:01:30 AM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653878945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2653878945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/276.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/277.uart_fifo_reset.3160812329 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 130912936322 ps |
| CPU time | 217.6 seconds |
| Started | Oct 09 06:01:05 AM UTC 24 |
| Finished | Oct 09 06:04:45 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160812329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3160812329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/277.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/279.uart_fifo_reset.1602832890 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 39906513087 ps |
| CPU time | 36.04 seconds |
| Started | Oct 09 06:01:12 AM UTC 24 |
| Finished | Oct 09 06:01:49 AM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602832890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1602832890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/279.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_alert_test.180134408 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 47408138 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 05:39:31 AM UTC 24 |
| Finished | Oct 09 05:39:34 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180134408 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.180134408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_fifo_full.1745804678 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 16656531441 ps |
| CPU time | 58.47 seconds |
| Started | Oct 09 05:39:08 AM UTC 24 |
| Finished | Oct 09 05:40:08 AM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745804678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1745804678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.2866815145 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 295489197035 ps |
| CPU time | 368.97 seconds |
| Started | Oct 09 05:39:08 AM UTC 24 |
| Finished | Oct 09 05:45:22 AM UTC 24 |
| Peak memory | 209448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866815145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2866815145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_fifo_reset.2689818563 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 48275710536 ps |
| CPU time | 52.73 seconds |
| Started | Oct 09 05:39:08 AM UTC 24 |
| Finished | Oct 09 05:40:02 AM UTC 24 |
| Peak memory | 204232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689818563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2689818563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_intr.1007658514 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 26900657579 ps |
| CPU time | 39.18 seconds |
| Started | Oct 09 05:39:12 AM UTC 24 |
| Finished | Oct 09 05:39:53 AM UTC 24 |
| Peak memory | 209780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007658514 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1007658514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.3166500722 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 149971331109 ps |
| CPU time | 947.21 seconds |
| Started | Oct 09 05:39:26 AM UTC 24 |
| Finished | Oct 09 05:55:25 AM UTC 24 |
| Peak memory | 207380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166500722 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3166500722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_loopback.2572466417 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 843252909 ps |
| CPU time | 2.42 seconds |
| Started | Oct 09 05:39:24 AM UTC 24 |
| Finished | Oct 09 05:39:27 AM UTC 24 |
| Peak memory | 205712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572466417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2572466417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_noise_filter.3282599573 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 65192586507 ps |
| CPU time | 55.93 seconds |
| Started | Oct 09 05:39:12 AM UTC 24 |
| Finished | Oct 09 05:40:10 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282599573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3282599573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_perf.2716367132 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 27868608216 ps |
| CPU time | 1604.99 seconds |
| Started | Oct 09 05:39:24 AM UTC 24 |
| Finished | Oct 09 06:06:27 AM UTC 24 |
| Peak memory | 207772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716367132 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2716367132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_rx_oversample.3338978693 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2605674728 ps |
| CPU time | 22.43 seconds |
| Started | Oct 09 05:39:09 AM UTC 24 |
| Finished | Oct 09 05:39:33 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338978693 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3338978693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.3901842958 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 42218168120 ps |
| CPU time | 34.59 seconds |
| Started | Oct 09 05:39:18 AM UTC 24 |
| Finished | Oct 09 05:39:54 AM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901842958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3901842958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.6483417 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 5427055203 ps |
| CPU time | 3.86 seconds |
| Started | Oct 09 05:39:17 AM UTC 24 |
| Finished | Oct 09 05:39:22 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6483417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.6483417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_smoke.224639018 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 648599101 ps |
| CPU time | 2.89 seconds |
| Started | Oct 09 05:39:04 AM UTC 24 |
| Finished | Oct 09 05:39:08 AM UTC 24 |
| Peak memory | 204268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224639018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 28.uart_smoke.224639018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.1261386812 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 6308399316 ps |
| CPU time | 37.42 seconds |
| Started | Oct 09 05:39:28 AM UTC 24 |
| Finished | Oct 09 05:40:07 AM UTC 24 |
| Peak memory | 218648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1261386812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all _with_rand_reset.1261386812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.4140580059 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1158463072 ps |
| CPU time | 7.17 seconds |
| Started | Oct 09 05:39:20 AM UTC 24 |
| Finished | Oct 09 05:39:29 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140580059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4140580059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_tx_rx.632989147 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 108409241294 ps |
| CPU time | 71.66 seconds |
| Started | Oct 09 05:39:06 AM UTC 24 |
| Finished | Oct 09 05:40:19 AM UTC 24 |
| Peak memory | 209504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632989147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.632989147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/28.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/280.uart_fifo_reset.3934482328 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 140989390873 ps |
| CPU time | 63.39 seconds |
| Started | Oct 09 06:01:13 AM UTC 24 |
| Finished | Oct 09 06:02:18 AM UTC 24 |
| Peak memory | 209464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934482328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3934482328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/280.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/281.uart_fifo_reset.1378855043 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 127872761791 ps |
| CPU time | 226.86 seconds |
| Started | Oct 09 06:01:15 AM UTC 24 |
| Finished | Oct 09 06:05:05 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378855043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1378855043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/281.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/282.uart_fifo_reset.735408574 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 111370318595 ps |
| CPU time | 235.56 seconds |
| Started | Oct 09 06:01:18 AM UTC 24 |
| Finished | Oct 09 06:05:17 AM UTC 24 |
| Peak memory | 209548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735408574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.735408574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/282.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/283.uart_fifo_reset.1648273006 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 140759708245 ps |
| CPU time | 263.46 seconds |
| Started | Oct 09 06:01:19 AM UTC 24 |
| Finished | Oct 09 06:05:46 AM UTC 24 |
| Peak memory | 205472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648273006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1648273006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/283.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/284.uart_fifo_reset.772629243 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 67895064176 ps |
| CPU time | 129.67 seconds |
| Started | Oct 09 06:01:19 AM UTC 24 |
| Finished | Oct 09 06:03:31 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772629243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.772629243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/284.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/285.uart_fifo_reset.2575687452 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 170139697969 ps |
| CPU time | 352.07 seconds |
| Started | Oct 09 06:01:20 AM UTC 24 |
| Finished | Oct 09 06:07:17 AM UTC 24 |
| Peak memory | 207648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575687452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2575687452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/285.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/286.uart_fifo_reset.1300725253 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 54969970580 ps |
| CPU time | 122.88 seconds |
| Started | Oct 09 06:01:21 AM UTC 24 |
| Finished | Oct 09 06:03:27 AM UTC 24 |
| Peak memory | 209472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300725253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1300725253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/286.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/287.uart_fifo_reset.1856612798 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 26826257144 ps |
| CPU time | 17.25 seconds |
| Started | Oct 09 06:01:25 AM UTC 24 |
| Finished | Oct 09 06:01:44 AM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856612798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1856612798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/287.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/288.uart_fifo_reset.503327801 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 97012260493 ps |
| CPU time | 220.12 seconds |
| Started | Oct 09 06:01:25 AM UTC 24 |
| Finished | Oct 09 06:05:09 AM UTC 24 |
| Peak memory | 204136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503327801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.503327801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/288.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/289.uart_fifo_reset.911767622 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 60752398482 ps |
| CPU time | 119.54 seconds |
| Started | Oct 09 06:01:29 AM UTC 24 |
| Finished | Oct 09 06:03:31 AM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911767622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.911767622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/289.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_alert_test.2216595929 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 22345446 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 05:40:09 AM UTC 24 |
| Finished | Oct 09 05:40:11 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216595929 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2216595929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_fifo_full.3650122686 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 167953282626 ps |
| CPU time | 276.69 seconds |
| Started | Oct 09 05:39:34 AM UTC 24 |
| Finished | Oct 09 05:44:15 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650122686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3650122686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.824929606 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 40487199225 ps |
| CPU time | 32.95 seconds |
| Started | Oct 09 05:39:37 AM UTC 24 |
| Finished | Oct 09 05:40:12 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824929606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.824929606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_fifo_reset.3867689209 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 84147340596 ps |
| CPU time | 219.77 seconds |
| Started | Oct 09 05:39:37 AM UTC 24 |
| Finished | Oct 09 05:43:21 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867689209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3867689209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_intr.1091755790 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 19011196344 ps |
| CPU time | 67.3 seconds |
| Started | Oct 09 05:39:44 AM UTC 24 |
| Finished | Oct 09 05:40:53 AM UTC 24 |
| Peak memory | 203996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091755790 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1091755790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.3868245346 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 162804928959 ps |
| CPU time | 426.93 seconds |
| Started | Oct 09 05:40:06 AM UTC 24 |
| Finished | Oct 09 05:47:19 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868245346 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3868245346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_loopback.208179239 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 6976155917 ps |
| CPU time | 21.01 seconds |
| Started | Oct 09 05:40:03 AM UTC 24 |
| Finished | Oct 09 05:40:25 AM UTC 24 |
| Peak memory | 204324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208179239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.uart_loopback.208179239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_noise_filter.4045888743 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 104099399357 ps |
| CPU time | 124.25 seconds |
| Started | Oct 09 05:39:54 AM UTC 24 |
| Finished | Oct 09 05:42:01 AM UTC 24 |
| Peak memory | 220516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045888743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.4045888743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_perf.1139630451 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 26094582083 ps |
| CPU time | 461.13 seconds |
| Started | Oct 09 05:40:05 AM UTC 24 |
| Finished | Oct 09 05:47:53 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139630451 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1139630451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_rx_oversample.1818252189 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 7934241430 ps |
| CPU time | 106.12 seconds |
| Started | Oct 09 05:39:39 AM UTC 24 |
| Finished | Oct 09 05:41:28 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818252189 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1818252189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.2368781882 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 37837897648 ps |
| CPU time | 75.99 seconds |
| Started | Oct 09 05:39:58 AM UTC 24 |
| Finished | Oct 09 05:41:16 AM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368781882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2368781882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.2196398122 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 40951416405 ps |
| CPU time | 22.38 seconds |
| Started | Oct 09 05:39:55 AM UTC 24 |
| Finished | Oct 09 05:40:19 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196398122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2196398122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_smoke.1568203769 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 121607739 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 05:39:32 AM UTC 24 |
| Finished | Oct 09 05:39:35 AM UTC 24 |
| Peak memory | 203344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568203769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1568203769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_stress_all.883805713 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 7112742864 ps |
| CPU time | 18.46 seconds |
| Started | Oct 09 05:40:08 AM UTC 24 |
| Finished | Oct 09 05:40:27 AM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883805713 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.883805713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.2674010694 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 24914884799 ps |
| CPU time | 83.86 seconds |
| Started | Oct 09 05:40:08 AM UTC 24 |
| Finished | Oct 09 05:41:33 AM UTC 24 |
| Peak memory | 222816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2674010694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all _with_rand_reset.2674010694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.2302899204 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 847226386 ps |
| CPU time | 2.27 seconds |
| Started | Oct 09 05:40:03 AM UTC 24 |
| Finished | Oct 09 05:40:07 AM UTC 24 |
| Peak memory | 203936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302899204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2302899204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_tx_rx.1083702079 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 80227971209 ps |
| CPU time | 86.49 seconds |
| Started | Oct 09 05:39:33 AM UTC 24 |
| Finished | Oct 09 05:41:02 AM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083702079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1083702079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/29.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/290.uart_fifo_reset.1928173768 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 85448989278 ps |
| CPU time | 154.4 seconds |
| Started | Oct 09 06:01:29 AM UTC 24 |
| Finished | Oct 09 06:04:06 AM UTC 24 |
| Peak memory | 204120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928173768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1928173768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/290.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/291.uart_fifo_reset.3203376782 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 92453534762 ps |
| CPU time | 40.26 seconds |
| Started | Oct 09 06:01:31 AM UTC 24 |
| Finished | Oct 09 06:02:13 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203376782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3203376782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/291.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/292.uart_fifo_reset.4128414538 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 164271743130 ps |
| CPU time | 64.18 seconds |
| Started | Oct 09 06:01:34 AM UTC 24 |
| Finished | Oct 09 06:02:40 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128414538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4128414538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/292.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/293.uart_fifo_reset.3637220491 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 174301056874 ps |
| CPU time | 162.56 seconds |
| Started | Oct 09 06:01:35 AM UTC 24 |
| Finished | Oct 09 06:04:20 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637220491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3637220491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/293.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/294.uart_fifo_reset.274297502 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 8573515531 ps |
| CPU time | 16.94 seconds |
| Started | Oct 09 06:01:40 AM UTC 24 |
| Finished | Oct 09 06:01:59 AM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274297502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.274297502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/294.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/295.uart_fifo_reset.4096493347 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 31290663629 ps |
| CPU time | 15.36 seconds |
| Started | Oct 09 06:01:43 AM UTC 24 |
| Finished | Oct 09 06:02:00 AM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096493347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.4096493347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/295.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/296.uart_fifo_reset.1403982794 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 108528102259 ps |
| CPU time | 84.05 seconds |
| Started | Oct 09 06:01:44 AM UTC 24 |
| Finished | Oct 09 06:03:10 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403982794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1403982794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/296.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/297.uart_fifo_reset.1674969859 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 233457490806 ps |
| CPU time | 907.55 seconds |
| Started | Oct 09 06:01:45 AM UTC 24 |
| Finished | Oct 09 06:17:03 AM UTC 24 |
| Peak memory | 213272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674969859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1674969859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/297.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3319497295 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 220044479363 ps |
| CPU time | 129.63 seconds |
| Started | Oct 09 06:01:49 AM UTC 24 |
| Finished | Oct 09 06:04:01 AM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319497295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3319497295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/299.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_alert_test.1930079298 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 13798098 ps |
| CPU time | 0.94 seconds |
| Started | Oct 09 05:27:17 AM UTC 24 |
| Finished | Oct 09 05:27:19 AM UTC 24 |
| Peak memory | 203408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930079298 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1930079298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_fifo_full.93277875 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 92714306346 ps |
| CPU time | 203.74 seconds |
| Started | Oct 09 05:27:03 AM UTC 24 |
| Finished | Oct 09 05:30:29 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93277875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.93277875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.465225913 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 23724360886 ps |
| CPU time | 46.22 seconds |
| Started | Oct 09 05:27:05 AM UTC 24 |
| Finished | Oct 09 05:27:53 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465225913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.465225913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_fifo_reset.4149669657 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 62509035512 ps |
| CPU time | 26.32 seconds |
| Started | Oct 09 05:27:05 AM UTC 24 |
| Finished | Oct 09 05:27:33 AM UTC 24 |
| Peak memory | 209380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149669657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4149669657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_intr.1598153262 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7101181995 ps |
| CPU time | 4.78 seconds |
| Started | Oct 09 05:27:07 AM UTC 24 |
| Finished | Oct 09 05:27:13 AM UTC 24 |
| Peak memory | 203792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598153262 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1598153262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.757772782 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 165172306192 ps |
| CPU time | 600.55 seconds |
| Started | Oct 09 05:27:15 AM UTC 24 |
| Finished | Oct 09 05:37:23 AM UTC 24 |
| Peak memory | 209416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757772782 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.757772782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_loopback.74649293 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 543689406 ps |
| CPU time | 2.99 seconds |
| Started | Oct 09 05:27:12 AM UTC 24 |
| Finished | Oct 09 05:27:17 AM UTC 24 |
| Peak memory | 203668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74649293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.uart_loopback.74649293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_noise_filter.2136462748 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 118234616704 ps |
| CPU time | 248.95 seconds |
| Started | Oct 09 05:27:07 AM UTC 24 |
| Finished | Oct 09 05:31:21 AM UTC 24 |
| Peak memory | 209692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136462748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2136462748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_rx_oversample.568392199 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4883917131 ps |
| CPU time | 39.84 seconds |
| Started | Oct 09 05:27:07 AM UTC 24 |
| Finished | Oct 09 05:27:49 AM UTC 24 |
| Peak memory | 204076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568392199 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.568392199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.3715420733 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 100131049682 ps |
| CPU time | 46.59 seconds |
| Started | Oct 09 05:27:12 AM UTC 24 |
| Finished | Oct 09 05:28:01 AM UTC 24 |
| Peak memory | 209708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715420733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3715420733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.1281368466 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1982220787 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 05:27:10 AM UTC 24 |
| Finished | Oct 09 05:27:15 AM UTC 24 |
| Peak memory | 203736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281368466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1281368466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_sec_cm.490345884 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 128939553 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 05:27:17 AM UTC 24 |
| Finished | Oct 09 05:27:19 AM UTC 24 |
| Peak memory | 235556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490345884 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.490345884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_smoke.3484572269 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 406832840 ps |
| CPU time | 3.02 seconds |
| Started | Oct 09 05:27:01 AM UTC 24 |
| Finished | Oct 09 05:27:05 AM UTC 24 |
| Peak memory | 204148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484572269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3484572269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_stress_all.1996605834 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 304048067126 ps |
| CPU time | 1206.09 seconds |
| Started | Oct 09 05:27:17 AM UTC 24 |
| Finished | Oct 09 05:47:38 AM UTC 24 |
| Peak memory | 213268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996605834 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1996605834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.2620903782 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4116839005 ps |
| CPU time | 14.55 seconds |
| Started | Oct 09 05:27:15 AM UTC 24 |
| Finished | Oct 09 05:27:31 AM UTC 24 |
| Peak memory | 218720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2620903782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_ with_rand_reset.2620903782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.1569556056 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 7523812391 ps |
| CPU time | 9.78 seconds |
| Started | Oct 09 05:27:12 AM UTC 24 |
| Finished | Oct 09 05:27:24 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569556056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1569556056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_tx_rx.2165742049 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 32895183950 ps |
| CPU time | 22.74 seconds |
| Started | Oct 09 05:27:01 AM UTC 24 |
| Finished | Oct 09 05:27:25 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165742049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2165742049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/3.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_alert_test.1907460629 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 88227190 ps |
| CPU time | 0.88 seconds |
| Started | Oct 09 05:41:11 AM UTC 24 |
| Finished | Oct 09 05:41:12 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907460629 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1907460629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_fifo_full.2447591691 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 34026578234 ps |
| CPU time | 86.31 seconds |
| Started | Oct 09 05:40:13 AM UTC 24 |
| Finished | Oct 09 05:41:41 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447591691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2447591691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.2549612681 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 117031401855 ps |
| CPU time | 239.78 seconds |
| Started | Oct 09 05:40:20 AM UTC 24 |
| Finished | Oct 09 05:44:23 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549612681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2549612681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_fifo_reset.1774224943 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 58444656070 ps |
| CPU time | 41.42 seconds |
| Started | Oct 09 05:40:20 AM UTC 24 |
| Finished | Oct 09 05:41:03 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774224943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1774224943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_intr.2125707120 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 33382370212 ps |
| CPU time | 59.12 seconds |
| Started | Oct 09 05:40:26 AM UTC 24 |
| Finished | Oct 09 05:41:27 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125707120 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2125707120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.3636908677 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 81007421977 ps |
| CPU time | 594.92 seconds |
| Started | Oct 09 05:41:03 AM UTC 24 |
| Finished | Oct 09 05:51:06 AM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636908677 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3636908677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_loopback.2390359287 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 5753504005 ps |
| CPU time | 22.21 seconds |
| Started | Oct 09 05:40:46 AM UTC 24 |
| Finished | Oct 09 05:41:10 AM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390359287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2390359287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_noise_filter.2431771820 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 125519142685 ps |
| CPU time | 91.27 seconds |
| Started | Oct 09 05:40:28 AM UTC 24 |
| Finished | Oct 09 05:42:02 AM UTC 24 |
| Peak memory | 220640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431771820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2431771820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_perf.98274551 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 15218290186 ps |
| CPU time | 977.62 seconds |
| Started | Oct 09 05:40:54 AM UTC 24 |
| Finished | Oct 09 05:57:24 AM UTC 24 |
| Peak memory | 207644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98274551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.98274551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_rx_oversample.1471495757 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 6939499457 ps |
| CPU time | 71.04 seconds |
| Started | Oct 09 05:40:23 AM UTC 24 |
| Finished | Oct 09 05:41:36 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471495757 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1471495757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.2442611584 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 167524052072 ps |
| CPU time | 350.29 seconds |
| Started | Oct 09 05:40:37 AM UTC 24 |
| Finished | Oct 09 05:46:31 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442611584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2442611584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.1048685011 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2962994407 ps |
| CPU time | 3.93 seconds |
| Started | Oct 09 05:40:34 AM UTC 24 |
| Finished | Oct 09 05:40:39 AM UTC 24 |
| Peak memory | 203924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048685011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1048685011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_smoke.2430569399 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 6016387148 ps |
| CPU time | 23.25 seconds |
| Started | Oct 09 05:40:11 AM UTC 24 |
| Finished | Oct 09 05:40:35 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430569399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2430569399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_stress_all.1896038034 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 182558884965 ps |
| CPU time | 213.47 seconds |
| Started | Oct 09 05:41:04 AM UTC 24 |
| Finished | Oct 09 05:44:41 AM UTC 24 |
| Peak memory | 220572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896038034 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1896038034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.2939854751 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 9956208988 ps |
| CPU time | 35.16 seconds |
| Started | Oct 09 05:41:03 AM UTC 24 |
| Finished | Oct 09 05:41:40 AM UTC 24 |
| Peak memory | 220444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2939854751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all _with_rand_reset.2939854751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.725104374 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2172326043 ps |
| CPU time | 4.34 seconds |
| Started | Oct 09 05:40:40 AM UTC 24 |
| Finished | Oct 09 05:40:45 AM UTC 24 |
| Peak memory | 204272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725104374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.725104374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_tx_rx.2165768920 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 73435528634 ps |
| CPU time | 217 seconds |
| Started | Oct 09 05:40:12 AM UTC 24 |
| Finished | Oct 09 05:43:52 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165768920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2165768920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/30.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_alert_test.413868067 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 11485679 ps |
| CPU time | 0.89 seconds |
| Started | Oct 09 05:41:37 AM UTC 24 |
| Finished | Oct 09 05:41:39 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413868067 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.413868067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_fifo_full.1583918644 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 49094323876 ps |
| CPU time | 83.45 seconds |
| Started | Oct 09 05:41:14 AM UTC 24 |
| Finished | Oct 09 05:42:39 AM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583918644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1583918644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.1910375015 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 87516751723 ps |
| CPU time | 37.83 seconds |
| Started | Oct 09 05:41:15 AM UTC 24 |
| Finished | Oct 09 05:41:54 AM UTC 24 |
| Peak memory | 209680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910375015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1910375015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_fifo_reset.393080376 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 79079444388 ps |
| CPU time | 196.68 seconds |
| Started | Oct 09 05:41:17 AM UTC 24 |
| Finished | Oct 09 05:44:37 AM UTC 24 |
| Peak memory | 209744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393080376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.393080376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_intr.4137091517 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 35784951691 ps |
| CPU time | 51.01 seconds |
| Started | Oct 09 05:41:21 AM UTC 24 |
| Finished | Oct 09 05:42:14 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137091517 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.4137091517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.3426693613 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 69852478196 ps |
| CPU time | 763.97 seconds |
| Started | Oct 09 05:41:34 AM UTC 24 |
| Finished | Oct 09 05:54:28 AM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426693613 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3426693613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_loopback.2508157696 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 15654719334 ps |
| CPU time | 9.43 seconds |
| Started | Oct 09 05:41:30 AM UTC 24 |
| Finished | Oct 09 05:41:40 AM UTC 24 |
| Peak memory | 204400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508157696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2508157696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_noise_filter.2076768744 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 68086595564 ps |
| CPU time | 149.99 seconds |
| Started | Oct 09 05:41:24 AM UTC 24 |
| Finished | Oct 09 05:43:57 AM UTC 24 |
| Peak memory | 209704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076768744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2076768744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_perf.583796236 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 14615672314 ps |
| CPU time | 378.47 seconds |
| Started | Oct 09 05:41:31 AM UTC 24 |
| Finished | Oct 09 05:47:55 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583796236 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.583796236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_rx_oversample.2184582257 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 6421137460 ps |
| CPU time | 7.15 seconds |
| Started | Oct 09 05:41:20 AM UTC 24 |
| Finished | Oct 09 05:41:28 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184582257 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2184582257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.414114816 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 100753170331 ps |
| CPU time | 103.95 seconds |
| Started | Oct 09 05:41:28 AM UTC 24 |
| Finished | Oct 09 05:43:14 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414114816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.414114816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.3044869421 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2987076574 ps |
| CPU time | 5.78 seconds |
| Started | Oct 09 05:41:28 AM UTC 24 |
| Finished | Oct 09 05:41:35 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044869421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3044869421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_smoke.420031751 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 5471475863 ps |
| CPU time | 17.06 seconds |
| Started | Oct 09 05:41:12 AM UTC 24 |
| Finished | Oct 09 05:41:30 AM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420031751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 31.uart_smoke.420031751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_stress_all.204144011 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 597517356179 ps |
| CPU time | 1522.71 seconds |
| Started | Oct 09 05:41:36 AM UTC 24 |
| Finished | Oct 09 06:07:15 AM UTC 24 |
| Peak memory | 223240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204144011 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.204144011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.1297339723 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 3271200707 ps |
| CPU time | 58.49 seconds |
| Started | Oct 09 05:41:35 AM UTC 24 |
| Finished | Oct 09 05:42:35 AM UTC 24 |
| Peak memory | 226088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1297339723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all _with_rand_reset.1297339723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.3879213306 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 894969089 ps |
| CPU time | 4.62 seconds |
| Started | Oct 09 05:41:29 AM UTC 24 |
| Finished | Oct 09 05:41:34 AM UTC 24 |
| Peak memory | 204148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879213306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3879213306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_tx_rx.3212306521 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 17157439221 ps |
| CPU time | 41.07 seconds |
| Started | Oct 09 05:41:14 AM UTC 24 |
| Finished | Oct 09 05:41:56 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212306521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3212306521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/31.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_alert_test.393372470 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 19180241 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 05:42:28 AM UTC 24 |
| Finished | Oct 09 05:42:30 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393372470 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.393372470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_fifo_full.2314097441 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 49563047731 ps |
| CPU time | 87.67 seconds |
| Started | Oct 09 05:41:41 AM UTC 24 |
| Finished | Oct 09 05:43:11 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314097441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2314097441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.109902988 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 129686772129 ps |
| CPU time | 104.05 seconds |
| Started | Oct 09 05:41:41 AM UTC 24 |
| Finished | Oct 09 05:43:27 AM UTC 24 |
| Peak memory | 209276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109902988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.109902988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_fifo_reset.2256762994 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 15734909178 ps |
| CPU time | 58.05 seconds |
| Started | Oct 09 05:41:42 AM UTC 24 |
| Finished | Oct 09 05:42:42 AM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256762994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2256762994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_intr.4015121745 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 190258415625 ps |
| CPU time | 157.85 seconds |
| Started | Oct 09 05:41:55 AM UTC 24 |
| Finished | Oct 09 05:44:36 AM UTC 24 |
| Peak memory | 208668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015121745 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4015121745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.4036472776 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 27103365020 ps |
| CPU time | 120.46 seconds |
| Started | Oct 09 05:42:14 AM UTC 24 |
| Finished | Oct 09 05:44:17 AM UTC 24 |
| Peak memory | 209680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036472776 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.4036472776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_loopback.3184540369 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2729463151 ps |
| CPU time | 2.25 seconds |
| Started | Oct 09 05:42:09 AM UTC 24 |
| Finished | Oct 09 05:42:12 AM UTC 24 |
| Peak memory | 205848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184540369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3184540369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_noise_filter.858072831 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 152688028708 ps |
| CPU time | 86.05 seconds |
| Started | Oct 09 05:41:57 AM UTC 24 |
| Finished | Oct 09 05:43:25 AM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858072831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.858072831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_perf.1347111953 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 7007973244 ps |
| CPU time | 69.7 seconds |
| Started | Oct 09 05:42:13 AM UTC 24 |
| Finished | Oct 09 05:43:25 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347111953 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1347111953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_rx_oversample.3714610983 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 4106622042 ps |
| CPU time | 44.88 seconds |
| Started | Oct 09 05:41:47 AM UTC 24 |
| Finished | Oct 09 05:42:33 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714610983 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3714610983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.991959729 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 139560492539 ps |
| CPU time | 201.55 seconds |
| Started | Oct 09 05:42:02 AM UTC 24 |
| Finished | Oct 09 05:45:27 AM UTC 24 |
| Peak memory | 209548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991959729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.991959729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.4076035475 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 43974774179 ps |
| CPU time | 79.34 seconds |
| Started | Oct 09 05:42:02 AM UTC 24 |
| Finished | Oct 09 05:43:23 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076035475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.4076035475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_smoke.2091737622 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 925644359 ps |
| CPU time | 6.75 seconds |
| Started | Oct 09 05:41:38 AM UTC 24 |
| Finished | Oct 09 05:41:46 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091737622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2091737622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_stress_all.4110482040 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 180830255329 ps |
| CPU time | 130.33 seconds |
| Started | Oct 09 05:42:23 AM UTC 24 |
| Finished | Oct 09 05:44:35 AM UTC 24 |
| Peak memory | 205960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110482040 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.4110482040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.1988568592 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 14850197267 ps |
| CPU time | 48.04 seconds |
| Started | Oct 09 05:42:20 AM UTC 24 |
| Finished | Oct 09 05:43:09 AM UTC 24 |
| Peak memory | 226508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1988568592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all _with_rand_reset.1988568592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.3425237489 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1976433006 ps |
| CPU time | 3.78 seconds |
| Started | Oct 09 05:42:03 AM UTC 24 |
| Finished | Oct 09 05:42:08 AM UTC 24 |
| Peak memory | 203936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425237489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3425237489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_tx_rx.3631729316 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 48180610129 ps |
| CPU time | 45.41 seconds |
| Started | Oct 09 05:41:40 AM UTC 24 |
| Finished | Oct 09 05:42:27 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631729316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3631729316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/32.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_alert_test.728854178 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 23948790 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 05:43:15 AM UTC 24 |
| Finished | Oct 09 05:43:17 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728854178 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.728854178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_fifo_full.1184467927 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 52731102432 ps |
| CPU time | 70.5 seconds |
| Started | Oct 09 05:42:36 AM UTC 24 |
| Finished | Oct 09 05:43:48 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184467927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1184467927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.1101995527 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 48665621414 ps |
| CPU time | 47.24 seconds |
| Started | Oct 09 05:42:36 AM UTC 24 |
| Finished | Oct 09 05:43:25 AM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101995527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1101995527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_fifo_reset.486602971 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 33181879425 ps |
| CPU time | 48.95 seconds |
| Started | Oct 09 05:42:36 AM UTC 24 |
| Finished | Oct 09 05:43:27 AM UTC 24 |
| Peak memory | 209404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486602971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.486602971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_intr.2066002416 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 12271828483 ps |
| CPU time | 43.71 seconds |
| Started | Oct 09 05:42:40 AM UTC 24 |
| Finished | Oct 09 05:43:26 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066002416 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2066002416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.908982473 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 85153822884 ps |
| CPU time | 587.44 seconds |
| Started | Oct 09 05:43:07 AM UTC 24 |
| Finished | Oct 09 05:53:02 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908982473 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.908982473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_loopback.4152649623 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 103438092 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 05:43:04 AM UTC 24 |
| Finished | Oct 09 05:43:07 AM UTC 24 |
| Peak memory | 203300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152649623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.4152649623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_noise_filter.3991855764 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 73820298112 ps |
| CPU time | 18.22 seconds |
| Started | Oct 09 05:42:43 AM UTC 24 |
| Finished | Oct 09 05:43:03 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991855764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3991855764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_perf.4127208189 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 13940363878 ps |
| CPU time | 993.48 seconds |
| Started | Oct 09 05:43:04 AM UTC 24 |
| Finished | Oct 09 05:59:49 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127208189 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.4127208189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_rx_oversample.885150891 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 5563185652 ps |
| CPU time | 7.82 seconds |
| Started | Oct 09 05:42:38 AM UTC 24 |
| Finished | Oct 09 05:42:47 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885150891 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.885150891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.1177275169 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 202970029937 ps |
| CPU time | 92.62 seconds |
| Started | Oct 09 05:42:50 AM UTC 24 |
| Finished | Oct 09 05:44:24 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177275169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1177275169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.2069538465 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 40450688482 ps |
| CPU time | 38.3 seconds |
| Started | Oct 09 05:42:48 AM UTC 24 |
| Finished | Oct 09 05:43:27 AM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069538465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2069538465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_smoke.4016594429 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 306757590 ps |
| CPU time | 2.69 seconds |
| Started | Oct 09 05:42:31 AM UTC 24 |
| Finished | Oct 09 05:42:35 AM UTC 24 |
| Peak memory | 203944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016594429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 33.uart_smoke.4016594429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_stress_all.3595086242 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 180874346679 ps |
| CPU time | 184.09 seconds |
| Started | Oct 09 05:43:12 AM UTC 24 |
| Finished | Oct 09 05:46:19 AM UTC 24 |
| Peak memory | 209660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595086242 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3595086242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.2856063150 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 12100289119 ps |
| CPU time | 49.16 seconds |
| Started | Oct 09 05:43:10 AM UTC 24 |
| Finished | Oct 09 05:44:01 AM UTC 24 |
| Peak memory | 220768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2856063150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all _with_rand_reset.2856063150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.2640337798 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1513490607 ps |
| CPU time | 3.43 seconds |
| Started | Oct 09 05:42:59 AM UTC 24 |
| Finished | Oct 09 05:43:03 AM UTC 24 |
| Peak memory | 203936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640337798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2640337798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_tx_rx.1959601368 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 18809872700 ps |
| CPU time | 13.3 seconds |
| Started | Oct 09 05:42:34 AM UTC 24 |
| Finished | Oct 09 05:42:48 AM UTC 24 |
| Peak memory | 208468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959601368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1959601368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/33.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_alert_test.3840566454 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 15121319 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 05:43:48 AM UTC 24 |
| Finished | Oct 09 05:43:50 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840566454 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3840566454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_fifo_full.3400831943 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 25610920829 ps |
| CPU time | 21.16 seconds |
| Started | Oct 09 05:43:24 AM UTC 24 |
| Finished | Oct 09 05:43:47 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400831943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3400831943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.395525155 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 77863071541 ps |
| CPU time | 110.94 seconds |
| Started | Oct 09 05:43:25 AM UTC 24 |
| Finished | Oct 09 05:45:18 AM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395525155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.395525155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_fifo_reset.2561544606 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 85466572325 ps |
| CPU time | 187.91 seconds |
| Started | Oct 09 05:43:26 AM UTC 24 |
| Finished | Oct 09 05:46:37 AM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561544606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2561544606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_intr.2400341308 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 62394117839 ps |
| CPU time | 40.66 seconds |
| Started | Oct 09 05:43:26 AM UTC 24 |
| Finished | Oct 09 05:44:09 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400341308 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2400341308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.3362788995 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 163552230015 ps |
| CPU time | 305.02 seconds |
| Started | Oct 09 05:43:34 AM UTC 24 |
| Finished | Oct 09 05:48:43 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362788995 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3362788995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_loopback.2505334801 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 5588542577 ps |
| CPU time | 15.83 seconds |
| Started | Oct 09 05:43:28 AM UTC 24 |
| Finished | Oct 09 05:43:46 AM UTC 24 |
| Peak memory | 208360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505334801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2505334801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_noise_filter.1409189492 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 225553811680 ps |
| CPU time | 88.76 seconds |
| Started | Oct 09 05:43:27 AM UTC 24 |
| Finished | Oct 09 05:44:58 AM UTC 24 |
| Peak memory | 218872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409189492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1409189492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_perf.3835415710 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 13517226027 ps |
| CPU time | 336.73 seconds |
| Started | Oct 09 05:43:30 AM UTC 24 |
| Finished | Oct 09 05:49:12 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835415710 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3835415710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_rx_oversample.2316875273 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2509502709 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 05:43:26 AM UTC 24 |
| Finished | Oct 09 05:43:29 AM UTC 24 |
| Peak memory | 203352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316875273 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2316875273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.2319415312 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 47929857116 ps |
| CPU time | 46.78 seconds |
| Started | Oct 09 05:43:28 AM UTC 24 |
| Finished | Oct 09 05:44:17 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319415312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2319415312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.1561169254 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 35815849271 ps |
| CPU time | 69.19 seconds |
| Started | Oct 09 05:43:28 AM UTC 24 |
| Finished | Oct 09 05:44:39 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561169254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1561169254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_smoke.1874278017 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 484352380 ps |
| CPU time | 2.37 seconds |
| Started | Oct 09 05:43:18 AM UTC 24 |
| Finished | Oct 09 05:43:22 AM UTC 24 |
| Peak memory | 203944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874278017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1874278017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_stress_all.3760220855 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 398016033715 ps |
| CPU time | 308.09 seconds |
| Started | Oct 09 05:43:47 AM UTC 24 |
| Finished | Oct 09 05:48:59 AM UTC 24 |
| Peak memory | 209484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760220855 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3760220855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.3289963079 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1586123016 ps |
| CPU time | 14.45 seconds |
| Started | Oct 09 05:43:38 AM UTC 24 |
| Finished | Oct 09 05:43:54 AM UTC 24 |
| Peak memory | 224816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3289963079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all _with_rand_reset.3289963079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.4025595055 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 6809251885 ps |
| CPU time | 33.44 seconds |
| Started | Oct 09 05:43:28 AM UTC 24 |
| Finished | Oct 09 05:44:03 AM UTC 24 |
| Peak memory | 204268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025595055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.4025595055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_tx_rx.596242068 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 141217914599 ps |
| CPU time | 14.39 seconds |
| Started | Oct 09 05:43:21 AM UTC 24 |
| Finished | Oct 09 05:43:37 AM UTC 24 |
| Peak memory | 209688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596242068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.596242068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/34.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_alert_test.2121783509 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 38710019 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:44:18 AM UTC 24 |
| Finished | Oct 09 05:44:20 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121783509 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2121783509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_fifo_full.1909309771 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 109147623245 ps |
| CPU time | 102.38 seconds |
| Started | Oct 09 05:43:51 AM UTC 24 |
| Finished | Oct 09 05:45:35 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909309771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1909309771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.1684840455 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 136749220857 ps |
| CPU time | 227.76 seconds |
| Started | Oct 09 05:43:52 AM UTC 24 |
| Finished | Oct 09 05:47:43 AM UTC 24 |
| Peak memory | 204128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684840455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1684840455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_fifo_reset.1316729532 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 29924759197 ps |
| CPU time | 23.79 seconds |
| Started | Oct 09 05:43:53 AM UTC 24 |
| Finished | Oct 09 05:44:18 AM UTC 24 |
| Peak memory | 209456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316729532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1316729532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_intr.3490810221 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 31179412357 ps |
| CPU time | 107.39 seconds |
| Started | Oct 09 05:43:55 AM UTC 24 |
| Finished | Oct 09 05:45:45 AM UTC 24 |
| Peak memory | 209240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490810221 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3490810221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.2268749537 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 185017325463 ps |
| CPU time | 176.66 seconds |
| Started | Oct 09 05:44:15 AM UTC 24 |
| Finished | Oct 09 05:47:15 AM UTC 24 |
| Peak memory | 203984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268749537 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2268749537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_loopback.3611828183 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 9162907529 ps |
| CPU time | 15.68 seconds |
| Started | Oct 09 05:44:10 AM UTC 24 |
| Finished | Oct 09 05:44:27 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611828183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3611828183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_noise_filter.3617545514 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 211891095037 ps |
| CPU time | 199.88 seconds |
| Started | Oct 09 05:43:58 AM UTC 24 |
| Finished | Oct 09 05:47:21 AM UTC 24 |
| Peak memory | 218856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617545514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3617545514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_perf.2124793607 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 14468258130 ps |
| CPU time | 426.79 seconds |
| Started | Oct 09 05:44:11 AM UTC 24 |
| Finished | Oct 09 05:51:23 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124793607 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2124793607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_rx_oversample.801164066 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 6766191530 ps |
| CPU time | 13.56 seconds |
| Started | Oct 09 05:43:55 AM UTC 24 |
| Finished | Oct 09 05:44:10 AM UTC 24 |
| Peak memory | 204076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801164066 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.801164066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.2127399199 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 108386246268 ps |
| CPU time | 45.82 seconds |
| Started | Oct 09 05:44:04 AM UTC 24 |
| Finished | Oct 09 05:44:51 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127399199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2127399199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.2514509708 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 3591615103 ps |
| CPU time | 6.19 seconds |
| Started | Oct 09 05:44:02 AM UTC 24 |
| Finished | Oct 09 05:44:09 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514509708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2514509708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_smoke.4072136895 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 769408638 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 05:43:48 AM UTC 24 |
| Finished | Oct 09 05:43:51 AM UTC 24 |
| Peak memory | 203360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072136895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.4072136895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_stress_all.54032120 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1186332825493 ps |
| CPU time | 276.56 seconds |
| Started | Oct 09 05:44:17 AM UTC 24 |
| Finished | Oct 09 05:48:58 AM UTC 24 |
| Peak memory | 218508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54032120 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.54032120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.3505699771 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 6107738286 ps |
| CPU time | 23.91 seconds |
| Started | Oct 09 05:44:16 AM UTC 24 |
| Finished | Oct 09 05:44:41 AM UTC 24 |
| Peak memory | 209924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3505699771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all _with_rand_reset.3505699771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.1001281108 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 1037541362 ps |
| CPU time | 2.96 seconds |
| Started | Oct 09 05:44:10 AM UTC 24 |
| Finished | Oct 09 05:44:14 AM UTC 24 |
| Peak memory | 208284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001281108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1001281108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_tx_rx.106489474 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 304456076040 ps |
| CPU time | 60.81 seconds |
| Started | Oct 09 05:43:49 AM UTC 24 |
| Finished | Oct 09 05:44:51 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106489474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.106489474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/35.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_alert_test.4127423301 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 32030140 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 05:44:52 AM UTC 24 |
| Finished | Oct 09 05:44:54 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127423301 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.4127423301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_fifo_full.3245352966 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 52350963566 ps |
| CPU time | 128.72 seconds |
| Started | Oct 09 05:44:24 AM UTC 24 |
| Finished | Oct 09 05:46:35 AM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245352966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3245352966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.3636194539 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 129932328593 ps |
| CPU time | 146.58 seconds |
| Started | Oct 09 05:44:25 AM UTC 24 |
| Finished | Oct 09 05:46:54 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636194539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3636194539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_fifo_reset.167158965 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 200737149984 ps |
| CPU time | 132.54 seconds |
| Started | Oct 09 05:44:25 AM UTC 24 |
| Finished | Oct 09 05:46:40 AM UTC 24 |
| Peak memory | 204136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167158965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.167158965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_intr.2668420559 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 248397720301 ps |
| CPU time | 101.27 seconds |
| Started | Oct 09 05:44:36 AM UTC 24 |
| Finished | Oct 09 05:46:19 AM UTC 24 |
| Peak memory | 203928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668420559 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2668420559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.2647584068 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 91084861766 ps |
| CPU time | 169.3 seconds |
| Started | Oct 09 05:44:47 AM UTC 24 |
| Finished | Oct 09 05:47:39 AM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647584068 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2647584068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_loopback.1437839535 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 168776795 ps |
| CPU time | 2.02 seconds |
| Started | Oct 09 05:44:42 AM UTC 24 |
| Finished | Oct 09 05:44:46 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437839535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1437839535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_noise_filter.2694873098 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 113388446323 ps |
| CPU time | 152.38 seconds |
| Started | Oct 09 05:44:37 AM UTC 24 |
| Finished | Oct 09 05:47:12 AM UTC 24 |
| Peak memory | 209764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694873098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2694873098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_perf.4179406993 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 10616485859 ps |
| CPU time | 268.49 seconds |
| Started | Oct 09 05:44:43 AM UTC 24 |
| Finished | Oct 09 05:49:15 AM UTC 24 |
| Peak memory | 209764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179406993 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4179406993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_rx_oversample.2452546470 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 4869692239 ps |
| CPU time | 46.18 seconds |
| Started | Oct 09 05:44:28 AM UTC 24 |
| Finished | Oct 09 05:45:16 AM UTC 24 |
| Peak memory | 204392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452546470 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2452546470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.348077400 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 50241196791 ps |
| CPU time | 90.87 seconds |
| Started | Oct 09 05:44:38 AM UTC 24 |
| Finished | Oct 09 05:46:11 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348077400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.348077400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.3932181247 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 41094367211 ps |
| CPU time | 43.27 seconds |
| Started | Oct 09 05:44:37 AM UTC 24 |
| Finished | Oct 09 05:45:22 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932181247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3932181247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_smoke.139509959 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 664630752 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 05:44:19 AM UTC 24 |
| Finished | Oct 09 05:44:22 AM UTC 24 |
| Peak memory | 203364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139509959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 36.uart_smoke.139509959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_stress_all.419523901 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 333275359273 ps |
| CPU time | 3017.04 seconds |
| Started | Oct 09 05:44:51 AM UTC 24 |
| Finished | Oct 09 06:35:43 AM UTC 24 |
| Peak memory | 213200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419523901 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.419523901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.3409154207 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 11051136180 ps |
| CPU time | 69.96 seconds |
| Started | Oct 09 05:44:47 AM UTC 24 |
| Finished | Oct 09 05:45:58 AM UTC 24 |
| Peak memory | 222376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3409154207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all _with_rand_reset.3409154207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.79102859 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 1277645947 ps |
| CPU time | 4.59 seconds |
| Started | Oct 09 05:44:40 AM UTC 24 |
| Finished | Oct 09 05:44:46 AM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79102859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.79102859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_tx_rx.4192382592 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 49379626963 ps |
| CPU time | 30.65 seconds |
| Started | Oct 09 05:44:22 AM UTC 24 |
| Finished | Oct 09 05:44:54 AM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192382592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.4192382592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/36.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_alert_test.1007976116 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 23158568 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:45:32 AM UTC 24 |
| Finished | Oct 09 05:45:35 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007976116 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1007976116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_fifo_full.1241233696 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 65219214271 ps |
| CPU time | 26.21 seconds |
| Started | Oct 09 05:44:55 AM UTC 24 |
| Finished | Oct 09 05:45:23 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241233696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1241233696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.2018079094 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 62916190632 ps |
| CPU time | 52.36 seconds |
| Started | Oct 09 05:44:57 AM UTC 24 |
| Finished | Oct 09 05:45:51 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018079094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2018079094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_fifo_reset.1536022697 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 36414455077 ps |
| CPU time | 83.49 seconds |
| Started | Oct 09 05:44:59 AM UTC 24 |
| Finished | Oct 09 05:46:25 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536022697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1536022697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_intr.723504816 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 15346677137 ps |
| CPU time | 14.15 seconds |
| Started | Oct 09 05:45:17 AM UTC 24 |
| Finished | Oct 09 05:45:32 AM UTC 24 |
| Peak memory | 208500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723504816 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.723504816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.1325392999 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 81921290348 ps |
| CPU time | 651.95 seconds |
| Started | Oct 09 05:45:27 AM UTC 24 |
| Finished | Oct 09 05:56:27 AM UTC 24 |
| Peak memory | 207448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325392999 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1325392999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_loopback.445834939 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 7483014021 ps |
| CPU time | 7.92 seconds |
| Started | Oct 09 05:45:24 AM UTC 24 |
| Finished | Oct 09 05:45:33 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445834939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 37.uart_loopback.445834939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_noise_filter.4036217142 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 45113036944 ps |
| CPU time | 51.37 seconds |
| Started | Oct 09 05:45:20 AM UTC 24 |
| Finished | Oct 09 05:46:13 AM UTC 24 |
| Peak memory | 208608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036217142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.4036217142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_perf.3878201397 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 9975390215 ps |
| CPU time | 578.61 seconds |
| Started | Oct 09 05:45:26 AM UTC 24 |
| Finished | Oct 09 05:55:12 AM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878201397 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3878201397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_rx_oversample.2171825301 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 3371296333 ps |
| CPU time | 18.77 seconds |
| Started | Oct 09 05:45:08 AM UTC 24 |
| Finished | Oct 09 05:45:29 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171825301 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2171825301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.1613000439 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 65446091308 ps |
| CPU time | 37.66 seconds |
| Started | Oct 09 05:45:23 AM UTC 24 |
| Finished | Oct 09 05:46:02 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613000439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1613000439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.2625823184 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1835923921 ps |
| CPU time | 7.62 seconds |
| Started | Oct 09 05:45:23 AM UTC 24 |
| Finished | Oct 09 05:45:32 AM UTC 24 |
| Peak memory | 203732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625823184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2625823184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_smoke.3357057813 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 508264585 ps |
| CPU time | 3.15 seconds |
| Started | Oct 09 05:44:52 AM UTC 24 |
| Finished | Oct 09 05:44:56 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357057813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3357057813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_stress_all.2216197128 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 270420857704 ps |
| CPU time | 849.73 seconds |
| Started | Oct 09 05:45:32 AM UTC 24 |
| Finished | Oct 09 05:59:53 AM UTC 24 |
| Peak memory | 213188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216197128 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2216197128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.3011635027 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 4291734735 ps |
| CPU time | 42.71 seconds |
| Started | Oct 09 05:45:29 AM UTC 24 |
| Finished | Oct 09 05:46:14 AM UTC 24 |
| Peak memory | 218536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3011635027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all _with_rand_reset.3011635027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.488831924 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 6825803395 ps |
| CPU time | 35.69 seconds |
| Started | Oct 09 05:45:24 AM UTC 24 |
| Finished | Oct 09 05:46:01 AM UTC 24 |
| Peak memory | 204076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488831924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.488831924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_tx_rx.3054973711 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 31583192374 ps |
| CPU time | 79 seconds |
| Started | Oct 09 05:44:54 AM UTC 24 |
| Finished | Oct 09 05:46:15 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054973711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3054973711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/37.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_alert_test.27376196 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 22475957 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:46:12 AM UTC 24 |
| Finished | Oct 09 05:46:14 AM UTC 24 |
| Peak memory | 203336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27376196 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.27376196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_fifo_full.3270514963 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 46213160455 ps |
| CPU time | 32.99 seconds |
| Started | Oct 09 05:45:37 AM UTC 24 |
| Finished | Oct 09 05:46:11 AM UTC 24 |
| Peak memory | 209392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270514963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3270514963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.1089723212 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 10671320672 ps |
| CPU time | 35.74 seconds |
| Started | Oct 09 05:45:37 AM UTC 24 |
| Finished | Oct 09 05:46:14 AM UTC 24 |
| Peak memory | 209420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089723212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1089723212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_fifo_reset.3984790651 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 15099652508 ps |
| CPU time | 49.43 seconds |
| Started | Oct 09 05:45:38 AM UTC 24 |
| Finished | Oct 09 05:46:29 AM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984790651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3984790651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_intr.1753549226 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 54255213001 ps |
| CPU time | 86.12 seconds |
| Started | Oct 09 05:45:44 AM UTC 24 |
| Finished | Oct 09 05:47:12 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753549226 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1753549226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.2406973337 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 43832714770 ps |
| CPU time | 298.82 seconds |
| Started | Oct 09 05:46:04 AM UTC 24 |
| Finished | Oct 09 05:51:07 AM UTC 24 |
| Peak memory | 203996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406973337 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2406973337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_loopback.720326592 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 6909352055 ps |
| CPU time | 8.17 seconds |
| Started | Oct 09 05:46:02 AM UTC 24 |
| Finished | Oct 09 05:46:11 AM UTC 24 |
| Peak memory | 204192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720326592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 38.uart_loopback.720326592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_noise_filter.1856568896 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 185699800031 ps |
| CPU time | 198.8 seconds |
| Started | Oct 09 05:45:46 AM UTC 24 |
| Finished | Oct 09 05:49:08 AM UTC 24 |
| Peak memory | 209760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856568896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1856568896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_perf.911975980 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 11540848858 ps |
| CPU time | 179.87 seconds |
| Started | Oct 09 05:46:03 AM UTC 24 |
| Finished | Oct 09 05:49:06 AM UTC 24 |
| Peak memory | 203992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911975980 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.911975980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_rx_oversample.1563461329 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 2906359268 ps |
| CPU time | 4.53 seconds |
| Started | Oct 09 05:45:38 AM UTC 24 |
| Finished | Oct 09 05:45:43 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563461329 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1563461329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.2349812598 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 21915289674 ps |
| CPU time | 74.03 seconds |
| Started | Oct 09 05:45:52 AM UTC 24 |
| Finished | Oct 09 05:47:08 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349812598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2349812598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.1466084971 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 51623740171 ps |
| CPU time | 132.52 seconds |
| Started | Oct 09 05:45:47 AM UTC 24 |
| Finished | Oct 09 05:48:02 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466084971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1466084971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_smoke.4241504262 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 692308606 ps |
| CPU time | 2.07 seconds |
| Started | Oct 09 05:45:34 AM UTC 24 |
| Finished | Oct 09 05:45:37 AM UTC 24 |
| Peak memory | 204200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241504262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4241504262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_stress_all.2184966206 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 173915202848 ps |
| CPU time | 306.43 seconds |
| Started | Oct 09 05:46:12 AM UTC 24 |
| Finished | Oct 09 05:51:23 AM UTC 24 |
| Peak memory | 208024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184966206 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2184966206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.2260433780 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 15934275683 ps |
| CPU time | 46.2 seconds |
| Started | Oct 09 05:46:12 AM UTC 24 |
| Finished | Oct 09 05:47:00 AM UTC 24 |
| Peak memory | 225404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2260433780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all _with_rand_reset.2260433780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.3258541700 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 582309791 ps |
| CPU time | 2.14 seconds |
| Started | Oct 09 05:45:59 AM UTC 24 |
| Finished | Oct 09 05:46:03 AM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258541700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3258541700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_tx_rx.1870469467 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 120799702086 ps |
| CPU time | 56.9 seconds |
| Started | Oct 09 05:45:36 AM UTC 24 |
| Finished | Oct 09 05:46:35 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870469467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1870469467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/38.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_alert_test.4209971670 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 99965803 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 05:46:42 AM UTC 24 |
| Finished | Oct 09 05:46:44 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209971670 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.4209971670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_fifo_full.3279319486 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 123918396013 ps |
| CPU time | 50.67 seconds |
| Started | Oct 09 05:46:15 AM UTC 24 |
| Finished | Oct 09 05:47:07 AM UTC 24 |
| Peak memory | 203996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279319486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3279319486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.683285687 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 80183381570 ps |
| CPU time | 25.44 seconds |
| Started | Oct 09 05:46:15 AM UTC 24 |
| Finished | Oct 09 05:46:42 AM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683285687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.683285687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_fifo_reset.3098430494 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 153169693059 ps |
| CPU time | 72.57 seconds |
| Started | Oct 09 05:46:16 AM UTC 24 |
| Finished | Oct 09 05:47:31 AM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098430494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3098430494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_intr.2977637517 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 209481140706 ps |
| CPU time | 438.96 seconds |
| Started | Oct 09 05:46:21 AM UTC 24 |
| Finished | Oct 09 05:53:45 AM UTC 24 |
| Peak memory | 208416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977637517 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2977637517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.158477455 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 90099326818 ps |
| CPU time | 606.72 seconds |
| Started | Oct 09 05:46:36 AM UTC 24 |
| Finished | Oct 09 05:56:50 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158477455 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.158477455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_loopback.1870441767 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 5137263935 ps |
| CPU time | 15.99 seconds |
| Started | Oct 09 05:46:33 AM UTC 24 |
| Finished | Oct 09 05:46:50 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870441767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1870441767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_noise_filter.3086882751 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 24263430832 ps |
| CPU time | 47.28 seconds |
| Started | Oct 09 05:46:21 AM UTC 24 |
| Finished | Oct 09 05:47:10 AM UTC 24 |
| Peak memory | 209956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086882751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3086882751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_perf.990175808 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 7175722469 ps |
| CPU time | 214.62 seconds |
| Started | Oct 09 05:46:35 AM UTC 24 |
| Finished | Oct 09 05:50:13 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990175808 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.990175808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_rx_oversample.1084138854 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 5903282731 ps |
| CPU time | 60.84 seconds |
| Started | Oct 09 05:46:19 AM UTC 24 |
| Finished | Oct 09 05:47:22 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084138854 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1084138854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.2219053688 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 186396592056 ps |
| CPU time | 128.97 seconds |
| Started | Oct 09 05:46:30 AM UTC 24 |
| Finished | Oct 09 05:48:41 AM UTC 24 |
| Peak memory | 209336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219053688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2219053688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.3321242870 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1554687581 ps |
| CPU time | 5.63 seconds |
| Started | Oct 09 05:46:26 AM UTC 24 |
| Finished | Oct 09 05:46:33 AM UTC 24 |
| Peak memory | 203732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321242870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3321242870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_smoke.1530546272 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 945572710 ps |
| CPU time | 4.21 seconds |
| Started | Oct 09 05:46:13 AM UTC 24 |
| Finished | Oct 09 05:46:18 AM UTC 24 |
| Peak memory | 204016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530546272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1530546272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_stress_all.568151099 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 416727066474 ps |
| CPU time | 218.52 seconds |
| Started | Oct 09 05:46:40 AM UTC 24 |
| Finished | Oct 09 05:50:22 AM UTC 24 |
| Peak memory | 218844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568151099 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.568151099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.3968575876 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 10626286266 ps |
| CPU time | 83.18 seconds |
| Started | Oct 09 05:46:38 AM UTC 24 |
| Finished | Oct 09 05:48:03 AM UTC 24 |
| Peak memory | 222544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3968575876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all _with_rand_reset.3968575876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1353924179 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 1449309935 ps |
| CPU time | 8.18 seconds |
| Started | Oct 09 05:46:32 AM UTC 24 |
| Finished | Oct 09 05:46:41 AM UTC 24 |
| Peak memory | 204268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353924179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1353924179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_tx_rx.3117797841 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 36156892811 ps |
| CPU time | 65 seconds |
| Started | Oct 09 05:46:14 AM UTC 24 |
| Finished | Oct 09 05:47:21 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117797841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3117797841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/39.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_alert_test.2921384352 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 13753348 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 05:27:41 AM UTC 24 |
| Finished | Oct 09 05:27:43 AM UTC 24 |
| Peak memory | 203408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921384352 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2921384352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.2753193753 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 84057745174 ps |
| CPU time | 141.42 seconds |
| Started | Oct 09 05:27:24 AM UTC 24 |
| Finished | Oct 09 05:29:47 AM UTC 24 |
| Peak memory | 209384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753193753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2753193753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_fifo_reset.2109138859 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 46254798319 ps |
| CPU time | 81.47 seconds |
| Started | Oct 09 05:27:24 AM UTC 24 |
| Finished | Oct 09 05:28:47 AM UTC 24 |
| Peak memory | 209660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109138859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2109138859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_intr.1507461075 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 79415565318 ps |
| CPU time | 35.5 seconds |
| Started | Oct 09 05:27:26 AM UTC 24 |
| Finished | Oct 09 05:28:03 AM UTC 24 |
| Peak memory | 203920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507461075 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1507461075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.2057893623 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 208797987667 ps |
| CPU time | 1177.83 seconds |
| Started | Oct 09 05:27:37 AM UTC 24 |
| Finished | Oct 09 05:47:28 AM UTC 24 |
| Peak memory | 209756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057893623 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2057893623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_loopback.3209130201 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 4850624957 ps |
| CPU time | 9.48 seconds |
| Started | Oct 09 05:27:34 AM UTC 24 |
| Finished | Oct 09 05:27:45 AM UTC 24 |
| Peak memory | 204260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209130201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3209130201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_noise_filter.3065107837 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 49278862427 ps |
| CPU time | 116.82 seconds |
| Started | Oct 09 05:27:26 AM UTC 24 |
| Finished | Oct 09 05:29:25 AM UTC 24 |
| Peak memory | 209620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065107837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3065107837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_rx_oversample.2087738391 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 4953294562 ps |
| CPU time | 26.91 seconds |
| Started | Oct 09 05:27:26 AM UTC 24 |
| Finished | Oct 09 05:27:54 AM UTC 24 |
| Peak memory | 204268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087738391 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2087738391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.294018896 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 91402419586 ps |
| CPU time | 42.95 seconds |
| Started | Oct 09 05:27:32 AM UTC 24 |
| Finished | Oct 09 05:28:17 AM UTC 24 |
| Peak memory | 209136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294018896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.294018896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.3884608421 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 2318788282 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 05:27:30 AM UTC 24 |
| Finished | Oct 09 05:27:34 AM UTC 24 |
| Peak memory | 203928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884608421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3884608421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_sec_cm.3414711660 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 40283938 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 05:27:39 AM UTC 24 |
| Finished | Oct 09 05:27:42 AM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414711660 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3414711660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_smoke.1914128998 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 531366279 ps |
| CPU time | 2.39 seconds |
| Started | Oct 09 05:27:19 AM UTC 24 |
| Finished | Oct 09 05:27:23 AM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914128998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1914128998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.3088960618 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 553805638 ps |
| CPU time | 4.12 seconds |
| Started | Oct 09 05:27:34 AM UTC 24 |
| Finished | Oct 09 05:27:40 AM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088960618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3088960618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_tx_rx.3994854170 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 36548114739 ps |
| CPU time | 16.34 seconds |
| Started | Oct 09 05:27:21 AM UTC 24 |
| Finished | Oct 09 05:27:39 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994854170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3994854170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/4.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_alert_test.428901656 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 37194717 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:47:21 AM UTC 24 |
| Finished | Oct 09 05:47:23 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428901656 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.428901656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_fifo_full.1017851625 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 67220954540 ps |
| CPU time | 63.06 seconds |
| Started | Oct 09 05:46:46 AM UTC 24 |
| Finished | Oct 09 05:47:51 AM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017851625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1017851625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.4152269439 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 81767603915 ps |
| CPU time | 172.51 seconds |
| Started | Oct 09 05:46:51 AM UTC 24 |
| Finished | Oct 09 05:49:46 AM UTC 24 |
| Peak memory | 209836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152269439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.4152269439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_fifo_reset.1928623255 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 5523980879 ps |
| CPU time | 24.17 seconds |
| Started | Oct 09 05:46:55 AM UTC 24 |
| Finished | Oct 09 05:47:21 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928623255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1928623255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_intr.2771205648 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 7062730061 ps |
| CPU time | 24.5 seconds |
| Started | Oct 09 05:47:08 AM UTC 24 |
| Finished | Oct 09 05:47:34 AM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771205648 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2771205648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.3569466663 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 96015278111 ps |
| CPU time | 822.22 seconds |
| Started | Oct 09 05:47:19 AM UTC 24 |
| Finished | Oct 09 06:01:11 AM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569466663 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3569466663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_loopback.2863952955 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 2667641544 ps |
| CPU time | 3.74 seconds |
| Started | Oct 09 05:47:14 AM UTC 24 |
| Finished | Oct 09 05:47:18 AM UTC 24 |
| Peak memory | 203728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863952955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2863952955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_noise_filter.4077815719 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 46177986839 ps |
| CPU time | 55.18 seconds |
| Started | Oct 09 05:47:09 AM UTC 24 |
| Finished | Oct 09 05:48:06 AM UTC 24 |
| Peak memory | 209764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077815719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.4077815719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_perf.4217252740 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 16236181451 ps |
| CPU time | 814.32 seconds |
| Started | Oct 09 05:47:16 AM UTC 24 |
| Finished | Oct 09 06:01:01 AM UTC 24 |
| Peak memory | 212876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217252740 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.4217252740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_rx_oversample.808618005 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5150340738 ps |
| CPU time | 28.76 seconds |
| Started | Oct 09 05:47:00 AM UTC 24 |
| Finished | Oct 09 05:47:30 AM UTC 24 |
| Peak memory | 204140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808618005 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.808618005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.824693936 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 63764418589 ps |
| CPU time | 105.54 seconds |
| Started | Oct 09 05:47:10 AM UTC 24 |
| Finished | Oct 09 05:48:58 AM UTC 24 |
| Peak memory | 209488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824693936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.824693936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.2745758926 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 90330099291 ps |
| CPU time | 12.09 seconds |
| Started | Oct 09 05:47:10 AM UTC 24 |
| Finished | Oct 09 05:47:24 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745758926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2745758926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_smoke.405903485 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 124547127 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 05:46:43 AM UTC 24 |
| Finished | Oct 09 05:46:45 AM UTC 24 |
| Peak memory | 203348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405903485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 40.uart_smoke.405903485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_stress_all.1116311134 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 152188768463 ps |
| CPU time | 339.52 seconds |
| Started | Oct 09 05:47:21 AM UTC 24 |
| Finished | Oct 09 05:53:05 AM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116311134 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1116311134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.587770487 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 7857473801 ps |
| CPU time | 70.78 seconds |
| Started | Oct 09 05:47:20 AM UTC 24 |
| Finished | Oct 09 05:48:32 AM UTC 24 |
| Peak memory | 218648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=587770487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all_ with_rand_reset.587770487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.3588513264 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 7891282569 ps |
| CPU time | 11.88 seconds |
| Started | Oct 09 05:47:14 AM UTC 24 |
| Finished | Oct 09 05:47:27 AM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588513264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3588513264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_tx_rx.3045272737 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 22196136854 ps |
| CPU time | 23.91 seconds |
| Started | Oct 09 05:46:45 AM UTC 24 |
| Finished | Oct 09 05:47:10 AM UTC 24 |
| Peak memory | 204200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045272737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3045272737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/40.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_alert_test.946020654 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 42058251 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 05:47:44 AM UTC 24 |
| Finished | Oct 09 05:47:45 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946020654 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.946020654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_fifo_full.1609695135 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 35509642708 ps |
| CPU time | 60.64 seconds |
| Started | Oct 09 05:47:23 AM UTC 24 |
| Finished | Oct 09 05:48:26 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609695135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1609695135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.1540738375 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 114573547554 ps |
| CPU time | 125.12 seconds |
| Started | Oct 09 05:47:24 AM UTC 24 |
| Finished | Oct 09 05:49:32 AM UTC 24 |
| Peak memory | 209516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540738375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1540738375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_fifo_reset.26301410 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 45720875202 ps |
| CPU time | 38.67 seconds |
| Started | Oct 09 05:47:26 AM UTC 24 |
| Finished | Oct 09 05:48:07 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26301410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.26301410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_intr.4173968644 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 29490612871 ps |
| CPU time | 50.68 seconds |
| Started | Oct 09 05:47:29 AM UTC 24 |
| Finished | Oct 09 05:48:21 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173968644 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.4173968644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.4165255001 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 63793469470 ps |
| CPU time | 251.5 seconds |
| Started | Oct 09 05:47:38 AM UTC 24 |
| Finished | Oct 09 05:51:53 AM UTC 24 |
| Peak memory | 204060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165255001 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4165255001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_loopback.1094826316 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 2447282959 ps |
| CPU time | 3.57 seconds |
| Started | Oct 09 05:47:38 AM UTC 24 |
| Finished | Oct 09 05:47:43 AM UTC 24 |
| Peak memory | 203936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094826316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1094826316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_noise_filter.4022411325 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 41175815760 ps |
| CPU time | 49.01 seconds |
| Started | Oct 09 05:47:31 AM UTC 24 |
| Finished | Oct 09 05:48:21 AM UTC 24 |
| Peak memory | 209688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022411325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.4022411325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_perf.540381505 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 15574147353 ps |
| CPU time | 198.67 seconds |
| Started | Oct 09 05:47:38 AM UTC 24 |
| Finished | Oct 09 05:51:00 AM UTC 24 |
| Peak memory | 209352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540381505 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.540381505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_rx_oversample.308338756 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1617013921 ps |
| CPU time | 3.21 seconds |
| Started | Oct 09 05:47:28 AM UTC 24 |
| Finished | Oct 09 05:47:32 AM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308338756 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.308338756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.2360287893 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 109421994273 ps |
| CPU time | 78.16 seconds |
| Started | Oct 09 05:47:33 AM UTC 24 |
| Finished | Oct 09 05:48:53 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360287893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2360287893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.1785958163 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3754654720 ps |
| CPU time | 4.27 seconds |
| Started | Oct 09 05:47:32 AM UTC 24 |
| Finished | Oct 09 05:47:37 AM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785958163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1785958163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_smoke.1921928327 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 948462667 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 05:47:22 AM UTC 24 |
| Finished | Oct 09 05:47:25 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921928327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1921928327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_stress_all.566876141 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 416503780623 ps |
| CPU time | 431.72 seconds |
| Started | Oct 09 05:47:40 AM UTC 24 |
| Finished | Oct 09 05:54:58 AM UTC 24 |
| Peak memory | 226060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566876141 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.566876141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.424307071 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 940794141 ps |
| CPU time | 10.78 seconds |
| Started | Oct 09 05:47:39 AM UTC 24 |
| Finished | Oct 09 05:47:51 AM UTC 24 |
| Peak memory | 224804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=424307071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all_ with_rand_reset.424307071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.2522633853 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 2150600072 ps |
| CPU time | 2.73 seconds |
| Started | Oct 09 05:47:35 AM UTC 24 |
| Finished | Oct 09 05:47:39 AM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522633853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2522633853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_tx_rx.3706084562 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 20019980159 ps |
| CPU time | 12.81 seconds |
| Started | Oct 09 05:47:23 AM UTC 24 |
| Finished | Oct 09 05:47:37 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706084562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3706084562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/41.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_alert_test.691261257 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 14796409 ps |
| CPU time | 0.86 seconds |
| Started | Oct 09 05:48:11 AM UTC 24 |
| Finished | Oct 09 05:48:13 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691261257 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.691261257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_fifo_full.1360831380 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 95960984074 ps |
| CPU time | 104.72 seconds |
| Started | Oct 09 05:47:46 AM UTC 24 |
| Finished | Oct 09 05:49:33 AM UTC 24 |
| Peak memory | 204084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360831380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1360831380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.2938254906 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 46691626554 ps |
| CPU time | 26.02 seconds |
| Started | Oct 09 05:47:52 AM UTC 24 |
| Finished | Oct 09 05:48:19 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938254906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2938254906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_intr.2397550656 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 99449455197 ps |
| CPU time | 13.3 seconds |
| Started | Oct 09 05:47:56 AM UTC 24 |
| Finished | Oct 09 05:48:11 AM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397550656 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2397550656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.385227929 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 132281920992 ps |
| CPU time | 704.98 seconds |
| Started | Oct 09 05:48:08 AM UTC 24 |
| Finished | Oct 09 06:00:01 AM UTC 24 |
| Peak memory | 207448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385227929 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.385227929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_loopback.430172947 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 2197735047 ps |
| CPU time | 8.15 seconds |
| Started | Oct 09 05:48:07 AM UTC 24 |
| Finished | Oct 09 05:48:16 AM UTC 24 |
| Peak memory | 204336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430172947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.uart_loopback.430172947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_noise_filter.3746691336 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 62567311463 ps |
| CPU time | 152.87 seconds |
| Started | Oct 09 05:47:58 AM UTC 24 |
| Finished | Oct 09 05:50:34 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746691336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3746691336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_perf.2099017949 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 10918438979 ps |
| CPU time | 138.69 seconds |
| Started | Oct 09 05:48:08 AM UTC 24 |
| Finished | Oct 09 05:50:29 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099017949 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2099017949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_rx_oversample.3832873555 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 5264236554 ps |
| CPU time | 11.96 seconds |
| Started | Oct 09 05:47:54 AM UTC 24 |
| Finished | Oct 09 05:48:07 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832873555 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3832873555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.2320417514 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 82281460278 ps |
| CPU time | 91.78 seconds |
| Started | Oct 09 05:48:04 AM UTC 24 |
| Finished | Oct 09 05:49:38 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320417514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2320417514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.2267529749 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 3045021544 ps |
| CPU time | 3.51 seconds |
| Started | Oct 09 05:48:03 AM UTC 24 |
| Finished | Oct 09 05:48:08 AM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267529749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2267529749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_smoke.28743090 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 11071771756 ps |
| CPU time | 44.33 seconds |
| Started | Oct 09 05:47:44 AM UTC 24 |
| Finished | Oct 09 05:48:29 AM UTC 24 |
| Peak memory | 204076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28743090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_smoke.28743090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_stress_all.991009740 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 95929689544 ps |
| CPU time | 516.38 seconds |
| Started | Oct 09 05:48:10 AM UTC 24 |
| Finished | Oct 09 05:56:53 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991009740 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.991009740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.1887527980 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 13303776137 ps |
| CPU time | 88.38 seconds |
| Started | Oct 09 05:48:09 AM UTC 24 |
| Finished | Oct 09 05:49:39 AM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1887527980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all _with_rand_reset.1887527980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.4056278642 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1250615192 ps |
| CPU time | 3.28 seconds |
| Started | Oct 09 05:48:04 AM UTC 24 |
| Finished | Oct 09 05:48:09 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056278642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.4056278642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_tx_rx.4052614758 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 22172235359 ps |
| CPU time | 17.51 seconds |
| Started | Oct 09 05:47:45 AM UTC 24 |
| Finished | Oct 09 05:48:03 AM UTC 24 |
| Peak memory | 204312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052614758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4052614758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/42.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_alert_test.2164326808 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 11714778 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 05:48:50 AM UTC 24 |
| Finished | Oct 09 05:48:52 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164326808 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2164326808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_fifo_full.3572107364 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 71442091320 ps |
| CPU time | 108.89 seconds |
| Started | Oct 09 05:48:16 AM UTC 24 |
| Finished | Oct 09 05:50:07 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572107364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3572107364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.3995272155 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 128618093624 ps |
| CPU time | 171.15 seconds |
| Started | Oct 09 05:48:18 AM UTC 24 |
| Finished | Oct 09 05:51:12 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995272155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3995272155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_fifo_reset.2408525287 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 41632548366 ps |
| CPU time | 25.42 seconds |
| Started | Oct 09 05:48:20 AM UTC 24 |
| Finished | Oct 09 05:48:47 AM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408525287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2408525287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_intr.1776815480 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 27886251249 ps |
| CPU time | 55.58 seconds |
| Started | Oct 09 05:48:23 AM UTC 24 |
| Finished | Oct 09 05:49:20 AM UTC 24 |
| Peak memory | 204132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776815480 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1776815480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.3510887964 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 192131767306 ps |
| CPU time | 120.78 seconds |
| Started | Oct 09 05:48:44 AM UTC 24 |
| Finished | Oct 09 05:50:47 AM UTC 24 |
| Peak memory | 206304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510887964 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3510887964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_loopback.161152127 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 5645578492 ps |
| CPU time | 20.45 seconds |
| Started | Oct 09 05:48:40 AM UTC 24 |
| Finished | Oct 09 05:49:02 AM UTC 24 |
| Peak memory | 204336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161152127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 43.uart_loopback.161152127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_noise_filter.362885389 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 46867328725 ps |
| CPU time | 115.03 seconds |
| Started | Oct 09 05:48:27 AM UTC 24 |
| Finished | Oct 09 05:50:24 AM UTC 24 |
| Peak memory | 209700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362885389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.362885389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_perf.1232248880 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 3357586073 ps |
| CPU time | 111.89 seconds |
| Started | Oct 09 05:48:42 AM UTC 24 |
| Finished | Oct 09 05:50:36 AM UTC 24 |
| Peak memory | 209408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232248880 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1232248880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_rx_oversample.1099071593 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 4398416080 ps |
| CPU time | 45.69 seconds |
| Started | Oct 09 05:48:22 AM UTC 24 |
| Finished | Oct 09 05:49:09 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099071593 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1099071593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.58545624 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 19630245498 ps |
| CPU time | 61.48 seconds |
| Started | Oct 09 05:48:30 AM UTC 24 |
| Finished | Oct 09 05:49:33 AM UTC 24 |
| Peak memory | 209576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58545624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.58545624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.1802098196 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 33486472014 ps |
| CPU time | 17.26 seconds |
| Started | Oct 09 05:48:29 AM UTC 24 |
| Finished | Oct 09 05:48:47 AM UTC 24 |
| Peak memory | 204116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802098196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1802098196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_smoke.2179162640 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 829377541 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 05:48:14 AM UTC 24 |
| Finished | Oct 09 05:48:18 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179162640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2179162640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_stress_all.1438988756 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 234550331384 ps |
| CPU time | 915.9 seconds |
| Started | Oct 09 05:48:49 AM UTC 24 |
| Finished | Oct 09 06:04:15 AM UTC 24 |
| Peak memory | 225416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438988756 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1438988756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.2508333682 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 8239815757 ps |
| CPU time | 68.67 seconds |
| Started | Oct 09 05:48:48 AM UTC 24 |
| Finished | Oct 09 05:49:59 AM UTC 24 |
| Peak memory | 226032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2508333682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all _with_rand_reset.2508333682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.1978719847 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 1065564783 ps |
| CPU time | 5.54 seconds |
| Started | Oct 09 05:48:33 AM UTC 24 |
| Finished | Oct 09 05:48:40 AM UTC 24 |
| Peak memory | 204020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978719847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1978719847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_tx_rx.502075450 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 26290927284 ps |
| CPU time | 49.97 seconds |
| Started | Oct 09 05:48:14 AM UTC 24 |
| Finished | Oct 09 05:49:06 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502075450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.502075450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/43.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_alert_test.3552180126 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 14204858 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 05:49:19 AM UTC 24 |
| Finished | Oct 09 05:49:21 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552180126 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3552180126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_fifo_full.3629186850 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 61955481503 ps |
| CPU time | 18.8 seconds |
| Started | Oct 09 05:48:57 AM UTC 24 |
| Finished | Oct 09 05:49:17 AM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629186850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3629186850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.1248277255 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 30713394121 ps |
| CPU time | 82.96 seconds |
| Started | Oct 09 05:48:58 AM UTC 24 |
| Finished | Oct 09 05:50:23 AM UTC 24 |
| Peak memory | 209360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248277255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1248277255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_fifo_reset.671115578 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 26111018330 ps |
| CPU time | 21.08 seconds |
| Started | Oct 09 05:48:59 AM UTC 24 |
| Finished | Oct 09 05:49:22 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671115578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.671115578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_intr.1944333043 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 20157225208 ps |
| CPU time | 13.15 seconds |
| Started | Oct 09 05:49:03 AM UTC 24 |
| Finished | Oct 09 05:49:18 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944333043 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1944333043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.2836350074 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 58920308518 ps |
| CPU time | 500.42 seconds |
| Started | Oct 09 05:49:12 AM UTC 24 |
| Finished | Oct 09 05:57:39 AM UTC 24 |
| Peak memory | 204060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836350074 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2836350074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_loopback.2567682433 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 9079146237 ps |
| CPU time | 9.48 seconds |
| Started | Oct 09 05:49:10 AM UTC 24 |
| Finished | Oct 09 05:49:20 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567682433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2567682433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_noise_filter.2845087064 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 59582957113 ps |
| CPU time | 106.58 seconds |
| Started | Oct 09 05:49:06 AM UTC 24 |
| Finished | Oct 09 05:50:55 AM UTC 24 |
| Peak memory | 209776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845087064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2845087064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_perf.613274906 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 15341886387 ps |
| CPU time | 991.62 seconds |
| Started | Oct 09 05:49:11 AM UTC 24 |
| Finished | Oct 09 06:05:55 AM UTC 24 |
| Peak memory | 212948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613274906 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.613274906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_rx_oversample.1885511428 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 2994716208 ps |
| CPU time | 7.67 seconds |
| Started | Oct 09 05:49:00 AM UTC 24 |
| Finished | Oct 09 05:49:09 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885511428 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1885511428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.3322651316 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 10671080591 ps |
| CPU time | 22.13 seconds |
| Started | Oct 09 05:49:09 AM UTC 24 |
| Finished | Oct 09 05:49:32 AM UTC 24 |
| Peak memory | 209272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322651316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3322651316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.2328808008 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 490109280 ps |
| CPU time | 1.69 seconds |
| Started | Oct 09 05:49:06 AM UTC 24 |
| Finished | Oct 09 05:49:09 AM UTC 24 |
| Peak memory | 203340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328808008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2328808008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_smoke.397187567 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 267859496 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 05:48:53 AM UTC 24 |
| Finished | Oct 09 05:48:56 AM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397187567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 44.uart_smoke.397187567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_stress_all.3103424745 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 38691262029 ps |
| CPU time | 251.27 seconds |
| Started | Oct 09 05:49:18 AM UTC 24 |
| Finished | Oct 09 05:53:33 AM UTC 24 |
| Peak memory | 206052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103424745 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3103424745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.1012377131 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 7732640497 ps |
| CPU time | 17.06 seconds |
| Started | Oct 09 05:49:10 AM UTC 24 |
| Finished | Oct 09 05:49:28 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012377131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1012377131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_tx_rx.3291502397 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 50148069773 ps |
| CPU time | 80.21 seconds |
| Started | Oct 09 05:48:54 AM UTC 24 |
| Finished | Oct 09 05:50:16 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291502397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3291502397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_alert_test.2180638071 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 52506985 ps |
| CPU time | 0.85 seconds |
| Started | Oct 09 05:49:57 AM UTC 24 |
| Finished | Oct 09 05:49:59 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180638071 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2180638071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_fifo_full.3577665833 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 76583529138 ps |
| CPU time | 66.19 seconds |
| Started | Oct 09 05:49:22 AM UTC 24 |
| Finished | Oct 09 05:50:31 AM UTC 24 |
| Peak memory | 209164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577665833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3577665833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.892404871 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 65738183255 ps |
| CPU time | 67.4 seconds |
| Started | Oct 09 05:49:23 AM UTC 24 |
| Finished | Oct 09 05:50:32 AM UTC 24 |
| Peak memory | 203924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892404871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.892404871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_fifo_reset.731239258 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 44274276380 ps |
| CPU time | 97.53 seconds |
| Started | Oct 09 05:49:29 AM UTC 24 |
| Finished | Oct 09 05:51:08 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731239258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.731239258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_intr.3160408043 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 46468280792 ps |
| CPU time | 53.39 seconds |
| Started | Oct 09 05:49:33 AM UTC 24 |
| Finished | Oct 09 05:50:28 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160408043 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3160408043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.4291618146 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 101376674152 ps |
| CPU time | 321.07 seconds |
| Started | Oct 09 05:49:47 AM UTC 24 |
| Finished | Oct 09 05:55:13 AM UTC 24 |
| Peak memory | 206108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291618146 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.4291618146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_loopback.4004637942 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 8053226478 ps |
| CPU time | 14.14 seconds |
| Started | Oct 09 05:49:40 AM UTC 24 |
| Finished | Oct 09 05:49:55 AM UTC 24 |
| Peak memory | 203928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004637942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.4004637942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_noise_filter.2744994599 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 6963970219 ps |
| CPU time | 18.16 seconds |
| Started | Oct 09 05:49:34 AM UTC 24 |
| Finished | Oct 09 05:49:53 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744994599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2744994599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_perf.311371955 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 11868481198 ps |
| CPU time | 149.96 seconds |
| Started | Oct 09 05:49:47 AM UTC 24 |
| Finished | Oct 09 05:52:20 AM UTC 24 |
| Peak memory | 204316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311371955 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.311371955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_rx_oversample.1644519455 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 6233599442 ps |
| CPU time | 74.83 seconds |
| Started | Oct 09 05:49:33 AM UTC 24 |
| Finished | Oct 09 05:50:49 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644519455 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1644519455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.652380679 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 34131188900 ps |
| CPU time | 115.44 seconds |
| Started | Oct 09 05:49:39 AM UTC 24 |
| Finished | Oct 09 05:51:37 AM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652380679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.652380679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.662457878 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 3410578814 ps |
| CPU time | 4.65 seconds |
| Started | Oct 09 05:49:34 AM UTC 24 |
| Finished | Oct 09 05:49:40 AM UTC 24 |
| Peak memory | 204124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662457878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.662457878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_smoke.3752059099 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 5996449088 ps |
| CPU time | 31.75 seconds |
| Started | Oct 09 05:49:20 AM UTC 24 |
| Finished | Oct 09 05:49:54 AM UTC 24 |
| Peak memory | 203944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752059099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3752059099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_stress_all.135707957 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 178240720173 ps |
| CPU time | 186.16 seconds |
| Started | Oct 09 05:49:55 AM UTC 24 |
| Finished | Oct 09 05:53:04 AM UTC 24 |
| Peak memory | 209688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135707957 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.135707957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.2294631237 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 7106208586 ps |
| CPU time | 32.25 seconds |
| Started | Oct 09 05:49:55 AM UTC 24 |
| Finished | Oct 09 05:50:28 AM UTC 24 |
| Peak memory | 220484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2294631237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all _with_rand_reset.2294631237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.2361193999 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 922942196 ps |
| CPU time | 5.45 seconds |
| Started | Oct 09 05:49:40 AM UTC 24 |
| Finished | Oct 09 05:49:47 AM UTC 24 |
| Peak memory | 203676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361193999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2361193999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_tx_rx.739320484 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 25800690187 ps |
| CPU time | 60.24 seconds |
| Started | Oct 09 05:49:21 AM UTC 24 |
| Finished | Oct 09 05:50:23 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739320484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.739320484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/45.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_alert_test.802368288 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 36868482 ps |
| CPU time | 0.82 seconds |
| Started | Oct 09 05:50:31 AM UTC 24 |
| Finished | Oct 09 05:50:33 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802368288 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.802368288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_fifo_full.4138574630 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 177215331970 ps |
| CPU time | 130.84 seconds |
| Started | Oct 09 05:50:03 AM UTC 24 |
| Finished | Oct 09 05:52:16 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138574630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.4138574630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.2784263432 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 202863321747 ps |
| CPU time | 24.99 seconds |
| Started | Oct 09 05:50:04 AM UTC 24 |
| Finished | Oct 09 05:50:30 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784263432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2784263432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_fifo_reset.3742333256 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 106212078653 ps |
| CPU time | 55.5 seconds |
| Started | Oct 09 05:50:08 AM UTC 24 |
| Finished | Oct 09 05:51:05 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742333256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3742333256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_intr.2471405566 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 123216102892 ps |
| CPU time | 161.99 seconds |
| Started | Oct 09 05:50:16 AM UTC 24 |
| Finished | Oct 09 05:53:01 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471405566 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2471405566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.1952539951 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 108353120530 ps |
| CPU time | 163.67 seconds |
| Started | Oct 09 05:50:30 AM UTC 24 |
| Finished | Oct 09 05:53:17 AM UTC 24 |
| Peak memory | 204060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952539951 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1952539951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_loopback.3621028525 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 9613847329 ps |
| CPU time | 11.87 seconds |
| Started | Oct 09 05:50:29 AM UTC 24 |
| Finished | Oct 09 05:50:42 AM UTC 24 |
| Peak memory | 203924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621028525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3621028525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_noise_filter.3336938900 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 50513358995 ps |
| CPU time | 35.11 seconds |
| Started | Oct 09 05:50:22 AM UTC 24 |
| Finished | Oct 09 05:50:59 AM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336938900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3336938900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_perf.3634672942 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 8557501943 ps |
| CPU time | 457.35 seconds |
| Started | Oct 09 05:50:29 AM UTC 24 |
| Finished | Oct 09 05:58:12 AM UTC 24 |
| Peak memory | 209408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634672942 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3634672942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_rx_oversample.1584932527 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 4420702429 ps |
| CPU time | 25.19 seconds |
| Started | Oct 09 05:50:14 AM UTC 24 |
| Finished | Oct 09 05:50:41 AM UTC 24 |
| Peak memory | 204392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584932527 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1584932527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.4259037462 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 50214658254 ps |
| CPU time | 25.37 seconds |
| Started | Oct 09 05:50:25 AM UTC 24 |
| Finished | Oct 09 05:50:52 AM UTC 24 |
| Peak memory | 204400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259037462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4259037462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.3199229514 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 783479575 ps |
| CPU time | 4.05 seconds |
| Started | Oct 09 05:50:25 AM UTC 24 |
| Finished | Oct 09 05:50:30 AM UTC 24 |
| Peak memory | 203860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199229514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3199229514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_smoke.3593696840 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 679310140 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 05:50:00 AM UTC 24 |
| Finished | Oct 09 05:50:03 AM UTC 24 |
| Peak memory | 204200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593696840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3593696840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_stress_all.3840623716 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 135137921859 ps |
| CPU time | 512.69 seconds |
| Started | Oct 09 05:50:31 AM UTC 24 |
| Finished | Oct 09 05:59:10 AM UTC 24 |
| Peak memory | 208296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840623716 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3840623716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.2393704013 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2968694565 ps |
| CPU time | 25.27 seconds |
| Started | Oct 09 05:50:31 AM UTC 24 |
| Finished | Oct 09 05:50:58 AM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2393704013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all _with_rand_reset.2393704013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.2219224911 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 6947259577 ps |
| CPU time | 18.17 seconds |
| Started | Oct 09 05:50:25 AM UTC 24 |
| Finished | Oct 09 05:50:44 AM UTC 24 |
| Peak memory | 204328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219224911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2219224911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_tx_rx.1092295567 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 8076380554 ps |
| CPU time | 31.68 seconds |
| Started | Oct 09 05:50:00 AM UTC 24 |
| Finished | Oct 09 05:50:33 AM UTC 24 |
| Peak memory | 209432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092295567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1092295567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/46.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_alert_test.2782836708 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 23024648 ps |
| CPU time | 0.83 seconds |
| Started | Oct 09 05:50:59 AM UTC 24 |
| Finished | Oct 09 05:51:01 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782836708 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2782836708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_fifo_full.768432478 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 78511219600 ps |
| CPU time | 119.84 seconds |
| Started | Oct 09 05:50:33 AM UTC 24 |
| Finished | Oct 09 05:52:36 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768432478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.768432478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.92057270 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 174608795933 ps |
| CPU time | 80.15 seconds |
| Started | Oct 09 05:50:35 AM UTC 24 |
| Finished | Oct 09 05:51:56 AM UTC 24 |
| Peak memory | 209564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92057270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.92057270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_fifo_reset.747712284 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 16499821391 ps |
| CPU time | 30.01 seconds |
| Started | Oct 09 05:50:38 AM UTC 24 |
| Finished | Oct 09 05:51:09 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747712284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.747712284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_intr.3851529647 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 36260268657 ps |
| CPU time | 19.91 seconds |
| Started | Oct 09 05:50:42 AM UTC 24 |
| Finished | Oct 09 05:51:03 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851529647 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3851529647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.3458188272 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 166656906466 ps |
| CPU time | 923.78 seconds |
| Started | Oct 09 05:50:50 AM UTC 24 |
| Finished | Oct 09 06:06:25 AM UTC 24 |
| Peak memory | 209688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458188272 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3458188272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_loopback.3746159914 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 6921928181 ps |
| CPU time | 10.3 seconds |
| Started | Oct 09 05:50:50 AM UTC 24 |
| Finished | Oct 09 05:51:02 AM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746159914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3746159914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_noise_filter.1381649366 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 41984146317 ps |
| CPU time | 42.72 seconds |
| Started | Oct 09 05:50:43 AM UTC 24 |
| Finished | Oct 09 05:51:27 AM UTC 24 |
| Peak memory | 208568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381649366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1381649366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_perf.109612877 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 21551984687 ps |
| CPU time | 277.29 seconds |
| Started | Oct 09 05:50:50 AM UTC 24 |
| Finished | Oct 09 05:55:31 AM UTC 24 |
| Peak memory | 209476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109612877 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.109612877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_rx_oversample.1112246310 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 6645314216 ps |
| CPU time | 9.12 seconds |
| Started | Oct 09 05:50:38 AM UTC 24 |
| Finished | Oct 09 05:50:48 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112246310 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1112246310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.1450884157 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 84415209845 ps |
| CPU time | 245.33 seconds |
| Started | Oct 09 05:50:48 AM UTC 24 |
| Finished | Oct 09 05:54:57 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450884157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1450884157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.1771723046 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 626236174 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 05:50:45 AM UTC 24 |
| Finished | Oct 09 05:50:50 AM UTC 24 |
| Peak memory | 203988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771723046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1771723046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_smoke.4167311728 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 428810112 ps |
| CPU time | 3.65 seconds |
| Started | Oct 09 05:50:32 AM UTC 24 |
| Finished | Oct 09 05:50:37 AM UTC 24 |
| Peak memory | 203872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167311728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4167311728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_stress_all.96264223 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 183832598965 ps |
| CPU time | 314.66 seconds |
| Started | Oct 09 05:50:56 AM UTC 24 |
| Finished | Oct 09 05:56:14 AM UTC 24 |
| Peak memory | 206252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96264223 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.96264223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.2804304732 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 21300903027 ps |
| CPU time | 31.06 seconds |
| Started | Oct 09 05:50:52 AM UTC 24 |
| Finished | Oct 09 05:51:25 AM UTC 24 |
| Peak memory | 218468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2804304732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all _with_rand_reset.2804304732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.1662628418 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 6561696856 ps |
| CPU time | 19.96 seconds |
| Started | Oct 09 05:50:49 AM UTC 24 |
| Finished | Oct 09 05:51:10 AM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662628418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1662628418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_tx_rx.2505760718 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 14985137138 ps |
| CPU time | 29.3 seconds |
| Started | Oct 09 05:50:33 AM UTC 24 |
| Finished | Oct 09 05:51:04 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505760718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2505760718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/47.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_alert_test.2405875284 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 21771854 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:51:17 AM UTC 24 |
| Finished | Oct 09 05:51:19 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405875284 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2405875284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_fifo_full.206522279 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 152518513189 ps |
| CPU time | 431.5 seconds |
| Started | Oct 09 05:51:01 AM UTC 24 |
| Finished | Oct 09 05:58:18 AM UTC 24 |
| Peak memory | 209544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206522279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.206522279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.1553007508 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 87468375120 ps |
| CPU time | 100.15 seconds |
| Started | Oct 09 05:51:03 AM UTC 24 |
| Finished | Oct 09 05:52:45 AM UTC 24 |
| Peak memory | 208920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553007508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1553007508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_fifo_reset.987191005 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 65591363291 ps |
| CPU time | 41.25 seconds |
| Started | Oct 09 05:51:04 AM UTC 24 |
| Finished | Oct 09 05:51:47 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987191005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.987191005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_intr.2280183741 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 71331148951 ps |
| CPU time | 116.11 seconds |
| Started | Oct 09 05:51:06 AM UTC 24 |
| Finished | Oct 09 05:53:05 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280183741 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2280183741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.238164360 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 129978219208 ps |
| CPU time | 294.05 seconds |
| Started | Oct 09 05:51:13 AM UTC 24 |
| Finished | Oct 09 05:56:12 AM UTC 24 |
| Peak memory | 204320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238164360 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.238164360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_loopback.1242424795 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 6961406332 ps |
| CPU time | 7.52 seconds |
| Started | Oct 09 05:51:11 AM UTC 24 |
| Finished | Oct 09 05:51:19 AM UTC 24 |
| Peak memory | 204080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242424795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1242424795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_noise_filter.2306554699 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 118765454875 ps |
| CPU time | 241.61 seconds |
| Started | Oct 09 05:51:06 AM UTC 24 |
| Finished | Oct 09 05:55:11 AM UTC 24 |
| Peak memory | 208312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306554699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2306554699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_perf.225888606 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 34111259021 ps |
| CPU time | 256.13 seconds |
| Started | Oct 09 05:51:11 AM UTC 24 |
| Finished | Oct 09 05:55:31 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225888606 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.225888606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_rx_oversample.463817015 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 6083634279 ps |
| CPU time | 3.76 seconds |
| Started | Oct 09 05:51:05 AM UTC 24 |
| Finished | Oct 09 05:51:10 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463817015 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.463817015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.1252844950 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 19947424099 ps |
| CPU time | 33.89 seconds |
| Started | Oct 09 05:51:09 AM UTC 24 |
| Finished | Oct 09 05:51:44 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252844950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1252844950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.3411012372 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 6728597065 ps |
| CPU time | 7.36 seconds |
| Started | Oct 09 05:51:08 AM UTC 24 |
| Finished | Oct 09 05:51:16 AM UTC 24 |
| Peak memory | 203724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411012372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3411012372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_smoke.1213673901 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 6245163288 ps |
| CPU time | 12.97 seconds |
| Started | Oct 09 05:51:00 AM UTC 24 |
| Finished | Oct 09 05:51:14 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213673901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1213673901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_stress_all.1430964472 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 155448607308 ps |
| CPU time | 375.95 seconds |
| Started | Oct 09 05:51:15 AM UTC 24 |
| Finished | Oct 09 05:57:36 AM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430964472 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1430964472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.3514008895 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 1893595779 ps |
| CPU time | 38.47 seconds |
| Started | Oct 09 05:51:15 AM UTC 24 |
| Finished | Oct 09 05:51:55 AM UTC 24 |
| Peak memory | 220824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3514008895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all _with_rand_reset.3514008895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.4180387754 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 809667694 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 05:51:10 AM UTC 24 |
| Finished | Oct 09 05:51:14 AM UTC 24 |
| Peak memory | 203948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180387754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.4180387754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/48.uart_tx_rx.3745142251 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 33682905462 ps |
| CPU time | 33.35 seconds |
| Started | Oct 09 05:51:01 AM UTC 24 |
| Finished | Oct 09 05:51:36 AM UTC 24 |
| Peak memory | 209736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745142251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3745142251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/48.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_alert_test.3854011780 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 11444205 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:51:47 AM UTC 24 |
| Finished | Oct 09 05:51:49 AM UTC 24 |
| Peak memory | 203404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854011780 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3854011780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_fifo_full.3625172379 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 76979924104 ps |
| CPU time | 147.59 seconds |
| Started | Oct 09 05:51:24 AM UTC 24 |
| Finished | Oct 09 05:53:54 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625172379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3625172379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.2925177068 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 40179012060 ps |
| CPU time | 30.45 seconds |
| Started | Oct 09 05:51:25 AM UTC 24 |
| Finished | Oct 09 05:51:57 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925177068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2925177068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_intr.1693272094 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 21396211617 ps |
| CPU time | 54.17 seconds |
| Started | Oct 09 05:51:29 AM UTC 24 |
| Finished | Oct 09 05:52:25 AM UTC 24 |
| Peak memory | 204060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693272094 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1693272094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.1751320536 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 110641272798 ps |
| CPU time | 832.38 seconds |
| Started | Oct 09 05:51:45 AM UTC 24 |
| Finished | Oct 09 06:05:48 AM UTC 24 |
| Peak memory | 207440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751320536 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1751320536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_loopback.4123895868 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 3257793472 ps |
| CPU time | 3.9 seconds |
| Started | Oct 09 05:51:42 AM UTC 24 |
| Finished | Oct 09 05:51:46 AM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123895868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.uart_loopback.4123895868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_noise_filter.939159450 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 81868312051 ps |
| CPU time | 264.16 seconds |
| Started | Oct 09 05:51:34 AM UTC 24 |
| Finished | Oct 09 05:56:02 AM UTC 24 |
| Peak memory | 209696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939159450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.939159450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_perf.2677937218 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 21553260571 ps |
| CPU time | 262.73 seconds |
| Started | Oct 09 05:51:44 AM UTC 24 |
| Finished | Oct 09 05:56:10 AM UTC 24 |
| Peak memory | 203928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677937218 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2677937218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_rx_oversample.873529851 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2255116781 ps |
| CPU time | 3.79 seconds |
| Started | Oct 09 05:51:28 AM UTC 24 |
| Finished | Oct 09 05:51:33 AM UTC 24 |
| Peak memory | 204332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873529851 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.873529851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.3942789341 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 212937098771 ps |
| CPU time | 129.16 seconds |
| Started | Oct 09 05:51:37 AM UTC 24 |
| Finished | Oct 09 05:53:49 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942789341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3942789341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.3280947556 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 1377093449 ps |
| CPU time | 3.22 seconds |
| Started | Oct 09 05:51:36 AM UTC 24 |
| Finished | Oct 09 05:51:40 AM UTC 24 |
| Peak memory | 203988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280947556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3280947556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_smoke.2218303129 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 5769481532 ps |
| CPU time | 19.53 seconds |
| Started | Oct 09 05:51:20 AM UTC 24 |
| Finished | Oct 09 05:51:41 AM UTC 24 |
| Peak memory | 204068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218303129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2218303129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_stress_all.201646288 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 183634948535 ps |
| CPU time | 216.4 seconds |
| Started | Oct 09 05:51:46 AM UTC 24 |
| Finished | Oct 09 05:55:26 AM UTC 24 |
| Peak memory | 206120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201646288 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.201646288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.3842607399 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 15127693566 ps |
| CPU time | 69.44 seconds |
| Started | Oct 09 05:51:46 AM UTC 24 |
| Finished | Oct 09 05:52:57 AM UTC 24 |
| Peak memory | 226524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3842607399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all _with_rand_reset.3842607399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.836918406 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 867752545 ps |
| CPU time | 2.93 seconds |
| Started | Oct 09 05:51:41 AM UTC 24 |
| Finished | Oct 09 05:51:45 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836918406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.836918406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_tx_rx.160624239 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2405079195 ps |
| CPU time | 6.89 seconds |
| Started | Oct 09 05:51:20 AM UTC 24 |
| Finished | Oct 09 05:51:28 AM UTC 24 |
| Peak memory | 203732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160624239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.160624239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/49.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_alert_test.3520390605 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 13711732 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:28:03 AM UTC 24 |
| Finished | Oct 09 05:28:05 AM UTC 24 |
| Peak memory | 203408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520390605 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3520390605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_fifo_full.608586417 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 122262431070 ps |
| CPU time | 287.42 seconds |
| Started | Oct 09 05:27:44 AM UTC 24 |
| Finished | Oct 09 05:32:35 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608586417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.608586417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.3153369339 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 29613052933 ps |
| CPU time | 54.85 seconds |
| Started | Oct 09 05:27:44 AM UTC 24 |
| Finished | Oct 09 05:28:40 AM UTC 24 |
| Peak memory | 208952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153369339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3153369339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_fifo_reset.837713353 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 48553614824 ps |
| CPU time | 32.09 seconds |
| Started | Oct 09 05:27:46 AM UTC 24 |
| Finished | Oct 09 05:28:20 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837713353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.837713353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_intr.63886004 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 3993793996 ps |
| CPU time | 3.15 seconds |
| Started | Oct 09 05:27:46 AM UTC 24 |
| Finished | Oct 09 05:27:51 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63886004 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.63886004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.1339140253 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 110322543395 ps |
| CPU time | 448.46 seconds |
| Started | Oct 09 05:27:56 AM UTC 24 |
| Finished | Oct 09 05:35:31 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339140253 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1339140253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_loopback.2382091671 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 6753227205 ps |
| CPU time | 11.26 seconds |
| Started | Oct 09 05:27:52 AM UTC 24 |
| Finished | Oct 09 05:28:04 AM UTC 24 |
| Peak memory | 204208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382091671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2382091671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_noise_filter.4200594910 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 25011765122 ps |
| CPU time | 69.07 seconds |
| Started | Oct 09 05:27:49 AM UTC 24 |
| Finished | Oct 09 05:29:00 AM UTC 24 |
| Peak memory | 209756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200594910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.4200594910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_perf.2654460693 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 10510153707 ps |
| CPU time | 119.68 seconds |
| Started | Oct 09 05:27:54 AM UTC 24 |
| Finished | Oct 09 05:29:56 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654460693 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2654460693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_rx_oversample.1555006474 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4215113823 ps |
| CPU time | 11.58 seconds |
| Started | Oct 09 05:27:46 AM UTC 24 |
| Finished | Oct 09 05:27:59 AM UTC 24 |
| Peak memory | 204076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555006474 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1555006474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.4003829244 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 33585914064 ps |
| CPU time | 86.26 seconds |
| Started | Oct 09 05:27:50 AM UTC 24 |
| Finished | Oct 09 05:29:18 AM UTC 24 |
| Peak memory | 204276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003829244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.4003829244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.986107302 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 25007522355 ps |
| CPU time | 34.61 seconds |
| Started | Oct 09 05:27:49 AM UTC 24 |
| Finished | Oct 09 05:28:25 AM UTC 24 |
| Peak memory | 204052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986107302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.986107302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_smoke.2335827555 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 443388074 ps |
| CPU time | 3.4 seconds |
| Started | Oct 09 05:27:41 AM UTC 24 |
| Finished | Oct 09 05:27:46 AM UTC 24 |
| Peak memory | 203876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335827555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2335827555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_stress_all.4156859960 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 24021180178 ps |
| CPU time | 43.3 seconds |
| Started | Oct 09 05:28:00 AM UTC 24 |
| Finished | Oct 09 05:28:45 AM UTC 24 |
| Peak memory | 204076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156859960 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.4156859960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.1184618116 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4181768518 ps |
| CPU time | 71.26 seconds |
| Started | Oct 09 05:28:00 AM UTC 24 |
| Finished | Oct 09 05:29:13 AM UTC 24 |
| Peak memory | 209672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1184618116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_ with_rand_reset.1184618116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.310240190 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 6844390957 ps |
| CPU time | 31.16 seconds |
| Started | Oct 09 05:27:50 AM UTC 24 |
| Finished | Oct 09 05:28:22 AM UTC 24 |
| Peak memory | 204016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310240190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.310240190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/5.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/50.uart_fifo_reset.827609067 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 9143011651 ps |
| CPU time | 27.34 seconds |
| Started | Oct 09 05:51:48 AM UTC 24 |
| Finished | Oct 09 05:52:17 AM UTC 24 |
| Peak memory | 209220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827609067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.827609067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/50.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.1324634537 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 1824217867 ps |
| CPU time | 14.42 seconds |
| Started | Oct 09 05:51:49 AM UTC 24 |
| Finished | Oct 09 05:52:05 AM UTC 24 |
| Peak memory | 223952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1324634537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all _with_rand_reset.1324634537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/51.uart_fifo_reset.2481046542 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 37871738976 ps |
| CPU time | 37.94 seconds |
| Started | Oct 09 05:51:54 AM UTC 24 |
| Finished | Oct 09 05:52:34 AM UTC 24 |
| Peak memory | 209624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481046542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2481046542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/51.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.3516276334 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 12932431147 ps |
| CPU time | 53.51 seconds |
| Started | Oct 09 05:51:56 AM UTC 24 |
| Finished | Oct 09 05:52:51 AM UTC 24 |
| Peak memory | 218776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3516276334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all _with_rand_reset.3516276334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/52.uart_fifo_reset.1883559689 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 10537470865 ps |
| CPU time | 13.61 seconds |
| Started | Oct 09 05:51:57 AM UTC 24 |
| Finished | Oct 09 05:52:12 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883559689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1883559689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/52.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.912701690 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 11427488463 ps |
| CPU time | 21.94 seconds |
| Started | Oct 09 05:51:57 AM UTC 24 |
| Finished | Oct 09 05:52:21 AM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=912701690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all_ with_rand_reset.912701690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.2144144839 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 11327183862 ps |
| CPU time | 99.64 seconds |
| Started | Oct 09 05:52:13 AM UTC 24 |
| Finished | Oct 09 05:53:54 AM UTC 24 |
| Peak memory | 209684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2144144839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all _with_rand_reset.2144144839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/54.uart_fifo_reset.1095998638 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 62992300368 ps |
| CPU time | 34.55 seconds |
| Started | Oct 09 05:52:17 AM UTC 24 |
| Finished | Oct 09 05:52:53 AM UTC 24 |
| Peak memory | 209620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095998638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1095998638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/54.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.1293198040 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 2892220699 ps |
| CPU time | 12.35 seconds |
| Started | Oct 09 05:52:17 AM UTC 24 |
| Finished | Oct 09 05:52:30 AM UTC 24 |
| Peak memory | 218880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1293198040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all _with_rand_reset.1293198040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.1272938142 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 11369378077 ps |
| CPU time | 91.15 seconds |
| Started | Oct 09 05:52:18 AM UTC 24 |
| Finished | Oct 09 05:53:51 AM UTC 24 |
| Peak memory | 222732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1272938142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all _with_rand_reset.1272938142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/56.uart_fifo_reset.546236619 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 75395752670 ps |
| CPU time | 111.47 seconds |
| Started | Oct 09 05:52:21 AM UTC 24 |
| Finished | Oct 09 05:54:15 AM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546236619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.546236619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/56.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.2968441919 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 874526164 ps |
| CPU time | 18.23 seconds |
| Started | Oct 09 05:52:22 AM UTC 24 |
| Finished | Oct 09 05:52:42 AM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2968441919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all _with_rand_reset.2968441919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/57.uart_fifo_reset.4099940202 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 80612375635 ps |
| CPU time | 81.16 seconds |
| Started | Oct 09 05:52:25 AM UTC 24 |
| Finished | Oct 09 05:53:49 AM UTC 24 |
| Peak memory | 209520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099940202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.4099940202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/57.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.1095645074 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 2518074087 ps |
| CPU time | 29.82 seconds |
| Started | Oct 09 05:52:31 AM UTC 24 |
| Finished | Oct 09 05:53:03 AM UTC 24 |
| Peak memory | 218448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1095645074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all _with_rand_reset.1095645074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/58.uart_fifo_reset.1224663196 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 15239458748 ps |
| CPU time | 22.74 seconds |
| Started | Oct 09 05:52:34 AM UTC 24 |
| Finished | Oct 09 05:52:59 AM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224663196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1224663196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/58.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.2835266839 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 17485306450 ps |
| CPU time | 102.89 seconds |
| Started | Oct 09 05:52:37 AM UTC 24 |
| Finished | Oct 09 05:54:22 AM UTC 24 |
| Peak memory | 224668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2835266839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all _with_rand_reset.2835266839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/59.uart_fifo_reset.1850615601 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 25225052014 ps |
| CPU time | 55.37 seconds |
| Started | Oct 09 05:52:43 AM UTC 24 |
| Finished | Oct 09 05:53:40 AM UTC 24 |
| Peak memory | 209692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850615601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1850615601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/59.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.3636850649 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 3080249675 ps |
| CPU time | 55.55 seconds |
| Started | Oct 09 05:52:46 AM UTC 24 |
| Finished | Oct 09 05:53:43 AM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3636850649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all _with_rand_reset.3636850649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_alert_test.4171758201 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 13107781 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 05:28:30 AM UTC 24 |
| Finished | Oct 09 05:28:32 AM UTC 24 |
| Peak memory | 203408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171758201 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.4171758201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_fifo_full.448852382 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 23947605628 ps |
| CPU time | 17.06 seconds |
| Started | Oct 09 05:28:05 AM UTC 24 |
| Finished | Oct 09 05:28:24 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448852382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.448852382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.19370331 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 75314273584 ps |
| CPU time | 42.93 seconds |
| Started | Oct 09 05:28:05 AM UTC 24 |
| Finished | Oct 09 05:28:50 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19370331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.19370331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_fifo_reset.3673900556 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 18821882591 ps |
| CPU time | 22.57 seconds |
| Started | Oct 09 05:28:07 AM UTC 24 |
| Finished | Oct 09 05:28:31 AM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673900556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3673900556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_intr.3706341690 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 24443362962 ps |
| CPU time | 75.11 seconds |
| Started | Oct 09 05:28:09 AM UTC 24 |
| Finished | Oct 09 05:29:26 AM UTC 24 |
| Peak memory | 209548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706341690 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3706341690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.3737361636 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 96541103560 ps |
| CPU time | 562.89 seconds |
| Started | Oct 09 05:28:24 AM UTC 24 |
| Finished | Oct 09 05:37:54 AM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737361636 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3737361636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_loopback.24559007 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 3155397847 ps |
| CPU time | 14.03 seconds |
| Started | Oct 09 05:28:20 AM UTC 24 |
| Finished | Oct 09 05:28:35 AM UTC 24 |
| Peak memory | 204088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24559007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.uart_loopback.24559007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_noise_filter.2444139150 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 160875517972 ps |
| CPU time | 415.64 seconds |
| Started | Oct 09 05:28:10 AM UTC 24 |
| Finished | Oct 09 05:35:11 AM UTC 24 |
| Peak memory | 209756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444139150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2444139150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_perf.1991407692 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 5495284780 ps |
| CPU time | 383.04 seconds |
| Started | Oct 09 05:28:23 AM UTC 24 |
| Finished | Oct 09 05:34:52 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991407692 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1991407692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_rx_oversample.2829870337 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2011711008 ps |
| CPU time | 3.36 seconds |
| Started | Oct 09 05:28:07 AM UTC 24 |
| Finished | Oct 09 05:28:12 AM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829870337 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2829870337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.317170278 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 18382390334 ps |
| CPU time | 40.8 seconds |
| Started | Oct 09 05:28:13 AM UTC 24 |
| Finished | Oct 09 05:28:55 AM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317170278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.317170278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.3439661336 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 46576834744 ps |
| CPU time | 19.8 seconds |
| Started | Oct 09 05:28:12 AM UTC 24 |
| Finished | Oct 09 05:28:33 AM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439661336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3439661336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_smoke.269829768 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 261766974 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 05:28:03 AM UTC 24 |
| Finished | Oct 09 05:28:06 AM UTC 24 |
| Peak memory | 204200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269829768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 6.uart_smoke.269829768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.3391907042 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4311133075 ps |
| CPU time | 36.1 seconds |
| Started | Oct 09 05:28:26 AM UTC 24 |
| Finished | Oct 09 05:29:03 AM UTC 24 |
| Peak memory | 209064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3391907042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_ with_rand_reset.3391907042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.362745969 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1152959872 ps |
| CPU time | 5.78 seconds |
| Started | Oct 09 05:28:18 AM UTC 24 |
| Finished | Oct 09 05:28:25 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362745969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.362745969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/6.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/60.uart_fifo_reset.1861980962 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 52922149429 ps |
| CPU time | 312.86 seconds |
| Started | Oct 09 05:52:52 AM UTC 24 |
| Finished | Oct 09 05:58:09 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861980962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1861980962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/60.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.3082814855 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 1691453736 ps |
| CPU time | 11.82 seconds |
| Started | Oct 09 05:52:54 AM UTC 24 |
| Finished | Oct 09 05:53:07 AM UTC 24 |
| Peak memory | 218444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3082814855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all _with_rand_reset.3082814855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/61.uart_fifo_reset.3135718779 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 57226176161 ps |
| CPU time | 18.19 seconds |
| Started | Oct 09 05:52:58 AM UTC 24 |
| Finished | Oct 09 05:53:17 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135718779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3135718779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/61.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.1162964132 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 619293724 ps |
| CPU time | 4.25 seconds |
| Started | Oct 09 05:52:59 AM UTC 24 |
| Finished | Oct 09 05:53:04 AM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1162964132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all _with_rand_reset.1162964132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/62.uart_fifo_reset.1477818218 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 42411159601 ps |
| CPU time | 82.74 seconds |
| Started | Oct 09 05:53:02 AM UTC 24 |
| Finished | Oct 09 05:54:27 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477818218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1477818218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/62.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.2835715645 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 4255578537 ps |
| CPU time | 95.93 seconds |
| Started | Oct 09 05:53:03 AM UTC 24 |
| Finished | Oct 09 05:54:41 AM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2835715645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all _with_rand_reset.2835715645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/63.uart_fifo_reset.2800478773 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 19804486792 ps |
| CPU time | 60.24 seconds |
| Started | Oct 09 05:53:03 AM UTC 24 |
| Finished | Oct 09 05:54:05 AM UTC 24 |
| Peak memory | 209280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800478773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2800478773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/63.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.3422081793 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 26189596124 ps |
| CPU time | 62.8 seconds |
| Started | Oct 09 05:53:05 AM UTC 24 |
| Finished | Oct 09 05:54:10 AM UTC 24 |
| Peak memory | 226116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3422081793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all _with_rand_reset.3422081793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/64.uart_fifo_reset.1460874283 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 131440126315 ps |
| CPU time | 146.33 seconds |
| Started | Oct 09 05:53:06 AM UTC 24 |
| Finished | Oct 09 05:55:34 AM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460874283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1460874283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/64.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.2522111301 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 1377709686 ps |
| CPU time | 26.58 seconds |
| Started | Oct 09 05:53:06 AM UTC 24 |
| Finished | Oct 09 05:53:33 AM UTC 24 |
| Peak memory | 218916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2522111301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all _with_rand_reset.2522111301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/65.uart_fifo_reset.479906849 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 72633169078 ps |
| CPU time | 22.25 seconds |
| Started | Oct 09 05:53:07 AM UTC 24 |
| Finished | Oct 09 05:53:30 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479906849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.479906849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/65.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.2709700366 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 12420868739 ps |
| CPU time | 43.3 seconds |
| Started | Oct 09 05:53:08 AM UTC 24 |
| Finished | Oct 09 05:53:53 AM UTC 24 |
| Peak memory | 220828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2709700366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all _with_rand_reset.2709700366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/66.uart_fifo_reset.2717790281 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 31637714678 ps |
| CPU time | 37.06 seconds |
| Started | Oct 09 05:53:17 AM UTC 24 |
| Finished | Oct 09 05:53:55 AM UTC 24 |
| Peak memory | 204332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717790281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2717790281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/66.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.1449371525 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 994954395 ps |
| CPU time | 15.1 seconds |
| Started | Oct 09 05:53:18 AM UTC 24 |
| Finished | Oct 09 05:53:34 AM UTC 24 |
| Peak memory | 218916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1449371525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all _with_rand_reset.1449371525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/67.uart_fifo_reset.1638680406 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 35302267233 ps |
| CPU time | 13.33 seconds |
| Started | Oct 09 05:53:31 AM UTC 24 |
| Finished | Oct 09 05:53:46 AM UTC 24 |
| Peak memory | 209424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638680406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1638680406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/67.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.122388132 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 619848174 ps |
| CPU time | 12.16 seconds |
| Started | Oct 09 05:53:34 AM UTC 24 |
| Finished | Oct 09 05:53:48 AM UTC 24 |
| Peak memory | 209956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=122388132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all_ with_rand_reset.122388132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/68.uart_fifo_reset.1208515172 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 109410015730 ps |
| CPU time | 44.06 seconds |
| Started | Oct 09 05:53:34 AM UTC 24 |
| Finished | Oct 09 05:54:20 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208515172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1208515172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/68.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.1688311517 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 15248084432 ps |
| CPU time | 50.93 seconds |
| Started | Oct 09 05:53:35 AM UTC 24 |
| Finished | Oct 09 05:54:28 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1688311517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all _with_rand_reset.1688311517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/69.uart_fifo_reset.1337314047 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 23360475829 ps |
| CPU time | 67.53 seconds |
| Started | Oct 09 05:53:40 AM UTC 24 |
| Finished | Oct 09 05:54:50 AM UTC 24 |
| Peak memory | 209572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337314047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1337314047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/69.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.2099996985 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1902401450 ps |
| CPU time | 19.87 seconds |
| Started | Oct 09 05:53:44 AM UTC 24 |
| Finished | Oct 09 05:54:05 AM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2099996985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all _with_rand_reset.2099996985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_alert_test.1490826022 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 53147840 ps |
| CPU time | 0.9 seconds |
| Started | Oct 09 05:28:57 AM UTC 24 |
| Finished | Oct 09 05:28:59 AM UTC 24 |
| Peak memory | 203408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490826022 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1490826022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_fifo_full.727560882 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 78799650789 ps |
| CPU time | 50.87 seconds |
| Started | Oct 09 05:28:34 AM UTC 24 |
| Finished | Oct 09 05:29:26 AM UTC 24 |
| Peak memory | 209568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727560882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.727560882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_intr.1310324174 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 26989309393 ps |
| CPU time | 76.2 seconds |
| Started | Oct 09 05:28:37 AM UTC 24 |
| Finished | Oct 09 05:29:55 AM UTC 24 |
| Peak memory | 204056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310324174 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1310324174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_loopback.2139609637 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 3957467418 ps |
| CPU time | 19.42 seconds |
| Started | Oct 09 05:28:48 AM UTC 24 |
| Finished | Oct 09 05:29:09 AM UTC 24 |
| Peak memory | 204064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139609637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2139609637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_noise_filter.1161416055 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 30053590026 ps |
| CPU time | 15.35 seconds |
| Started | Oct 09 05:28:40 AM UTC 24 |
| Finished | Oct 09 05:28:56 AM UTC 24 |
| Peak memory | 206048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161416055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1161416055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_perf.2345118508 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 17664779519 ps |
| CPU time | 575.3 seconds |
| Started | Oct 09 05:28:48 AM UTC 24 |
| Finished | Oct 09 05:38:31 AM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345118508 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2345118508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_rx_oversample.227661136 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 5857105128 ps |
| CPU time | 30.47 seconds |
| Started | Oct 09 05:28:36 AM UTC 24 |
| Finished | Oct 09 05:29:08 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227661136 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.227661136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.26866736 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 27641746903 ps |
| CPU time | 26.03 seconds |
| Started | Oct 09 05:28:46 AM UTC 24 |
| Finished | Oct 09 05:29:14 AM UTC 24 |
| Peak memory | 209040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26866736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.26866736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.2734801894 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3826792882 ps |
| CPU time | 8.82 seconds |
| Started | Oct 09 05:28:42 AM UTC 24 |
| Finished | Oct 09 05:28:52 AM UTC 24 |
| Peak memory | 203800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734801894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2734801894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_smoke.4092279661 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 109046283 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 05:28:32 AM UTC 24 |
| Finished | Oct 09 05:28:34 AM UTC 24 |
| Peak memory | 205332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092279661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.uart_smoke.4092279661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_stress_all.780339343 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 66921106284 ps |
| CPU time | 39.14 seconds |
| Started | Oct 09 05:28:55 AM UTC 24 |
| Finished | Oct 09 05:29:36 AM UTC 24 |
| Peak memory | 204344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780339343 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.780339343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.2881997173 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7819804614 ps |
| CPU time | 51.96 seconds |
| Started | Oct 09 05:28:52 AM UTC 24 |
| Finished | Oct 09 05:29:46 AM UTC 24 |
| Peak memory | 224868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2881997173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_ with_rand_reset.2881997173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.2283669654 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6604851211 ps |
| CPU time | 12.42 seconds |
| Started | Oct 09 05:28:46 AM UTC 24 |
| Finished | Oct 09 05:29:00 AM UTC 24 |
| Peak memory | 204132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283669654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2283669654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_tx_rx.118247469 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 34296847935 ps |
| CPU time | 21.17 seconds |
| Started | Oct 09 05:28:33 AM UTC 24 |
| Finished | Oct 09 05:28:55 AM UTC 24 |
| Peak memory | 209740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118247469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.118247469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/7.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/70.uart_fifo_reset.695626413 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 288762055723 ps |
| CPU time | 106.28 seconds |
| Started | Oct 09 05:53:46 AM UTC 24 |
| Finished | Oct 09 05:55:34 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695626413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.695626413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/70.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.1438358770 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 27518099678 ps |
| CPU time | 32.26 seconds |
| Started | Oct 09 05:53:47 AM UTC 24 |
| Finished | Oct 09 05:54:20 AM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1438358770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all _with_rand_reset.1438358770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/72.uart_fifo_reset.1213853644 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 46367355338 ps |
| CPU time | 96.52 seconds |
| Started | Oct 09 05:53:50 AM UTC 24 |
| Finished | Oct 09 05:55:29 AM UTC 24 |
| Peak memory | 209200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213853644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1213853644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/72.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.2782627137 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 1306878286 ps |
| CPU time | 22.59 seconds |
| Started | Oct 09 05:53:54 AM UTC 24 |
| Finished | Oct 09 05:54:19 AM UTC 24 |
| Peak memory | 218096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2782627137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all _with_rand_reset.2782627137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/74.uart_fifo_reset.1246195523 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 23369628690 ps |
| CPU time | 115.5 seconds |
| Started | Oct 09 05:53:55 AM UTC 24 |
| Finished | Oct 09 05:55:53 AM UTC 24 |
| Peak memory | 209480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246195523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1246195523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/74.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.1938510090 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 10957259188 ps |
| CPU time | 69.03 seconds |
| Started | Oct 09 05:53:56 AM UTC 24 |
| Finished | Oct 09 05:55:08 AM UTC 24 |
| Peak memory | 220736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1938510090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all _with_rand_reset.1938510090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/75.uart_fifo_reset.3984338061 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 43999472937 ps |
| CPU time | 83.13 seconds |
| Started | Oct 09 05:54:06 AM UTC 24 |
| Finished | Oct 09 05:55:31 AM UTC 24 |
| Peak memory | 203940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984338061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3984338061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/75.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.3939135879 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 51331565072 ps |
| CPU time | 93.86 seconds |
| Started | Oct 09 05:54:06 AM UTC 24 |
| Finished | Oct 09 05:55:42 AM UTC 24 |
| Peak memory | 223072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3939135879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all _with_rand_reset.3939135879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/76.uart_fifo_reset.775032859 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 16321260383 ps |
| CPU time | 36.07 seconds |
| Started | Oct 09 05:54:11 AM UTC 24 |
| Finished | Oct 09 05:54:48 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775032859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.775032859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/76.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.1920934392 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 4635489814 ps |
| CPU time | 20.48 seconds |
| Started | Oct 09 05:54:16 AM UTC 24 |
| Finished | Oct 09 05:54:38 AM UTC 24 |
| Peak memory | 218720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1920934392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all _with_rand_reset.1920934392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/77.uart_fifo_reset.3460458376 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 55208207187 ps |
| CPU time | 60.87 seconds |
| Started | Oct 09 05:54:19 AM UTC 24 |
| Finished | Oct 09 05:55:22 AM UTC 24 |
| Peak memory | 204404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460458376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3460458376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/77.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.1338022697 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 2064974823 ps |
| CPU time | 42.33 seconds |
| Started | Oct 09 05:54:21 AM UTC 24 |
| Finished | Oct 09 05:55:05 AM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1338022697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all _with_rand_reset.1338022697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/78.uart_fifo_reset.3589418795 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 15377179732 ps |
| CPU time | 15.61 seconds |
| Started | Oct 09 05:54:21 AM UTC 24 |
| Finished | Oct 09 05:54:38 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589418795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3589418795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/78.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.1114176971 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 4456407003 ps |
| CPU time | 65 seconds |
| Started | Oct 09 05:54:22 AM UTC 24 |
| Finished | Oct 09 05:55:29 AM UTC 24 |
| Peak memory | 220768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1114176971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all _with_rand_reset.1114176971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/79.uart_fifo_reset.4054422385 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 140370808527 ps |
| CPU time | 223.91 seconds |
| Started | Oct 09 05:54:27 AM UTC 24 |
| Finished | Oct 09 05:58:14 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054422385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.4054422385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/79.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.4151615737 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 6817183946 ps |
| CPU time | 28.05 seconds |
| Started | Oct 09 05:54:28 AM UTC 24 |
| Finished | Oct 09 05:54:58 AM UTC 24 |
| Peak memory | 218436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4151615737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all _with_rand_reset.4151615737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_alert_test.1459368748 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 28960124 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 05:29:22 AM UTC 24 |
| Finished | Oct 09 05:29:24 AM UTC 24 |
| Peak memory | 203408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459368748 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1459368748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_fifo_full.3675073914 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 153841547652 ps |
| CPU time | 121.93 seconds |
| Started | Oct 09 05:29:00 AM UTC 24 |
| Finished | Oct 09 05:31:04 AM UTC 24 |
| Peak memory | 204020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675073914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3675073914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.4276684499 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 63692164937 ps |
| CPU time | 67.12 seconds |
| Started | Oct 09 05:29:01 AM UTC 24 |
| Finished | Oct 09 05:30:10 AM UTC 24 |
| Peak memory | 209552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276684499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.4276684499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_fifo_reset.2210735487 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 127732064264 ps |
| CPU time | 206.27 seconds |
| Started | Oct 09 05:29:01 AM UTC 24 |
| Finished | Oct 09 05:32:31 AM UTC 24 |
| Peak memory | 209444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210735487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2210735487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_intr.3956666426 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 256371556999 ps |
| CPU time | 161.18 seconds |
| Started | Oct 09 05:29:04 AM UTC 24 |
| Finished | Oct 09 05:31:48 AM UTC 24 |
| Peak memory | 204312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956666426 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3956666426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_loopback.3538623036 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1789671535 ps |
| CPU time | 4.36 seconds |
| Started | Oct 09 05:29:16 AM UTC 24 |
| Finished | Oct 09 05:29:21 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538623036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3538623036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_noise_filter.99153500 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 9999628827 ps |
| CPU time | 25.4 seconds |
| Started | Oct 09 05:29:09 AM UTC 24 |
| Finished | Oct 09 05:29:36 AM UTC 24 |
| Peak memory | 206052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99153500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.99153500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_perf.629986925 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 24163754733 ps |
| CPU time | 791.21 seconds |
| Started | Oct 09 05:29:17 AM UTC 24 |
| Finished | Oct 09 05:42:37 AM UTC 24 |
| Peak memory | 207328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629986925 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.629986925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_rx_oversample.153705421 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 5330282094 ps |
| CPU time | 26.48 seconds |
| Started | Oct 09 05:29:01 AM UTC 24 |
| Finished | Oct 09 05:29:29 AM UTC 24 |
| Peak memory | 204332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153705421 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.153705421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.1444811024 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 172605534088 ps |
| CPU time | 268.49 seconds |
| Started | Oct 09 05:29:14 AM UTC 24 |
| Finished | Oct 09 05:33:47 AM UTC 24 |
| Peak memory | 209492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444811024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1444811024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.3391914249 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4840735041 ps |
| CPU time | 16.91 seconds |
| Started | Oct 09 05:29:09 AM UTC 24 |
| Finished | Oct 09 05:29:28 AM UTC 24 |
| Peak memory | 203728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391914249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3391914249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_smoke.3166079843 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 511990549 ps |
| CPU time | 2.09 seconds |
| Started | Oct 09 05:28:57 AM UTC 24 |
| Finished | Oct 09 05:29:00 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166079843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3166079843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.3410266252 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1093688626 ps |
| CPU time | 6 seconds |
| Started | Oct 09 05:29:14 AM UTC 24 |
| Finished | Oct 09 05:29:22 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410266252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3410266252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_tx_rx.3672845352 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 88512965632 ps |
| CPU time | 29.47 seconds |
| Started | Oct 09 05:28:57 AM UTC 24 |
| Finished | Oct 09 05:29:28 AM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672845352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3672845352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/8.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/80.uart_fifo_reset.1995112545 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 21384337343 ps |
| CPU time | 65.57 seconds |
| Started | Oct 09 05:54:28 AM UTC 24 |
| Finished | Oct 09 05:55:36 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995112545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1995112545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/80.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.1943891405 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 2119977001 ps |
| CPU time | 36.89 seconds |
| Started | Oct 09 05:54:39 AM UTC 24 |
| Finished | Oct 09 05:55:17 AM UTC 24 |
| Peak memory | 220440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1943891405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all _with_rand_reset.1943891405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/81.uart_fifo_reset.1656550202 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 19197382287 ps |
| CPU time | 44.1 seconds |
| Started | Oct 09 05:54:39 AM UTC 24 |
| Finished | Oct 09 05:55:24 AM UTC 24 |
| Peak memory | 204012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656550202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1656550202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/81.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.952707353 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 7850226773 ps |
| CPU time | 54.78 seconds |
| Started | Oct 09 05:54:42 AM UTC 24 |
| Finished | Oct 09 05:55:38 AM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=952707353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all_ with_rand_reset.952707353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/82.uart_fifo_reset.507906765 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 65795676902 ps |
| CPU time | 127.27 seconds |
| Started | Oct 09 05:54:45 AM UTC 24 |
| Finished | Oct 09 05:56:55 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507906765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.507906765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/82.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.3943247064 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 5973935819 ps |
| CPU time | 30.97 seconds |
| Started | Oct 09 05:54:49 AM UTC 24 |
| Finished | Oct 09 05:55:21 AM UTC 24 |
| Peak memory | 218460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3943247064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all _with_rand_reset.3943247064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/83.uart_fifo_reset.1121534308 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 18282336082 ps |
| CPU time | 37.97 seconds |
| Started | Oct 09 05:54:50 AM UTC 24 |
| Finished | Oct 09 05:55:30 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121534308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1121534308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/83.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.193059 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 1437211026 ps |
| CPU time | 24.21 seconds |
| Started | Oct 09 05:54:51 AM UTC 24 |
| Finished | Oct 09 05:55:17 AM UTC 24 |
| Peak memory | 218588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=193059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all_wit h_rand_reset.193059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/84.uart_fifo_reset.2281880742 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 8040217117 ps |
| CPU time | 14.9 seconds |
| Started | Oct 09 05:54:53 AM UTC 24 |
| Finished | Oct 09 05:55:09 AM UTC 24 |
| Peak memory | 203804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281880742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2281880742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/84.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.2151776692 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 12223792258 ps |
| CPU time | 83.05 seconds |
| Started | Oct 09 05:54:57 AM UTC 24 |
| Finished | Oct 09 05:56:23 AM UTC 24 |
| Peak memory | 222620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2151776692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all _with_rand_reset.2151776692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/85.uart_fifo_reset.2795695097 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 10584580610 ps |
| CPU time | 23.06 seconds |
| Started | Oct 09 05:54:59 AM UTC 24 |
| Finished | Oct 09 05:55:23 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795695097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2795695097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/85.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.4093311959 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 10006016354 ps |
| CPU time | 34.45 seconds |
| Started | Oct 09 05:54:59 AM UTC 24 |
| Finished | Oct 09 05:55:34 AM UTC 24 |
| Peak memory | 222952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4093311959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all _with_rand_reset.4093311959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/86.uart_fifo_reset.276567722 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 26332741146 ps |
| CPU time | 31.1 seconds |
| Started | Oct 09 05:55:05 AM UTC 24 |
| Finished | Oct 09 05:55:37 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276567722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.276567722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/86.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.930430658 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 1233992725 ps |
| CPU time | 60.81 seconds |
| Started | Oct 09 05:55:06 AM UTC 24 |
| Finished | Oct 09 05:56:08 AM UTC 24 |
| Peak memory | 209548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=930430658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all_ with_rand_reset.930430658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/87.uart_fifo_reset.4056377249 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 135717035527 ps |
| CPU time | 239.17 seconds |
| Started | Oct 09 05:55:09 AM UTC 24 |
| Finished | Oct 09 05:59:12 AM UTC 24 |
| Peak memory | 203996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056377249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4056377249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/87.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.3309213485 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 23733198636 ps |
| CPU time | 77.29 seconds |
| Started | Oct 09 05:55:10 AM UTC 24 |
| Finished | Oct 09 05:56:29 AM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3309213485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all _with_rand_reset.3309213485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/88.uart_fifo_reset.98996848 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 152503682396 ps |
| CPU time | 288.68 seconds |
| Started | Oct 09 05:55:12 AM UTC 24 |
| Finished | Oct 09 06:00:05 AM UTC 24 |
| Peak memory | 209744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98996848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.98996848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/88.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.1094142285 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 3783899270 ps |
| CPU time | 95.78 seconds |
| Started | Oct 09 05:55:12 AM UTC 24 |
| Finished | Oct 09 05:56:50 AM UTC 24 |
| Peak memory | 218828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1094142285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all _with_rand_reset.1094142285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2848905587 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 161777662883 ps |
| CPU time | 24.44 seconds |
| Started | Oct 09 05:55:13 AM UTC 24 |
| Finished | Oct 09 05:55:39 AM UTC 24 |
| Peak memory | 204084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848905587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2848905587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/89.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.1152568025 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 7645432961 ps |
| CPU time | 60.96 seconds |
| Started | Oct 09 05:55:16 AM UTC 24 |
| Finished | Oct 09 05:56:19 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1152568025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all _with_rand_reset.1152568025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_alert_test.416341118 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 14184118 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 05:29:46 AM UTC 24 |
| Finished | Oct 09 05:29:48 AM UTC 24 |
| Peak memory | 203344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416341118 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.416341118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_fifo_full.942460652 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 55028335661 ps |
| CPU time | 45.33 seconds |
| Started | Oct 09 05:29:27 AM UTC 24 |
| Finished | Oct 09 05:30:13 AM UTC 24 |
| Peak memory | 206244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942460652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.942460652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.353827369 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 26402327764 ps |
| CPU time | 44.64 seconds |
| Started | Oct 09 05:29:27 AM UTC 24 |
| Finished | Oct 09 05:30:13 AM UTC 24 |
| Peak memory | 209428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353827369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.353827369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_fifo_reset.1744006664 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 350220776214 ps |
| CPU time | 465.49 seconds |
| Started | Oct 09 05:29:27 AM UTC 24 |
| Finished | Oct 09 05:37:18 AM UTC 24 |
| Peak memory | 209504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744006664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1744006664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_intr.4172491890 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 14387963128 ps |
| CPU time | 55.76 seconds |
| Started | Oct 09 05:29:28 AM UTC 24 |
| Finished | Oct 09 05:30:25 AM UTC 24 |
| Peak memory | 207888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172491890 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4172491890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.2736560008 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 65955323268 ps |
| CPU time | 229.27 seconds |
| Started | Oct 09 05:29:36 AM UTC 24 |
| Finished | Oct 09 05:33:29 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736560008 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2736560008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_loopback.2573697313 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 562402122 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 05:29:33 AM UTC 24 |
| Finished | Oct 09 05:29:36 AM UTC 24 |
| Peak memory | 203280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573697313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2573697313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_loopback/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_noise_filter.1167363906 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 48766174835 ps |
| CPU time | 51.15 seconds |
| Started | Oct 09 05:29:29 AM UTC 24 |
| Finished | Oct 09 05:30:22 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167363906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1167363906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_noise_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_perf.955796429 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 19594905452 ps |
| CPU time | 271.13 seconds |
| Started | Oct 09 05:29:34 AM UTC 24 |
| Finished | Oct 09 05:34:09 AM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955796429 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.955796429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_rx_oversample.703870464 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 7453034778 ps |
| CPU time | 70.78 seconds |
| Started | Oct 09 05:29:28 AM UTC 24 |
| Finished | Oct 09 05:30:40 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703870464 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.703870464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_rx_oversample/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.3562257897 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 124006381789 ps |
| CPU time | 685.45 seconds |
| Started | Oct 09 05:29:29 AM UTC 24 |
| Finished | Oct 09 05:41:02 AM UTC 24 |
| Peak memory | 212656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562257897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3562257897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_rx_parity_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.597678917 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3091856203 ps |
| CPU time | 3.39 seconds |
| Started | Oct 09 05:29:29 AM UTC 24 |
| Finished | Oct 09 05:29:33 AM UTC 24 |
| Peak memory | 203796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597678917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.597678917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_smoke.4072775410 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 629027650 ps |
| CPU time | 5.06 seconds |
| Started | Oct 09 05:29:22 AM UTC 24 |
| Finished | Oct 09 05:29:28 AM UTC 24 |
| Peak memory | 204204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072775410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.uart_smoke.4072775410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3415949263 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 27925462806 ps |
| CPU time | 30.91 seconds |
| Started | Oct 09 05:29:37 AM UTC 24 |
| Finished | Oct 09 05:30:10 AM UTC 24 |
| Peak memory | 226516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3415949263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_ with_rand_reset.3415949263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1247310347 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 7545242628 ps |
| CPU time | 13.5 seconds |
| Started | Oct 09 05:29:30 AM UTC 24 |
| Finished | Oct 09 05:29:45 AM UTC 24 |
| Peak memory | 204008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247310347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1247310347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_tx_ovrd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_tx_rx.1729027615 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 72543749764 ps |
| CPU time | 52.78 seconds |
| Started | Oct 09 05:29:25 AM UTC 24 |
| Finished | Oct 09 05:30:20 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729027615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1729027615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/9.uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/90.uart_fifo_reset.4135571516 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 94953600404 ps |
| CPU time | 196.94 seconds |
| Started | Oct 09 05:55:17 AM UTC 24 |
| Finished | Oct 09 05:58:37 AM UTC 24 |
| Peak memory | 204084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135571516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4135571516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/90.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.4054561893 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 1808192695 ps |
| CPU time | 20.89 seconds |
| Started | Oct 09 05:55:19 AM UTC 24 |
| Finished | Oct 09 05:55:41 AM UTC 24 |
| Peak memory | 218580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4054561893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all _with_rand_reset.4054561893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/91.uart_fifo_reset.790168847 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 48320250248 ps |
| CPU time | 38.04 seconds |
| Started | Oct 09 05:55:23 AM UTC 24 |
| Finished | Oct 09 05:56:02 AM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790168847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.790168847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/91.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.2500395431 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 4672692509 ps |
| CPU time | 62.48 seconds |
| Started | Oct 09 05:55:23 AM UTC 24 |
| Finished | Oct 09 05:56:27 AM UTC 24 |
| Peak memory | 218916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2500395431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all _with_rand_reset.2500395431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/92.uart_fifo_reset.488858747 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 88255150546 ps |
| CPU time | 62.49 seconds |
| Started | Oct 09 05:55:24 AM UTC 24 |
| Finished | Oct 09 05:56:28 AM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488858747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.488858747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/92.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.2220074656 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 8255485199 ps |
| CPU time | 33.53 seconds |
| Started | Oct 09 05:55:25 AM UTC 24 |
| Finished | Oct 09 05:56:00 AM UTC 24 |
| Peak memory | 222620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2220074656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all _with_rand_reset.2220074656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/93.uart_fifo_reset.1685060597 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 123134599518 ps |
| CPU time | 184.91 seconds |
| Started | Oct 09 05:55:26 AM UTC 24 |
| Finished | Oct 09 05:58:34 AM UTC 24 |
| Peak memory | 209508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685060597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1685060597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/93.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.2858125512 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 3856781662 ps |
| CPU time | 25.92 seconds |
| Started | Oct 09 05:55:26 AM UTC 24 |
| Finished | Oct 09 05:55:53 AM UTC 24 |
| Peak memory | 220824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2858125512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all _with_rand_reset.2858125512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/94.uart_fifo_reset.3235926310 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 23084637201 ps |
| CPU time | 19.44 seconds |
| Started | Oct 09 05:55:29 AM UTC 24 |
| Finished | Oct 09 05:55:50 AM UTC 24 |
| Peak memory | 204264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235926310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3235926310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/94.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.509170005 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 4330820945 ps |
| CPU time | 34.42 seconds |
| Started | Oct 09 05:55:30 AM UTC 24 |
| Finished | Oct 09 05:56:06 AM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=509170005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all_ with_rand_reset.509170005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/95.uart_fifo_reset.619242046 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 25732939156 ps |
| CPU time | 45.02 seconds |
| Started | Oct 09 05:55:30 AM UTC 24 |
| Finished | Oct 09 05:56:17 AM UTC 24 |
| Peak memory | 209540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619242046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.619242046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/95.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.1371390430 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 6062414945 ps |
| CPU time | 38.13 seconds |
| Started | Oct 09 05:55:31 AM UTC 24 |
| Finished | Oct 09 05:56:11 AM UTC 24 |
| Peak memory | 220620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1371390430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all _with_rand_reset.1371390430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/96.uart_fifo_reset.4173625889 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 137856645630 ps |
| CPU time | 70.53 seconds |
| Started | Oct 09 05:55:31 AM UTC 24 |
| Finished | Oct 09 05:56:44 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173625889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.4173625889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/96.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.3212904165 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 16262280512 ps |
| CPU time | 41.39 seconds |
| Started | Oct 09 05:55:33 AM UTC 24 |
| Finished | Oct 09 05:56:15 AM UTC 24 |
| Peak memory | 218436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3212904165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all _with_rand_reset.3212904165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/97.uart_fifo_reset.3701746266 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 21240274050 ps |
| CPU time | 21.24 seconds |
| Started | Oct 09 05:55:35 AM UTC 24 |
| Finished | Oct 09 05:55:57 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701746266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3701746266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/97.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2237754780 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 3144222223 ps |
| CPU time | 86.81 seconds |
| Started | Oct 09 05:55:36 AM UTC 24 |
| Finished | Oct 09 05:57:05 AM UTC 24 |
| Peak memory | 218464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2237754780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all _with_rand_reset.2237754780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2118627986 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 89014289885 ps |
| CPU time | 59.1 seconds |
| Started | Oct 09 05:55:36 AM UTC 24 |
| Finished | Oct 09 05:56:36 AM UTC 24 |
| Peak memory | 209560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118627986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2118627986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/98.uart_fifo_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.1068061793 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 2389048819 ps |
| CPU time | 115.96 seconds |
| Started | Oct 09 05:55:37 AM UTC 24 |
| Finished | Oct 09 05:57:35 AM UTC 24 |
| Peak memory | 220816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1068061793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all _with_rand_reset.1068061793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/99.uart_fifo_reset.2004589370 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 101827747712 ps |
| CPU time | 156.2 seconds |
| Started | Oct 09 05:55:38 AM UTC 24 |
| Finished | Oct 09 05:58:17 AM UTC 24 |
| Peak memory | 204072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004589370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2004589370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/99.uart_fifo_reset/latest |
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