| T648 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_smoke.4016594429 |
|
|
Oct 09 05:42:31 AM UTC 24 |
Oct 09 05:42:35 AM UTC 24 |
306757590 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.1297339723 |
|
|
Oct 09 05:41:35 AM UTC 24 |
Oct 09 05:42:35 AM UTC 24 |
3271200707 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_fifo_full.3684522100 |
|
|
Oct 09 05:38:02 AM UTC 24 |
Oct 09 05:42:36 AM UTC 24 |
151028185002 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_perf.629986925 |
|
|
Oct 09 05:29:17 AM UTC 24 |
Oct 09 05:42:37 AM UTC 24 |
24163754733 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_fifo_full.1583918644 |
|
|
Oct 09 05:41:14 AM UTC 24 |
Oct 09 05:42:39 AM UTC 24 |
49094323876 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_fifo_reset.2256762994 |
|
|
Oct 09 05:41:42 AM UTC 24 |
Oct 09 05:42:42 AM UTC 24 |
15734909178 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_rx_oversample.885150891 |
|
|
Oct 09 05:42:38 AM UTC 24 |
Oct 09 05:42:47 AM UTC 24 |
5563185652 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_tx_rx.1959601368 |
|
|
Oct 09 05:42:34 AM UTC 24 |
Oct 09 05:42:48 AM UTC 24 |
18809872700 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.4010786915 |
|
|
Oct 09 05:37:52 AM UTC 24 |
Oct 09 05:42:58 AM UTC 24 |
113010849040 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_noise_filter.3991855764 |
|
|
Oct 09 05:42:43 AM UTC 24 |
Oct 09 05:43:03 AM UTC 24 |
73820298112 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.2640337798 |
|
|
Oct 09 05:42:59 AM UTC 24 |
Oct 09 05:43:03 AM UTC 24 |
1513490607 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_loopback.4152649623 |
|
|
Oct 09 05:43:04 AM UTC 24 |
Oct 09 05:43:07 AM UTC 24 |
103438092 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.1988568592 |
|
|
Oct 09 05:42:20 AM UTC 24 |
Oct 09 05:43:09 AM UTC 24 |
14850197267 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_fifo_full.2314097441 |
|
|
Oct 09 05:41:41 AM UTC 24 |
Oct 09 05:43:11 AM UTC 24 |
49563047731 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.414114816 |
|
|
Oct 09 05:41:28 AM UTC 24 |
Oct 09 05:43:14 AM UTC 24 |
100753170331 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_alert_test.728854178 |
|
|
Oct 09 05:43:15 AM UTC 24 |
Oct 09 05:43:17 AM UTC 24 |
23948790 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_stress_all.158196447 |
|
|
Oct 09 05:39:30 AM UTC 24 |
Oct 09 05:43:47 AM UTC 24 |
315448600803 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_fifo_reset.3867689209 |
|
|
Oct 09 05:39:37 AM UTC 24 |
Oct 09 05:43:21 AM UTC 24 |
84147340596 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_smoke.1874278017 |
|
|
Oct 09 05:43:18 AM UTC 24 |
Oct 09 05:43:22 AM UTC 24 |
484352380 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.4076035475 |
|
|
Oct 09 05:42:02 AM UTC 24 |
Oct 09 05:43:23 AM UTC 24 |
43974774179 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_perf.1347111953 |
|
|
Oct 09 05:42:13 AM UTC 24 |
Oct 09 05:43:25 AM UTC 24 |
7007973244 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_noise_filter.858072831 |
|
|
Oct 09 05:41:57 AM UTC 24 |
Oct 09 05:43:25 AM UTC 24 |
152688028708 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.1101995527 |
|
|
Oct 09 05:42:36 AM UTC 24 |
Oct 09 05:43:25 AM UTC 24 |
48665621414 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_intr.2066002416 |
|
|
Oct 09 05:42:40 AM UTC 24 |
Oct 09 05:43:26 AM UTC 24 |
12271828483 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_fifo_reset.486602971 |
|
|
Oct 09 05:42:36 AM UTC 24 |
Oct 09 05:43:27 AM UTC 24 |
33181879425 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_perf.2455092087 |
|
|
Oct 09 05:34:52 AM UTC 24 |
Oct 09 05:43:27 AM UTC 24 |
12110171622 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.2069538465 |
|
|
Oct 09 05:42:48 AM UTC 24 |
Oct 09 05:43:27 AM UTC 24 |
40450688482 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.109902988 |
|
|
Oct 09 05:41:41 AM UTC 24 |
Oct 09 05:43:27 AM UTC 24 |
129686772129 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_rx_oversample.2316875273 |
|
|
Oct 09 05:43:26 AM UTC 24 |
Oct 09 05:43:29 AM UTC 24 |
2509502709 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.3453317485 |
|
|
Oct 09 05:37:24 AM UTC 24 |
Oct 09 05:43:34 AM UTC 24 |
149307740811 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_tx_rx.596242068 |
|
|
Oct 09 05:43:21 AM UTC 24 |
Oct 09 05:43:37 AM UTC 24 |
141217914599 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_loopback.2505334801 |
|
|
Oct 09 05:43:28 AM UTC 24 |
Oct 09 05:43:46 AM UTC 24 |
5588542577 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_fifo_full.3400831943 |
|
|
Oct 09 05:43:24 AM UTC 24 |
Oct 09 05:43:47 AM UTC 24 |
25610920829 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_fifo_full.1184467927 |
|
|
Oct 09 05:42:36 AM UTC 24 |
Oct 09 05:43:48 AM UTC 24 |
52731102432 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_alert_test.3840566454 |
|
|
Oct 09 05:43:48 AM UTC 24 |
Oct 09 05:43:50 AM UTC 24 |
15121319 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_smoke.4072136895 |
|
|
Oct 09 05:43:48 AM UTC 24 |
Oct 09 05:43:51 AM UTC 24 |
769408638 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_tx_rx.2165768920 |
|
|
Oct 09 05:40:12 AM UTC 24 |
Oct 09 05:43:52 AM UTC 24 |
73435528634 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.3289963079 |
|
|
Oct 09 05:43:38 AM UTC 24 |
Oct 09 05:43:54 AM UTC 24 |
1586123016 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_stress_all.1903488071 |
|
|
Oct 09 05:36:02 AM UTC 24 |
Oct 09 05:43:55 AM UTC 24 |
254040103838 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_noise_filter.2076768744 |
|
|
Oct 09 05:41:24 AM UTC 24 |
Oct 09 05:43:57 AM UTC 24 |
68086595564 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.2856063150 |
|
|
Oct 09 05:43:10 AM UTC 24 |
Oct 09 05:44:01 AM UTC 24 |
12100289119 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.4025595055 |
|
|
Oct 09 05:43:28 AM UTC 24 |
Oct 09 05:44:03 AM UTC 24 |
6809251885 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_intr.2400341308 |
|
|
Oct 09 05:43:26 AM UTC 24 |
Oct 09 05:44:09 AM UTC 24 |
62394117839 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.2514509708 |
|
|
Oct 09 05:44:02 AM UTC 24 |
Oct 09 05:44:09 AM UTC 24 |
3591615103 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_rx_oversample.801164066 |
|
|
Oct 09 05:43:55 AM UTC 24 |
Oct 09 05:44:10 AM UTC 24 |
6766191530 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.1001281108 |
|
|
Oct 09 05:44:10 AM UTC 24 |
Oct 09 05:44:14 AM UTC 24 |
1037541362 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_fifo_full.3650122686 |
|
|
Oct 09 05:39:34 AM UTC 24 |
Oct 09 05:44:15 AM UTC 24 |
167953282626 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.2319415312 |
|
|
Oct 09 05:43:28 AM UTC 24 |
Oct 09 05:44:17 AM UTC 24 |
47929857116 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.4036472776 |
|
|
Oct 09 05:42:14 AM UTC 24 |
Oct 09 05:44:17 AM UTC 24 |
27103365020 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_fifo_reset.1316729532 |
|
|
Oct 09 05:43:53 AM UTC 24 |
Oct 09 05:44:18 AM UTC 24 |
29924759197 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_alert_test.2121783509 |
|
|
Oct 09 05:44:18 AM UTC 24 |
Oct 09 05:44:20 AM UTC 24 |
38710019 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_smoke.139509959 |
|
|
Oct 09 05:44:19 AM UTC 24 |
Oct 09 05:44:22 AM UTC 24 |
664630752 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.2549612681 |
|
|
Oct 09 05:40:20 AM UTC 24 |
Oct 09 05:44:23 AM UTC 24 |
117031401855 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.1177275169 |
|
|
Oct 09 05:42:50 AM UTC 24 |
Oct 09 05:44:24 AM UTC 24 |
202970029937 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_loopback.3611828183 |
|
|
Oct 09 05:44:10 AM UTC 24 |
Oct 09 05:44:27 AM UTC 24 |
9162907529 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_stress_all.4110482040 |
|
|
Oct 09 05:42:23 AM UTC 24 |
Oct 09 05:44:35 AM UTC 24 |
180830255329 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_intr.4015121745 |
|
|
Oct 09 05:41:55 AM UTC 24 |
Oct 09 05:44:36 AM UTC 24 |
190258415625 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.1811759454 |
|
|
Oct 09 05:38:57 AM UTC 24 |
Oct 09 05:44:36 AM UTC 24 |
224623987237 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_fifo_reset.393080376 |
|
|
Oct 09 05:41:17 AM UTC 24 |
Oct 09 05:44:37 AM UTC 24 |
79079444388 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.1561169254 |
|
|
Oct 09 05:43:28 AM UTC 24 |
Oct 09 05:44:39 AM UTC 24 |
35815849271 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_stress_all.1896038034 |
|
|
Oct 09 05:41:04 AM UTC 24 |
Oct 09 05:44:41 AM UTC 24 |
182558884965 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.3505699771 |
|
|
Oct 09 05:44:16 AM UTC 24 |
Oct 09 05:44:41 AM UTC 24 |
6107738286 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_loopback.1437839535 |
|
|
Oct 09 05:44:42 AM UTC 24 |
Oct 09 05:44:46 AM UTC 24 |
168776795 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.79102859 |
|
|
Oct 09 05:44:40 AM UTC 24 |
Oct 09 05:44:46 AM UTC 24 |
1277645947 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.4059094123 |
|
|
Oct 09 05:35:19 AM UTC 24 |
Oct 09 05:44:50 AM UTC 24 |
137663118765 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.2127399199 |
|
|
Oct 09 05:44:04 AM UTC 24 |
Oct 09 05:44:51 AM UTC 24 |
108386246268 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_tx_rx.106489474 |
|
|
Oct 09 05:43:49 AM UTC 24 |
Oct 09 05:44:51 AM UTC 24 |
304456076040 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_tx_rx.4192382592 |
|
|
Oct 09 05:44:22 AM UTC 24 |
Oct 09 05:44:54 AM UTC 24 |
49379626963 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_alert_test.4127423301 |
|
|
Oct 09 05:44:52 AM UTC 24 |
Oct 09 05:44:54 AM UTC 24 |
32030140 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_smoke.3357057813 |
|
|
Oct 09 05:44:52 AM UTC 24 |
Oct 09 05:44:56 AM UTC 24 |
508264585 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_noise_filter.1409189492 |
|
|
Oct 09 05:43:27 AM UTC 24 |
Oct 09 05:44:58 AM UTC 24 |
225553811680 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_perf.3897737172 |
|
|
Oct 09 05:26:50 AM UTC 24 |
Oct 09 05:45:07 AM UTC 24 |
16583450746 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_rx_oversample.2452546470 |
|
|
Oct 09 05:44:28 AM UTC 24 |
Oct 09 05:45:16 AM UTC 24 |
4869692239 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.395525155 |
|
|
Oct 09 05:43:25 AM UTC 24 |
Oct 09 05:45:18 AM UTC 24 |
77863071541 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.2866815145 |
|
|
Oct 09 05:39:08 AM UTC 24 |
Oct 09 05:45:22 AM UTC 24 |
295489197035 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.3932181247 |
|
|
Oct 09 05:44:37 AM UTC 24 |
Oct 09 05:45:22 AM UTC 24 |
41094367211 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_fifo_full.1241233696 |
|
|
Oct 09 05:44:55 AM UTC 24 |
Oct 09 05:45:23 AM UTC 24 |
65219214271 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/25.uart_stress_all.329301949 |
|
|
Oct 09 05:37:54 AM UTC 24 |
Oct 09 05:45:23 AM UTC 24 |
182181263022 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/27.uart_stress_all.1179387602 |
|
|
Oct 09 05:38:59 AM UTC 24 |
Oct 09 05:45:25 AM UTC 24 |
140061824454 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.991959729 |
|
|
Oct 09 05:42:02 AM UTC 24 |
Oct 09 05:45:27 AM UTC 24 |
139560492539 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_rx_oversample.2171825301 |
|
|
Oct 09 05:45:08 AM UTC 24 |
Oct 09 05:45:29 AM UTC 24 |
3371296333 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.2625823184 |
|
|
Oct 09 05:45:23 AM UTC 24 |
Oct 09 05:45:32 AM UTC 24 |
1835923921 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_intr.723504816 |
|
|
Oct 09 05:45:17 AM UTC 24 |
Oct 09 05:45:32 AM UTC 24 |
15346677137 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_loopback.445834939 |
|
|
Oct 09 05:45:24 AM UTC 24 |
Oct 09 05:45:33 AM UTC 24 |
7483014021 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_alert_test.1007976116 |
|
|
Oct 09 05:45:32 AM UTC 24 |
Oct 09 05:45:35 AM UTC 24 |
23158568 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_perf.2721772562 |
|
|
Oct 09 05:37:24 AM UTC 24 |
Oct 09 05:45:35 AM UTC 24 |
6938591846 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_fifo_full.1909309771 |
|
|
Oct 09 05:43:51 AM UTC 24 |
Oct 09 05:45:35 AM UTC 24 |
109147623245 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_smoke.4241504262 |
|
|
Oct 09 05:45:34 AM UTC 24 |
Oct 09 05:45:37 AM UTC 24 |
692308606 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.3524175908 |
|
|
Oct 09 05:34:10 AM UTC 24 |
Oct 09 05:45:37 AM UTC 24 |
64442770638 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_rx_oversample.1563461329 |
|
|
Oct 09 05:45:38 AM UTC 24 |
Oct 09 05:45:43 AM UTC 24 |
2906359268 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_intr.3490810221 |
|
|
Oct 09 05:43:55 AM UTC 24 |
Oct 09 05:45:45 AM UTC 24 |
31179412357 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.2767909355 |
|
|
Oct 09 05:35:58 AM UTC 24 |
Oct 09 05:45:47 AM UTC 24 |
82949329907 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.2018079094 |
|
|
Oct 09 05:44:57 AM UTC 24 |
Oct 09 05:45:51 AM UTC 24 |
62916190632 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.3409154207 |
|
|
Oct 09 05:44:47 AM UTC 24 |
Oct 09 05:45:58 AM UTC 24 |
11051136180 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.488831924 |
|
|
Oct 09 05:45:24 AM UTC 24 |
Oct 09 05:46:01 AM UTC 24 |
6825803395 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.1613000439 |
|
|
Oct 09 05:45:23 AM UTC 24 |
Oct 09 05:46:02 AM UTC 24 |
65446091308 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.3258541700 |
|
|
Oct 09 05:45:59 AM UTC 24 |
Oct 09 05:46:03 AM UTC 24 |
582309791 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_loopback.720326592 |
|
|
Oct 09 05:46:02 AM UTC 24 |
Oct 09 05:46:11 AM UTC 24 |
6909352055 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.348077400 |
|
|
Oct 09 05:44:38 AM UTC 24 |
Oct 09 05:46:11 AM UTC 24 |
50241196791 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_fifo_full.3270514963 |
|
|
Oct 09 05:45:37 AM UTC 24 |
Oct 09 05:46:11 AM UTC 24 |
46213160455 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_noise_filter.4036217142 |
|
|
Oct 09 05:45:20 AM UTC 24 |
Oct 09 05:46:13 AM UTC 24 |
45113036944 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.3011635027 |
|
|
Oct 09 05:45:29 AM UTC 24 |
Oct 09 05:46:14 AM UTC 24 |
4291734735 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_alert_test.27376196 |
|
|
Oct 09 05:46:12 AM UTC 24 |
Oct 09 05:46:14 AM UTC 24 |
22475957 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.1089723212 |
|
|
Oct 09 05:45:37 AM UTC 24 |
Oct 09 05:46:14 AM UTC 24 |
10671320672 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_tx_rx.3054973711 |
|
|
Oct 09 05:44:54 AM UTC 24 |
Oct 09 05:46:15 AM UTC 24 |
31583192374 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_smoke.1530546272 |
|
|
Oct 09 05:46:13 AM UTC 24 |
Oct 09 05:46:18 AM UTC 24 |
945572710 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_intr.2668420559 |
|
|
Oct 09 05:44:36 AM UTC 24 |
Oct 09 05:46:19 AM UTC 24 |
248397720301 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/33.uart_stress_all.3595086242 |
|
|
Oct 09 05:43:12 AM UTC 24 |
Oct 09 05:46:19 AM UTC 24 |
180874346679 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/37.uart_fifo_reset.1536022697 |
|
|
Oct 09 05:44:59 AM UTC 24 |
Oct 09 05:46:25 AM UTC 24 |
36414455077 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_fifo_reset.3984790651 |
|
|
Oct 09 05:45:38 AM UTC 24 |
Oct 09 05:46:29 AM UTC 24 |
15099652508 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.2442611584 |
|
|
Oct 09 05:40:37 AM UTC 24 |
Oct 09 05:46:31 AM UTC 24 |
167524052072 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.3321242870 |
|
|
Oct 09 05:46:26 AM UTC 24 |
Oct 09 05:46:33 AM UTC 24 |
1554687581 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_tx_rx.1870469467 |
|
|
Oct 09 05:45:36 AM UTC 24 |
Oct 09 05:46:35 AM UTC 24 |
120799702086 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_fifo_full.3245352966 |
|
|
Oct 09 05:44:24 AM UTC 24 |
Oct 09 05:46:35 AM UTC 24 |
52350963566 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_fifo_reset.2561544606 |
|
|
Oct 09 05:43:26 AM UTC 24 |
Oct 09 05:46:37 AM UTC 24 |
85466572325 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_fifo_reset.167158965 |
|
|
Oct 09 05:44:25 AM UTC 24 |
Oct 09 05:46:40 AM UTC 24 |
200737149984 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1353924179 |
|
|
Oct 09 05:46:32 AM UTC 24 |
Oct 09 05:46:41 AM UTC 24 |
1449309935 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.683285687 |
|
|
Oct 09 05:46:15 AM UTC 24 |
Oct 09 05:46:42 AM UTC 24 |
80183381570 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_alert_test.4209971670 |
|
|
Oct 09 05:46:42 AM UTC 24 |
Oct 09 05:46:44 AM UTC 24 |
99965803 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_smoke.405903485 |
|
|
Oct 09 05:46:43 AM UTC 24 |
Oct 09 05:46:45 AM UTC 24 |
124547127 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_loopback.1870441767 |
|
|
Oct 09 05:46:33 AM UTC 24 |
Oct 09 05:46:50 AM UTC 24 |
5137263935 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.3636194539 |
|
|
Oct 09 05:44:25 AM UTC 24 |
Oct 09 05:46:54 AM UTC 24 |
129932328593 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.2260433780 |
|
|
Oct 09 05:46:12 AM UTC 24 |
Oct 09 05:47:00 AM UTC 24 |
15934275683 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_fifo_full.3279319486 |
|
|
Oct 09 05:46:15 AM UTC 24 |
Oct 09 05:47:07 AM UTC 24 |
123918396013 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.2349812598 |
|
|
Oct 09 05:45:52 AM UTC 24 |
Oct 09 05:47:08 AM UTC 24 |
21915289674 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_noise_filter.3086882751 |
|
|
Oct 09 05:46:21 AM UTC 24 |
Oct 09 05:47:10 AM UTC 24 |
24263430832 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_tx_rx.3045272737 |
|
|
Oct 09 05:46:45 AM UTC 24 |
Oct 09 05:47:10 AM UTC 24 |
22196136854 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_intr.1753549226 |
|
|
Oct 09 05:45:44 AM UTC 24 |
Oct 09 05:47:12 AM UTC 24 |
54255213001 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_noise_filter.2694873098 |
|
|
Oct 09 05:44:37 AM UTC 24 |
Oct 09 05:47:12 AM UTC 24 |
113388446323 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.2268749537 |
|
|
Oct 09 05:44:15 AM UTC 24 |
Oct 09 05:47:15 AM UTC 24 |
185017325463 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_loopback.2863952955 |
|
|
Oct 09 05:47:14 AM UTC 24 |
Oct 09 05:47:18 AM UTC 24 |
2667641544 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.3868245346 |
|
|
Oct 09 05:40:06 AM UTC 24 |
Oct 09 05:47:19 AM UTC 24 |
162804928959 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_fifo_reset.1928623255 |
|
|
Oct 09 05:46:55 AM UTC 24 |
Oct 09 05:47:21 AM UTC 24 |
5523980879 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_noise_filter.3617545514 |
|
|
Oct 09 05:43:58 AM UTC 24 |
Oct 09 05:47:21 AM UTC 24 |
211891095037 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_tx_rx.3117797841 |
|
|
Oct 09 05:46:14 AM UTC 24 |
Oct 09 05:47:21 AM UTC 24 |
36156892811 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_rx_oversample.1084138854 |
|
|
Oct 09 05:46:19 AM UTC 24 |
Oct 09 05:47:22 AM UTC 24 |
5903282731 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_alert_test.428901656 |
|
|
Oct 09 05:47:21 AM UTC 24 |
Oct 09 05:47:23 AM UTC 24 |
37194717 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.2745758926 |
|
|
Oct 09 05:47:10 AM UTC 24 |
Oct 09 05:47:24 AM UTC 24 |
90330099291 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_smoke.1921928327 |
|
|
Oct 09 05:47:22 AM UTC 24 |
Oct 09 05:47:25 AM UTC 24 |
948462667 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.3588513264 |
|
|
Oct 09 05:47:14 AM UTC 24 |
Oct 09 05:47:27 AM UTC 24 |
7891282569 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.2057893623 |
|
|
Oct 09 05:27:37 AM UTC 24 |
Oct 09 05:47:28 AM UTC 24 |
208797987667 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_rx_oversample.808618005 |
|
|
Oct 09 05:47:00 AM UTC 24 |
Oct 09 05:47:30 AM UTC 24 |
5150340738 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_fifo_reset.3098430494 |
|
|
Oct 09 05:46:16 AM UTC 24 |
Oct 09 05:47:31 AM UTC 24 |
153169693059 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_rx_oversample.308338756 |
|
|
Oct 09 05:47:28 AM UTC 24 |
Oct 09 05:47:32 AM UTC 24 |
1617013921 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_intr.2771205648 |
|
|
Oct 09 05:47:08 AM UTC 24 |
Oct 09 05:47:34 AM UTC 24 |
7062730061 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.1785958163 |
|
|
Oct 09 05:47:32 AM UTC 24 |
Oct 09 05:47:37 AM UTC 24 |
3754654720 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_tx_rx.3706084562 |
|
|
Oct 09 05:47:23 AM UTC 24 |
Oct 09 05:47:37 AM UTC 24 |
20019980159 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_stress_all.1996605834 |
|
|
Oct 09 05:27:17 AM UTC 24 |
Oct 09 05:47:38 AM UTC 24 |
304048067126 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.2522633853 |
|
|
Oct 09 05:47:35 AM UTC 24 |
Oct 09 05:47:39 AM UTC 24 |
2150600072 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.2647584068 |
|
|
Oct 09 05:44:47 AM UTC 24 |
Oct 09 05:47:39 AM UTC 24 |
91084861766 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.1066274234 |
|
|
Oct 09 05:30:36 AM UTC 24 |
Oct 09 05:47:43 AM UTC 24 |
152041087501 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_loopback.1094826316 |
|
|
Oct 09 05:47:38 AM UTC 24 |
Oct 09 05:47:43 AM UTC 24 |
2447282959 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.1684840455 |
|
|
Oct 09 05:43:52 AM UTC 24 |
Oct 09 05:47:43 AM UTC 24 |
136749220857 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_alert_test.946020654 |
|
|
Oct 09 05:47:44 AM UTC 24 |
Oct 09 05:47:45 AM UTC 24 |
42058251 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_fifo_full.1017851625 |
|
|
Oct 09 05:46:46 AM UTC 24 |
Oct 09 05:47:51 AM UTC 24 |
67220954540 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.424307071 |
|
|
Oct 09 05:47:39 AM UTC 24 |
Oct 09 05:47:51 AM UTC 24 |
940794141 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/29.uart_perf.1139630451 |
|
|
Oct 09 05:40:05 AM UTC 24 |
Oct 09 05:47:53 AM UTC 24 |
26094582083 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/31.uart_perf.583796236 |
|
|
Oct 09 05:41:31 AM UTC 24 |
Oct 09 05:47:55 AM UTC 24 |
14615672314 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.2678069660 |
|
|
Oct 09 05:26:52 AM UTC 24 |
Oct 09 05:47:57 AM UTC 24 |
138675846507 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.1466084971 |
|
|
Oct 09 05:45:47 AM UTC 24 |
Oct 09 05:48:02 AM UTC 24 |
51623740171 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_tx_rx.4052614758 |
|
|
Oct 09 05:47:45 AM UTC 24 |
Oct 09 05:48:03 AM UTC 24 |
22172235359 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.3968575876 |
|
|
Oct 09 05:46:38 AM UTC 24 |
Oct 09 05:48:03 AM UTC 24 |
10626286266 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_noise_filter.4077815719 |
|
|
Oct 09 05:47:09 AM UTC 24 |
Oct 09 05:48:06 AM UTC 24 |
46177986839 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_fifo_reset.26301410 |
|
|
Oct 09 05:47:26 AM UTC 24 |
Oct 09 05:48:07 AM UTC 24 |
45720875202 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_rx_oversample.3832873555 |
|
|
Oct 09 05:47:54 AM UTC 24 |
Oct 09 05:48:07 AM UTC 24 |
5264236554 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.2267529749 |
|
|
Oct 09 05:48:03 AM UTC 24 |
Oct 09 05:48:08 AM UTC 24 |
3045021544 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.4056278642 |
|
|
Oct 09 05:48:04 AM UTC 24 |
Oct 09 05:48:09 AM UTC 24 |
1250615192 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_intr.2397550656 |
|
|
Oct 09 05:47:56 AM UTC 24 |
Oct 09 05:48:11 AM UTC 24 |
99449455197 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_alert_test.691261257 |
|
|
Oct 09 05:48:11 AM UTC 24 |
Oct 09 05:48:13 AM UTC 24 |
14796409 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_stress_all.3162418907 |
|
|
Oct 09 05:33:09 AM UTC 24 |
Oct 09 05:48:13 AM UTC 24 |
209701842490 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_loopback.430172947 |
|
|
Oct 09 05:48:07 AM UTC 24 |
Oct 09 05:48:16 AM UTC 24 |
2197735047 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_smoke.2179162640 |
|
|
Oct 09 05:48:14 AM UTC 24 |
Oct 09 05:48:18 AM UTC 24 |
829377541 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.2938254906 |
|
|
Oct 09 05:47:52 AM UTC 24 |
Oct 09 05:48:19 AM UTC 24 |
46691626554 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_intr.4173968644 |
|
|
Oct 09 05:47:29 AM UTC 24 |
Oct 09 05:48:21 AM UTC 24 |
29490612871 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_noise_filter.4022411325 |
|
|
Oct 09 05:47:31 AM UTC 24 |
Oct 09 05:48:21 AM UTC 24 |
41175815760 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_fifo_full.1609695135 |
|
|
Oct 09 05:47:23 AM UTC 24 |
Oct 09 05:48:26 AM UTC 24 |
35509642708 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_fifo_reset.1943236971 |
|
|
Oct 09 05:47:52 AM UTC 24 |
Oct 09 05:48:28 AM UTC 24 |
94889412788 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_smoke.28743090 |
|
|
Oct 09 05:47:44 AM UTC 24 |
Oct 09 05:48:29 AM UTC 24 |
11071771756 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.587770487 |
|
|
Oct 09 05:47:20 AM UTC 24 |
Oct 09 05:48:32 AM UTC 24 |
7857473801 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.1978719847 |
|
|
Oct 09 05:48:33 AM UTC 24 |
Oct 09 05:48:40 AM UTC 24 |
1065564783 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.2219053688 |
|
|
Oct 09 05:46:30 AM UTC 24 |
Oct 09 05:48:41 AM UTC 24 |
186396592056 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.3362788995 |
|
|
Oct 09 05:43:34 AM UTC 24 |
Oct 09 05:48:43 AM UTC 24 |
163552230015 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_fifo_reset.2408525287 |
|
|
Oct 09 05:48:20 AM UTC 24 |
Oct 09 05:48:47 AM UTC 24 |
41632548366 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.1802098196 |
|
|
Oct 09 05:48:29 AM UTC 24 |
Oct 09 05:48:47 AM UTC 24 |
33486472014 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/26.uart_perf.739064832 |
|
|
Oct 09 05:38:23 AM UTC 24 |
Oct 09 05:48:48 AM UTC 24 |
18996897846 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_alert_test.2164326808 |
|
|
Oct 09 05:48:50 AM UTC 24 |
Oct 09 05:48:52 AM UTC 24 |
11714778 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.2360287893 |
|
|
Oct 09 05:47:33 AM UTC 24 |
Oct 09 05:48:53 AM UTC 24 |
109421994273 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_smoke.397187567 |
|
|
Oct 09 05:48:53 AM UTC 24 |
Oct 09 05:48:56 AM UTC 24 |
267859496 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/35.uart_stress_all.54032120 |
|
|
Oct 09 05:44:17 AM UTC 24 |
Oct 09 05:48:58 AM UTC 24 |
1186332825493 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.824693936 |
|
|
Oct 09 05:47:10 AM UTC 24 |
Oct 09 05:48:58 AM UTC 24 |
63764418589 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_stress_all.3760220855 |
|
|
Oct 09 05:43:47 AM UTC 24 |
Oct 09 05:48:59 AM UTC 24 |
398016033715 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_loopback.161152127 |
|
|
Oct 09 05:48:40 AM UTC 24 |
Oct 09 05:49:02 AM UTC 24 |
5645578492 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_perf.911975980 |
|
|
Oct 09 05:46:03 AM UTC 24 |
Oct 09 05:49:06 AM UTC 24 |
11540848858 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_tx_rx.502075450 |
|
|
Oct 09 05:48:14 AM UTC 24 |
Oct 09 05:49:06 AM UTC 24 |
26290927284 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/38.uart_noise_filter.1856568896 |
|
|
Oct 09 05:45:46 AM UTC 24 |
Oct 09 05:49:08 AM UTC 24 |
185699800031 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_rx_oversample.1099071593 |
|
|
Oct 09 05:48:22 AM UTC 24 |
Oct 09 05:49:09 AM UTC 24 |
4398416080 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_rx_oversample.1885511428 |
|
|
Oct 09 05:49:00 AM UTC 24 |
Oct 09 05:49:09 AM UTC 24 |
2994716208 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.2328808008 |
|
|
Oct 09 05:49:06 AM UTC 24 |
Oct 09 05:49:09 AM UTC 24 |
490109280 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/34.uart_perf.3835415710 |
|
|
Oct 09 05:43:30 AM UTC 24 |
Oct 09 05:49:12 AM UTC 24 |
13517226027 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/36.uart_perf.4179406993 |
|
|
Oct 09 05:44:43 AM UTC 24 |
Oct 09 05:49:15 AM UTC 24 |
10616485859 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_fifo_full.3629186850 |
|
|
Oct 09 05:48:57 AM UTC 24 |
Oct 09 05:49:17 AM UTC 24 |
61955481503 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_intr.1944333043 |
|
|
Oct 09 05:49:03 AM UTC 24 |
Oct 09 05:49:18 AM UTC 24 |
20157225208 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_intr.1776815480 |
|
|
Oct 09 05:48:23 AM UTC 24 |
Oct 09 05:49:20 AM UTC 24 |
27886251249 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_loopback.2567682433 |
|
|
Oct 09 05:49:10 AM UTC 24 |
Oct 09 05:49:20 AM UTC 24 |
9079146237 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_alert_test.3552180126 |
|
|
Oct 09 05:49:19 AM UTC 24 |
Oct 09 05:49:21 AM UTC 24 |
14204858 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_fifo_reset.671115578 |
|
|
Oct 09 05:48:59 AM UTC 24 |
Oct 09 05:49:22 AM UTC 24 |
26111018330 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.1012377131 |
|
|
Oct 09 05:49:10 AM UTC 24 |
Oct 09 05:49:28 AM UTC 24 |
7732640497 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.1540738375 |
|
|
Oct 09 05:47:24 AM UTC 24 |
Oct 09 05:49:32 AM UTC 24 |
114573547554 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.3322651316 |
|
|
Oct 09 05:49:09 AM UTC 24 |
Oct 09 05:49:32 AM UTC 24 |
10671080591 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_fifo_full.1360831380 |
|
|
Oct 09 05:47:46 AM UTC 24 |
Oct 09 05:49:33 AM UTC 24 |
95960984074 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.58545624 |
|
|
Oct 09 05:48:30 AM UTC 24 |
Oct 09 05:49:33 AM UTC 24 |
19630245498 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.2320417514 |
|
|
Oct 09 05:48:04 AM UTC 24 |
Oct 09 05:49:38 AM UTC 24 |
82281460278 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.1887527980 |
|
|
Oct 09 05:48:09 AM UTC 24 |
Oct 09 05:49:39 AM UTC 24 |
13303776137 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.662457878 |
|
|
Oct 09 05:49:34 AM UTC 24 |
Oct 09 05:49:40 AM UTC 24 |
3410578814 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.4152269439 |
|
|
Oct 09 05:46:51 AM UTC 24 |
Oct 09 05:49:46 AM UTC 24 |
81767603915 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.2361193999 |
|
|
Oct 09 05:49:40 AM UTC 24 |
Oct 09 05:49:47 AM UTC 24 |
922942196 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_noise_filter.2744994599 |
|
|
Oct 09 05:49:34 AM UTC 24 |
Oct 09 05:49:53 AM UTC 24 |
6963970219 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_smoke.3752059099 |
|
|
Oct 09 05:49:20 AM UTC 24 |
Oct 09 05:49:54 AM UTC 24 |
5996449088 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_loopback.4004637942 |
|
|
Oct 09 05:49:40 AM UTC 24 |
Oct 09 05:49:55 AM UTC 24 |
8053226478 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_alert_test.2180638071 |
|
|
Oct 09 05:49:57 AM UTC 24 |
Oct 09 05:49:59 AM UTC 24 |
52506985 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.2508333682 |
|
|
Oct 09 05:48:48 AM UTC 24 |
Oct 09 05:49:59 AM UTC 24 |
8239815757 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_perf.3463896015 |
|
|
Oct 09 05:35:58 AM UTC 24 |
Oct 09 05:50:02 AM UTC 24 |
13386853235 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_smoke.3593696840 |
|
|
Oct 09 05:50:00 AM UTC 24 |
Oct 09 05:50:03 AM UTC 24 |
679310140 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_fifo_full.3572107364 |
|
|
Oct 09 05:48:16 AM UTC 24 |
Oct 09 05:50:07 AM UTC 24 |
71442091320 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_perf.990175808 |
|
|
Oct 09 05:46:35 AM UTC 24 |
Oct 09 05:50:13 AM UTC 24 |
7175722469 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_tx_rx.3291502397 |
|
|
Oct 09 05:48:54 AM UTC 24 |
Oct 09 05:50:16 AM UTC 24 |
50148069773 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/39.uart_stress_all.568151099 |
|
|
Oct 09 05:46:40 AM UTC 24 |
Oct 09 05:50:22 AM UTC 24 |
416727066474 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.1248277255 |
|
|
Oct 09 05:48:58 AM UTC 24 |
Oct 09 05:50:23 AM UTC 24 |
30713394121 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_tx_rx.739320484 |
|
|
Oct 09 05:49:21 AM UTC 24 |
Oct 09 05:50:23 AM UTC 24 |
25800690187 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_noise_filter.362885389 |
|
|
Oct 09 05:48:27 AM UTC 24 |
Oct 09 05:50:24 AM UTC 24 |
46867328725 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_intr.3160408043 |
|
|
Oct 09 05:49:33 AM UTC 24 |
Oct 09 05:50:28 AM UTC 24 |
46468280792 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.2294631237 |
|
|
Oct 09 05:49:55 AM UTC 24 |
Oct 09 05:50:28 AM UTC 24 |
7106208586 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_perf.2099017949 |
|
|
Oct 09 05:48:08 AM UTC 24 |
Oct 09 05:50:29 AM UTC 24 |
10918438979 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.3199229514 |
|
|
Oct 09 05:50:25 AM UTC 24 |
Oct 09 05:50:30 AM UTC 24 |
783479575 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.2784263432 |
|
|
Oct 09 05:50:04 AM UTC 24 |
Oct 09 05:50:30 AM UTC 24 |
202863321747 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_fifo_full.3577665833 |
|
|
Oct 09 05:49:22 AM UTC 24 |
Oct 09 05:50:31 AM UTC 24 |
76583529138 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.892404871 |
|
|
Oct 09 05:49:23 AM UTC 24 |
Oct 09 05:50:32 AM UTC 24 |
65738183255 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_tx_rx.1092295567 |
|
|
Oct 09 05:50:00 AM UTC 24 |
Oct 09 05:50:33 AM UTC 24 |
8076380554 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_alert_test.802368288 |
|
|
Oct 09 05:50:31 AM UTC 24 |
Oct 09 05:50:33 AM UTC 24 |
36868482 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_noise_filter.3746691336 |
|
|
Oct 09 05:47:58 AM UTC 24 |
Oct 09 05:50:34 AM UTC 24 |
62567311463 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_perf.1232248880 |
|
|
Oct 09 05:48:42 AM UTC 24 |
Oct 09 05:50:36 AM UTC 24 |
3357586073 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_smoke.4167311728 |
|
|
Oct 09 05:50:32 AM UTC 24 |
Oct 09 05:50:37 AM UTC 24 |
428810112 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_rx_oversample.1584932527 |
|
|
Oct 09 05:50:14 AM UTC 24 |
Oct 09 05:50:41 AM UTC 24 |
4420702429 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_loopback.3621028525 |
|
|
Oct 09 05:50:29 AM UTC 24 |
Oct 09 05:50:42 AM UTC 24 |
9613847329 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.2219224911 |
|
|
Oct 09 05:50:25 AM UTC 24 |
Oct 09 05:50:44 AM UTC 24 |
6947259577 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.3510887964 |
|
|
Oct 09 05:48:44 AM UTC 24 |
Oct 09 05:50:47 AM UTC 24 |
192131767306 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_rx_oversample.1112246310 |
|
|
Oct 09 05:50:38 AM UTC 24 |
Oct 09 05:50:48 AM UTC 24 |
6645314216 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/45.uart_rx_oversample.1644519455 |
|
|
Oct 09 05:49:33 AM UTC 24 |
Oct 09 05:50:49 AM UTC 24 |
6233599442 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.1771723046 |
|
|
Oct 09 05:50:45 AM UTC 24 |
Oct 09 05:50:50 AM UTC 24 |
626236174 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.4259037462 |
|
|
Oct 09 05:50:25 AM UTC 24 |
Oct 09 05:50:52 AM UTC 24 |
50214658254 ps |