UART Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	34.630s	6.300ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.880s	47.220us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.960s	15.568us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.170s	116.260us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.150s	48.976us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.520s	41.446us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.960s	15.568us	20	20	100.00
		uart_csr_aliasing	1.150s	48.976us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.185m	90.178ms	50	50	100.00
V2	parity	uart_smoke	34.630s	6.300ms	50	50	100.00
		uart_tx_rx	5.185m	90.178ms	50	50	100.00
V2	parity_error	uart_intr	6.465m	228.556ms	49	50	98.00
		uart_rx_parity_err	6.361m	188.096ms	50	50	100.00
V2	watermark	uart_tx_rx	5.185m	90.178ms	50	50	100.00
		uart_intr	6.465m	228.556ms	49	50	98.00
V2	fifo_full	uart_fifo_full	8.904m	259.401ms	49	50	98.00
V2	fifo_overflow	uart_fifo_overflow	6.777m	159.336ms	49	50	98.00
V2	fifo_reset	uart_fifo_reset	8.904m	282.730ms	300	300	100.00
V2	rx_frame_err	uart_intr	6.465m	228.556ms	49	50	98.00
V2	rx_break_err	uart_intr	6.465m	228.556ms	49	50	98.00
V2	rx_timeout	uart_intr	6.465m	228.556ms	49	50	98.00
V2	perf	uart_perf	28.829m	29.582ms	50	50	100.00
V2	sys_loopback	uart_loopback	40.470s	10.458ms	50	50	100.00
V2	line_loopback	uart_loopback	40.470s	10.458ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.176m	89.212ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.909m	69.801ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	45.490s	11.933ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.373m	7.577ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	22.902m	198.364ms	50	50	100.00
V2	stress_all	uart_stress_all	29.507m	184.132ms	49	50	98.00
V2	alert_test	uart_alert_test	0.890s	13.231us	50	50	100.00
V2	intr_test	uart_intr_test	0.900s	14.708us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.090s	113.289us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.090s	113.289us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.880s	47.220us	5	5	100.00
		uart_csr_rw	0.960s	15.568us	20	20	100.00
		uart_csr_aliasing	1.150s	48.976us	5	5	100.00
		uart_same_csr_outstanding	1.130s	102.472us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.880s	47.220us	5	5	100.00
		uart_csr_rw	0.960s	15.568us	20	20	100.00
		uart_csr_aliasing	1.150s	48.976us	5	5	100.00
		uart_same_csr_outstanding	1.130s	102.472us	20	20	100.00
V2		TOTAL			1085	1090	99.54
V2S	tl_intg_err	uart_sec_cm	1.340s	64.955us	5	5	100.00
		uart_tl_intg_err	2.070s	184.799us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.070s	184.799us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.373m	4.469ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1314	1320	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	13	72.22
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.08	97.65	100.00	--	98.35	100.00	99.62

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 4 failures:

Test uart_stress_all has 1 failures.

1.uart_stress_all.30212303352084919959396440636793716206129814168579078373625479057899996333474
Line 84, in log /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/1.uart_stress_all/latest/run.log

  UVM_ERROR @ 52017247292 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 52102687292 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 53993567292 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark

Test uart_fifo_overflow has 1 failures.

6.uart_fifo_overflow.22156975400407847785182082429253630261065293913405896004287874211804649461325
Line 61, in log /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/6.uart_fifo_overflow/latest/run.log

  UVM_ERROR @   2085015 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 1244025015 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/9
  UVM_INFO @ 1567265015 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/9
  UVM_INFO @ 10983305015 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/9
  UVM_INFO @ 32649605015 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/9

Test uart_intr has 1 failures.

31.uart_intr.82304180803255852071668675201059502081422557469561090712887957609987975400140
Line 71, in log /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/31.uart_intr/latest/run.log

  UVM_ERROR @ 6027724765 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 6119044765 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 7494204765 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark

Test uart_fifo_full has 1 failures.

44.uart_fifo_full.106079539508994172435729039464543294942374204802624518971926578972784316885336
Line 68, in log /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/44.uart_fifo_full/latest/run.log

  UVM_ERROR @ 29146079442 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 29146079442 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 31028848022 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 8/9
  UVM_INFO @ 31512300992 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 9/9
  UVM_INFO @ 37443709381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 4.uart_noise_filter.46922784524410717483851298335818168773358448997511588895338897195644155704987
    Line 75, in log /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/4.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:867) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

5.uart_stress_all_with_rand_reset.86914786878111017872662343084295163685824445403062706234163034856078992903121
Line 114, in log /workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1634397281 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1634404156 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1634404156 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 1634407485 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1