UART Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	52.120s	5.546ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.920s	29.879us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.930s	13.767us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.660s	867.317us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.200s	32.845us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.460s	71.412us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.930s	13.767us	20	20	100.00
		uart_csr_aliasing	1.200s	32.845us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.123m	94.863ms	50	50	100.00
V2	parity	uart_smoke	52.120s	5.546ms	50	50	100.00
		uart_tx_rx	3.123m	94.863ms	50	50	100.00
V2	parity_error	uart_intr	6.662m	194.273ms	48	50	96.00
		uart_rx_parity_err	5.221m	319.053ms	50	50	100.00
V2	watermark	uart_tx_rx	3.123m	94.863ms	50	50	100.00
		uart_intr	6.662m	194.273ms	48	50	96.00
V2	fifo_full	uart_fifo_full	14.535m	180.815ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.732m	180.290ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	14.774m	138.109ms	299	300	99.67
V2	rx_frame_err	uart_intr	6.662m	194.273ms	48	50	96.00
V2	rx_break_err	uart_intr	6.662m	194.273ms	48	50	96.00
V2	rx_timeout	uart_intr	6.662m	194.273ms	48	50	96.00
V2	perf	uart_perf	27.447m	26.534ms	50	50	100.00
V2	sys_loopback	uart_loopback	36.690s	15.936ms	50	50	100.00
V2	line_loopback	uart_loopback	36.690s	15.936ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.532m	128.931ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.431m	39.017ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	40.090s	6.340ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.115m	4.726ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	25.825m	173.524ms	50	50	100.00
V2	stress_all	uart_stress_all	29.384m	385.860ms	50	50	100.00
V2	alert_test	uart_alert_test	0.890s	15.974us	50	50	100.00
V2	intr_test	uart_intr_test	0.890s	15.689us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.300s	363.056us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.300s	363.056us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.920s	29.879us	5	5	100.00
		uart_csr_rw	0.930s	13.767us	20	20	100.00
		uart_csr_aliasing	1.200s	32.845us	5	5	100.00
		uart_same_csr_outstanding	1.130s	31.021us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.920s	29.879us	5	5	100.00
		uart_csr_rw	0.930s	13.767us	20	20	100.00
		uart_csr_aliasing	1.200s	32.845us	5	5	100.00
		uart_same_csr_outstanding	1.130s	31.021us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	1.360s	61.577us	5	5	100.00
		uart_tl_intg_err	1.950s	79.674us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.950s	79.674us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.710m	4.396ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1316	1320	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.08	97.65	100.00	--	98.35	100.00	99.46

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

Test uart_intr has 2 failures.

5.uart_intr.47426222834177175251167876975716947499788276693566252735553782679642955578443
Line 105, in log /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/5.uart_intr/latest/run.log

  UVM_ERROR @ 29569931726 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 29569931726 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 29648024437 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 29804350890 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

44.uart_intr.60466012820405539688776897809937624294173228354472684630253582933208631284339
Line 94, in log /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/44.uart_intr/latest/run.log

  UVM_ERROR @ 68912930929 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 69968070929 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 72052320929 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr

Test uart_fifo_reset has 1 failures.

279.uart_fifo_reset.101996012416703336055244216960682741615528469851168949283764049828557169451360
Line 61, in log /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/279.uart_fifo_reset/latest/run.log

  UVM_ERROR @   1784771 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @   1784771 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 3301408390 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/8
  UVM_INFO @ 6389169203 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/8
  UVM_INFO @ 6508878494 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/8

UVM_ERROR (cip_base_vseq.sv:867) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

31.uart_stress_all_with_rand_reset.80646775899503369551274098403133516123979336863224462962719093471234662863759
Line 119, in log /workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2039648884 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2039660800 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2039660800 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 2039668884 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1