UART Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	56.500s	10.585ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.000s	17.349us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.990s	11.751us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.540s	1.648ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.200s	17.853us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.710s	26.181us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.990s	11.751us	20	20	100.00
		uart_csr_aliasing	1.200s	17.853us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.632m	150.236ms	50	50	100.00
V2	parity	uart_smoke	56.500s	10.585ms	50	50	100.00
		uart_tx_rx	3.632m	150.236ms	50	50	100.00
V2	parity_error	uart_intr	23.961m	777.552ms	49	50	98.00
		uart_rx_parity_err	14.099m	217.572ms	49	50	98.00
V2	watermark	uart_tx_rx	3.632m	150.236ms	50	50	100.00
		uart_intr	23.961m	777.552ms	49	50	98.00
V2	fifo_full	uart_fifo_full	8.512m	75.797ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	10.594m	203.115ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	13.426m	166.777ms	300	300	100.00
V2	rx_frame_err	uart_intr	23.961m	777.552ms	49	50	98.00
V2	rx_break_err	uart_intr	23.961m	777.552ms	49	50	98.00
V2	rx_timeout	uart_intr	23.961m	777.552ms	49	50	98.00
V2	perf	uart_perf	25.087m	31.870ms	50	50	100.00
V2	sys_loopback	uart_loopback	48.510s	10.808ms	50	50	100.00
V2	line_loopback	uart_loopback	48.510s	10.808ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	6.030m	198.034ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.432m	76.835ms	49	50	98.00
V2	tx_overide	uart_tx_ovrd	45.630s	6.928ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.591m	7.321ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	25.430m	151.344ms	49	50	98.00
V2	stress_all	uart_stress_all	42.671m	408.837ms	48	50	96.00
V2	alert_test	uart_alert_test	0.980s	13.554us	50	50	100.00
V2	intr_test	uart_intr_test	0.900s	23.366us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.900s	144.785us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.900s	144.785us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.000s	17.349us	5	5	100.00
		uart_csr_rw	0.990s	11.751us	20	20	100.00
		uart_csr_aliasing	1.200s	17.853us	5	5	100.00
		uart_same_csr_outstanding	1.220s	103.633us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.000s	17.349us	5	5	100.00
		uart_csr_rw	0.990s	11.751us	20	20	100.00
		uart_csr_aliasing	1.200s	17.853us	5	5	100.00
		uart_same_csr_outstanding	1.220s	103.633us	20	20	100.00
V2		TOTAL			1083	1090	99.36
V2S	tl_intg_err	uart_sec_cm	1.540s	84.247us	5	5	100.00
		uart_tl_intg_err	2.050s	351.128us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.050s	351.128us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.204m	22.505ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1311	1320	99.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	12	66.67
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.08	97.65	100.00	--	98.35	100.00	99.62

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

Test uart_stress_all has 2 failures.

14.uart_stress_all.10512132494935502118944017233858447464382464756419060438519617510708543197772
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/14.uart_stress_all/latest/run.log

  UVM_ERROR @ 162875370 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 240965370 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout
  UVM_INFO @ 2647735370 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr

42.uart_stress_all.21488986099399910865992643581194040805803893917495891593966794812489016687064
Line 113, in log /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/42.uart_stress_all/latest/run.log

  UVM_ERROR @ 227966933418 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 228052717413 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 228226379220 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty

Test uart_noise_filter has 1 failures.

20.uart_noise_filter.107574273650764343824922399352139365516340980358296257042328084874096099220090
Line 61, in log /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/20.uart_noise_filter/latest/run.log

  UVM_ERROR @  13289214 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 2072649214 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/5
  UVM_INFO @ 3002849214 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/5
  UVM_INFO @ 37253849214 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/5
  UVM_INFO @ 38305569214 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/5

Job returned non-zero exit code has 2 failures:

Test uart_rx_start_bit_filter has 1 failures.

0.uart_rx_start_bit_filter.11781530044594489093959931262306690952048773791616286839856448261885937500095
Log /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_rx_start_bit_filter/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  2 19:06 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test uart_rx_parity_err has 1 failures.

0.uart_rx_parity_err.29024456304841081311177554559950410143478534025248512936382621112578540834024
Log /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/0.uart_rx_parity_err/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  2 19:06 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

UVM_ERROR (cip_base_vseq.sv:771) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

10.uart_stress_all_with_rand_reset.91808468516103292142412137262424755452915446432485253446065383426573457505258
Line 134, in log /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6291288088 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6291288088 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 8/10
  UVM_INFO @ 6291413089 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 8/10

85.uart_stress_all_with_rand_reset.14060868796766924917059430520918832122666132085204326427532478671421310550867
Line 87, in log /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 772979095 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 772979095 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 4/10
  UVM_INFO @ 773079095 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 4/10

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

18.uart_long_xfer_wo_dly.67969502607795611212532624029005012732349430364120383447357038639609124513902
Line 61, in log /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 363793462 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 431088118 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 565853902 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 1082858038 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 2522281318 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxDone has 1 failures:

Test uart_intr has 1 failures.

41.uart_intr.54891443575078359369538758577597583636394246068153112179159073829180755583739
Line 73, in log /workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/41.uart_intr/latest/run.log

  UVM_ERROR @ 3796441921 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxDone
  UVM_INFO @ 3800641921 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout
  UVM_INFO @ 5968241921 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty