UART Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	34.540s	5.835ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.820s	1.030ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.950s	42.219us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.260s	214.031us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.160s	79.959us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.690s	29.010us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.950s	42.219us	20	20	100.00
		uart_csr_aliasing	1.160s	79.959us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.486m	69.046ms	50	50	100.00
V2	parity	uart_smoke	34.540s	5.835ms	50	50	100.00
		uart_tx_rx	5.486m	69.046ms	50	50	100.00
V2	parity_error	uart_intr	7.640m	239.492ms	46	50	92.00
		uart_rx_parity_err	12.174m	239.968ms	50	50	100.00
V2	watermark	uart_tx_rx	5.486m	69.046ms	50	50	100.00
		uart_intr	7.640m	239.492ms	46	50	92.00
V2	fifo_full	uart_fifo_full	6.794m	164.781ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	12.350m	130.466ms	49	50	98.00
V2	fifo_reset	uart_fifo_reset	11.152m	312.354ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.640m	239.492ms	46	50	92.00
V2	rx_break_err	uart_intr	7.640m	239.492ms	46	50	92.00
V2	rx_timeout	uart_intr	7.640m	239.492ms	46	50	92.00
V2	perf	uart_perf	25.000m	22.944ms	50	50	100.00
V2	sys_loopback	uart_loopback	34.210s	9.845ms	50	50	100.00
V2	line_loopback	uart_loopback	34.210s	9.845ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	8.564m	89.852ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.741m	47.560ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	30.440s	6.171ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	58.900s	5.078ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	31.436m	175.942ms	50	50	100.00
V2	stress_all	uart_stress_all	26.335m	264.081ms	50	50	100.00
V2	alert_test	uart_alert_test	0.900s	16.180us	50	50	100.00
V2	intr_test	uart_intr_test	0.900s	39.424us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.600s	162.614us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.600s	162.614us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.820s	1.030ms	5	5	100.00
		uart_csr_rw	0.950s	42.219us	20	20	100.00
		uart_csr_aliasing	1.160s	79.959us	5	5	100.00
		uart_same_csr_outstanding	1.120s	18.032us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.820s	1.030ms	5	5	100.00
		uart_csr_rw	0.950s	42.219us	20	20	100.00
		uart_csr_aliasing	1.160s	79.959us	5	5	100.00
		uart_same_csr_outstanding	1.120s	18.032us	20	20	100.00
V2		TOTAL			1085	1090	99.54
V2S	tl_intg_err	uart_sec_cm	1.950s	266.622us	5	5	100.00
		uart_tl_intg_err	1.980s	90.443us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.980s	90.443us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.087m	87.533ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1312	1320	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.08	97.65	100.00	--	98.35	100.00	99.57

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty

has 4 failures:

Test uart_intr has 4 failures.

10.uart_intr.71188151282216953668129092990493199435776898854712694937123147282017096950681
Line 107, in log /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_intr/latest/run.log

  UVM_ERROR @ 31936320239 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 31936320239 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 31980007040 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 32414333424 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

12.uart_intr.30689368911894379077964938562041625259758679596854529345045964230375602955121
Line 84, in log /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_intr/latest/run.log

  UVM_ERROR @ 21256128646 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 21340713991 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 21512668111 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:771) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 3 failures:

Test uart_stress_all_with_rand_reset has 3 failures.

28.uart_stress_all_with_rand_reset.22590679086966804075979717798227147134739376052882092577589017684852803917844
Line 130, in log /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6895726156 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6895726156 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 7/10
  UVM_INFO @ 6895856418 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_smoke_vseq] finished run 1/2
  UVM_INFO @ 6895856418 ps: (uart_stress_all_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_stress_all_vseq] starting stress_all sub-sequence uart_perf_vseq

64.uart_stress_all_with_rand_reset.100898505635423896484759462086267831404910938102236698805721032794391569561729
Line 71, in log /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 579532975 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 579532975 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 579961546 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 2/5

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_fifo_overflow has 1 failures.
  - 19.uart_fifo_overflow.60102093424388841235079063993054867302704048181632813667923485232457461405669
    Line 71, in log /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_fifo_overflow/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```