UART Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	44.330s	11.072ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.840s	16.662us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.880s	14.598us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.040s	218.903us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.030s	31.026us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.640s	175.306us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.880s	14.598us	20	20	100.00
		uart_csr_aliasing	1.030s	31.026us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.005m	78.019ms	50	50	100.00
V2	parity	uart_smoke	44.330s	11.072ms	50	50	100.00
		uart_tx_rx	4.005m	78.019ms	50	50	100.00
V2	parity_error	uart_intr	7.316m	209.481ms	48	50	96.00
		uart_rx_parity_err	11.424m	124.006ms	50	50	100.00
V2	watermark	uart_tx_rx	4.005m	78.019ms	50	50	100.00
		uart_intr	7.316m	209.481ms	48	50	96.00
V2	fifo_full	uart_fifo_full	7.192m	152.519ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.150m	295.489ms	49	50	98.00
V2	fifo_reset	uart_fifo_reset	15.126m	233.457ms	299	300	99.67
V2	rx_frame_err	uart_intr	7.316m	209.481ms	48	50	96.00
V2	rx_break_err	uart_intr	7.316m	209.481ms	48	50	96.00
V2	rx_timeout	uart_intr	7.316m	209.481ms	48	50	96.00
V2	perf	uart_perf	26.750m	27.869ms	50	50	100.00
V2	sys_loopback	uart_loopback	25.280s	6.221ms	50	50	100.00
V2	line_loopback	uart_loopback	25.280s	6.221ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	6.927m	160.876ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.209m	51.624ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	35.690s	6.826ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.769m	7.934ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	20.825m	138.676ms	50	50	100.00
V2	stress_all	uart_stress_all	50.284m	333.275ms	50	50	100.00
V2	alert_test	uart_alert_test	0.990s	22.345us	50	50	100.00
V2	intr_test	uart_intr_test	0.840s	16.728us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.610s	88.985us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.610s	88.985us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.840s	16.662us	5	5	100.00
		uart_csr_rw	0.880s	14.598us	20	20	100.00
		uart_csr_aliasing	1.030s	31.026us	5	5	100.00
		uart_same_csr_outstanding	1.140s	36.945us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.840s	16.662us	5	5	100.00
		uart_csr_rw	0.880s	14.598us	20	20	100.00
		uart_csr_aliasing	1.030s	31.026us	5	5	100.00
		uart_same_csr_outstanding	1.140s	36.945us	20	20	100.00
V2		TOTAL			1085	1090	99.54
V2S	tl_intg_err	uart_sec_cm	1.380s	62.679us	5	5	100.00
		uart_tl_intg_err	1.860s	497.295us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.860s	497.295us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.860m	5.046ms	96	100	96.00
V3		TOTAL			96	100	96.00
		TOTAL			1311	1320	99.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	14	77.78
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.08	97.65	100.00	--	98.35	100.00	99.53

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 4 failures:

Test uart_intr has 2 failures.

22.uart_intr.105046074823274006473366336924492882239664247295745520154509458266966541647560
Line 94, in log /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/22.uart_intr/latest/run.log

  UVM_ERROR @ 53803626983 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 53888855108 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark
  UVM_INFO @ 54323904913 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark

26.uart_intr.32767384098756598563903475248008991812562844937129598976850879158473808985035
Line 109, in log /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/26.uart_intr/latest/run.log

  UVM_ERROR @ 14892632988 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 14977497473 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark
  UVM_INFO @ 15150453748 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark

Test uart_noise_filter has 1 failures.

24.uart_noise_filter.56541770468072365240872155015823350992194131562410145031726414999453506855895
Line 61, in log /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/24.uart_noise_filter/latest/run.log

  UVM_ERROR @   4884045 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 18237863241 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/12
  UVM_INFO @ 25073042922 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/12
  UVM_INFO @ 39907953267 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/12
  UVM_INFO @ 56710962690 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/12

Test uart_fifo_reset has 1 failures.

138.uart_fifo_reset.72370589233367544581279701480848982301931218952448581852388247911274007409400
Line 61, in log /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/138.uart_fifo_reset/latest/run.log

  UVM_ERROR @   1640993 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 1183272554 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/7
  UVM_INFO @ 1446072630 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7
  UVM_INFO @ 1591712707 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7
  UVM_INFO @ 1732206786 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/7

UVM_ERROR (cip_base_vseq.sv:771) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

44.uart_stress_all_with_rand_reset.25242020252896003901389334995576886576599897647190011444834940491994539087313
Line 90, in log /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4824591729 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4824591729 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 4824829824 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 3/10

71.uart_stress_all_with_rand_reset.70825765949382957816239596895146680054105058106417700287297733041668562903217
Line 140, in log /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11414388903 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 11414388903 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 8/10
  UVM_INFO @ 11414388903 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/5
  UVM_INFO @ 11414688903 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_fifo_overflow has 1 failures.
  - 12.uart_fifo_overflow.11484037842758026623576424863359954619020429192020491242244132895291888855041
    Line 70, in log /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/12.uart_fifo_overflow/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:867) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

72.uart_stress_all_with_rand_reset.22838713540557325891975839445105295569713261079794370335848990009224987307894
Line 143, in log /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2366818814 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2366821223 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2366821223 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 6/10
  UVM_INFO @ 2366828814 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

99.uart_stress_all_with_rand_reset.12223780119250185933901412009841899370821089145280059932572836171306028984659
Line 101, in log /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8724974115 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 8728091787 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 9/948
  UVM_ERROR @ 8798151171 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 8962976019 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 9050741427 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 10/948