USBDEV Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0.670s 1.843us 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.790s 23.811us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.090s 62.112us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.210s 1.521ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.500s 372.448us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 3.400s 145.807us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.090s 62.112us 20 20 100.00
usbdev_csr_aliasing 3.500s 372.448us 5 5 100.00
V1 mem_walk usbdev_mem_walk 3.920s 143.556us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.270s 200.580us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 intr_test usbdev_intr_test 0.720s 56.976us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.010s 234.034us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.010s 234.034us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.790s 23.811us 5 5 100.00
usbdev_csr_rw 1.090s 62.112us 20 20 100.00
usbdev_csr_aliasing 3.500s 372.448us 5 5 100.00
usbdev_same_csr_outstanding 9.320s 10.141ms 18 20 90.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.790s 23.811us 5 5 100.00
usbdev_csr_rw 1.090s 62.112us 20 20 100.00
usbdev_csr_aliasing 3.500s 372.448us 5 5 100.00
usbdev_same_csr_outstanding 9.320s 10.141ms 18 20 90.00
V2 TOTAL 88 90 97.78
V2S tl_intg_err usbdev_sec_cm 10.110s 10.006ms 0 5 0.00
usbdev_tl_intg_err 10.900s 10.010ms 5 20 25.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 10.900s 10.010ms 5 20 25.00
V2S TOTAL 5 25 20.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.670s 1.638us 0 50 0.00
usbdev_stress_all 0.650s 0 50 0.00
TOTAL 158 330 47.88

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 7 87.50
V2 3 3 2 66.67
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
69.76 69.43 63.91 87.42 0.00 74.05 97.77 95.72

Failure Buckets

Past Results