USBDEV Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 16.880s 10.125ms 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.940s 120.360us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.080s 95.853us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 7.420s 1.084ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.410s 389.230us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.550s 96.319us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.080s 95.853us 20 20 100.00
usbdev_csr_aliasing 3.410s 389.230us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.390s 173.568us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.400s 92.781us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 16.180s 10.136ms 49 50 98.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 16.090s 10.061ms 50 50 100.00
V2 av_buffer usbdev_av_buffer 16.680s 10.060ms 50 50 100.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 16.510s 10.114ms 50 50 100.00
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 16.860s 10.041ms 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 16.910s 10.095ms 50 50 100.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 16.580s 10.080ms 50 50 100.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 16.770s 10.099ms 50 50 100.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 16.120s 10.065ms 50 50 100.00
V2 in_stall usbdev_in_stall 16.440s 10.043ms 50 50 100.00
V2 out_iso out_iso 0 0 --
V2 in_iso usbdev_in_iso 16.740s 10.121ms 50 50 100.00
V2 pkt_received usbdev_pkt_received 17.260s 10.091ms 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 16.370s 10.067ms 50 50 100.00
V2 disconnected usbdev_disconnected 15.930s 10.042ms 50 50 100.00
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 21.050s 13.260ms 50 50 100.00
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err usbdev_link_in_err 16.330s 10.091ms 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 16.530s 10.049ms 50 50 100.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 15.850s 10.051ms 16 50 32.00
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 15.940s 10.051ms 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 17.130s 10.073ms 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 17.660s 10.672ms 43 50 86.00
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 17.500s 10.081ms 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 16.970s 10.083ms 50 50 100.00
V2 nak_trans usbdev_nak_trans 16.370s 10.076ms 50 50 100.00
V2 stall_trans usbdev_stall_trans 16.230s 10.078ms 50 50 100.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 16.070s 10.093ms 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 16.060s 10.054ms 50 50 100.00
V2 streaming_test streaming_test 0 0 --
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 1.100m 32.168ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume usbdev_aon_wake_resume 20.690s 13.277ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 20.890s 13.269ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 22.010s 13.781ms 50 50 100.00
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 19.850s 11.608ms 50 50 100.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 17.740s 10.112ms 50 50 100.00
V2 intr_test usbdev_intr_test 0.750s 43.352us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.500s 288.425us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.500s 288.425us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.940s 120.360us 5 5 100.00
usbdev_csr_rw 1.080s 95.853us 20 20 100.00
usbdev_csr_aliasing 3.410s 389.230us 5 5 100.00
usbdev_same_csr_outstanding 1.900s 243.638us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.940s 120.360us 5 5 100.00
usbdev_csr_rw 1.080s 95.853us 20 20 100.00
usbdev_csr_aliasing 3.410s 389.230us 5 5 100.00
usbdev_same_csr_outstanding 1.900s 243.638us 20 20 100.00
V2 TOTAL 1698 1740 97.59
V2S tl_intg_err usbdev_sec_cm 2.170s 1.189ms 5 5 100.00
usbdev_tl_intg_err 5.700s 1.105ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.700s 1.105ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 41.320s 5.118ms 1 1 100.00
usbdev_out_iso 15.570s 10.100ms 50 50 100.00
random_length_in_trans 16.350s 10.126ms 50 50 100.00
min_length_in_transaction 15.830s 10.082ms 50 50 100.00
max_length_in_transaction 16.190s 10.141ms 50 50 100.00
usbdev_stress_all_with_rand_reset 0.690s 59.097us 0 50 0.00
usbdev_stress_all 0.640s 0 50 0.00
TOTAL 1889 2031 93.01

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 2 50.00
V1 8 8 8 100.00
V2 76 36 33 43.42
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.56 97.44 92.01 97.86 70.31 95.72 98.17 96.40

Failure Buckets

Past Results