USBDEV Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 17.370s 10.124ms 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.070s 134.288us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.160s 145.307us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 11.970s 2.688ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.740s 381.371us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.380s 148.667us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.160s 145.307us 20 20 100.00
usbdev_csr_aliasing 3.740s 381.371us 5 5 100.00
V1 mem_walk usbdev_mem_walk 5.160s 736.874us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.390s 195.454us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 18.480s 10.135ms 50 50 100.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 17.770s 10.035ms 50 50 100.00
V2 av_buffer usbdev_av_buffer 18.420s 10.096ms 50 50 100.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 17.040s 10.117ms 50 50 100.00
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 17.430s 10.040ms 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 18.120s 10.097ms 50 50 100.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 18.070s 10.107ms 50 50 100.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 16.440s 10.053ms 50 50 100.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 18.400s 10.079ms 50 50 100.00
V2 in_stall usbdev_in_stall 17.680s 10.078ms 50 50 100.00
V2 out_iso out_iso 0 0 --
V2 in_iso usbdev_in_iso 16.870s 10.150ms 50 50 100.00
V2 pkt_received usbdev_pkt_received 17.160s 10.090ms 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 18.210s 10.102ms 50 50 100.00
V2 disconnected usbdev_disconnected 18.040s 10.046ms 50 50 100.00
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 23.000s 13.252ms 50 50 100.00
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err usbdev_link_in_err 19.040s 10.104ms 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 18.660s 10.041ms 50 50 100.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 17.290s 10.031ms 20 50 40.00
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 18.810s 10.076ms 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 17.920s 10.052ms 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 18.770s 10.596ms 43 50 86.00
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 17.970s 10.096ms 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 18.240s 10.057ms 50 50 100.00
V2 nak_trans usbdev_nak_trans 17.690s 10.131ms 50 50 100.00
V2 stall_trans usbdev_stall_trans 18.170s 10.080ms 50 50 100.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 18.210s 10.059ms 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 17.260s 10.075ms 50 50 100.00
V2 streaming_test streaming_test 0 0 --
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 1.137m 32.544ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume usbdev_aon_wake_resume 22.650s 13.358ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 21.600s 13.188ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 22.420s 14.172ms 50 50 100.00
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 18.720s 10.884ms 50 50 100.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 18.150s 10.291ms 50 50 100.00
V2 intr_test usbdev_intr_test 0.770s 58.776us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.470s 384.569us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.470s 384.569us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.070s 134.288us 5 5 100.00
usbdev_csr_rw 1.160s 145.307us 20 20 100.00
usbdev_csr_aliasing 3.740s 381.371us 5 5 100.00
usbdev_same_csr_outstanding 2.010s 234.582us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.070s 134.288us 5 5 100.00
usbdev_csr_rw 1.160s 145.307us 20 20 100.00
usbdev_csr_aliasing 3.740s 381.371us 5 5 100.00
usbdev_same_csr_outstanding 2.010s 234.582us 20 20 100.00
V2 TOTAL 1703 1740 97.87
V2S tl_intg_err usbdev_sec_cm 1.920s 1.026ms 5 5 100.00
usbdev_tl_intg_err 6.080s 1.720ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 6.080s 1.720ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 37.040s 5.107ms 1 1 100.00
usbdev_out_iso 18.340s 10.137ms 50 50 100.00
random_length_in_trans 17.760s 10.087ms 50 50 100.00
min_length_in_transaction 17.660s 10.066ms 49 50 98.00
max_length_in_transaction 18.260s 10.136ms 49 50 98.00
usbdev_stress_all_with_rand_reset 0.750s 40.699us 0 50 0.00
usbdev_stress_all 0.620s 0 50 0.00
TOTAL 1894 2031 93.25

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 2 50.00
V1 8 8 8 100.00
V2 76 36 34 44.74
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.59 97.44 92.03 97.86 70.31 95.72 98.17 96.58

Failure Buckets

Past Results