USBDEV Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.280s 234.692us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.010s 183.263us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.140s 106.761us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.490s 1.016ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.810s 334.326us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 3.060s 122.544us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.140s 106.761us 20 20 100.00
usbdev_csr_aliasing 3.810s 334.326us 5 5 100.00
V1 mem_walk usbdev_mem_walk 3.750s 189.767us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.400s 210.471us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.130s 245.008us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 1.930s 545.468us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.790s 106.822us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.000s 251.813us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.017m 23.493ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.090s 306.946us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.930s 189.153us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.190s 236.913us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.150s 268.414us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.000s 217.852us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 0.980s 209.303us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.920s 148.219us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.020s 201.560us 50 50 100.00
usbdev_stream_len_max 3.780s 1.319ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.170s 290.268us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.960s 204.214us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.970s 190.693us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.040s 219.051us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.060s 264.139us 50 50 100.00
V2 out_stall usbdev_out_stall 1.010s 227.535us 50 50 100.00
V2 in_stall usbdev_in_stall 0.960s 202.047us 50 50 100.00
V2 out_iso usbdev_out_iso 1.040s 190.053us 50 50 100.00
V2 in_iso usbdev_in_iso 1.410s 272.801us 50 50 100.00
V2 pkt_received usbdev_pkt_received 0.990s 232.769us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.100s 238.391us 50 50 100.00
V2 disconnected usbdev_disconnected 0.940s 177.225us 50 50 100.00
V2 host_lost usbdev_host_lost 9.960s 4.156ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.900s 171.860us 1 1 100.00
V2 link_suspend usbdev_link_suspend 15.410s 11.308ms 50 50 100.00
V2 link_resume usbdev_link_resume 53.340s 32.917ms 50 50 100.00
V2 av_empty usbdev_av_empty 0.980s 176.489us 5 5 100.00
V2 rx_full usbdev_rx_full 1.500s 471.081us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.880s 146.362us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.110s 319.833us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.010s 251.647us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 0.990s 267.034us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.980s 210.200us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.370s 454.027us 1 1 100.00
V2 enable usbdev_enable 0.790s 60.125us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 29.200s 20.168ms 20 20 100.00
V2 device_address usbdev_device_address 1.786m 56.302ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.620s 545.148us 1 1 100.00
V2 setup_stage usbdev_setup_stage 1.000s 218.277us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.870s 1.020ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 3.090s 1.583ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 2.520s 1.141ms 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 0.990s 189.225us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.000s 188.567us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.070s 230.927us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.000s 210.341us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.160s 302.992us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.020s 222.814us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.990s 142.465us 50 50 100.00
V2 streaming_test usbdev_streaming_out 2.103m 4.330ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.568m 120.245ms 5 5 100.00
usbdev_freq_loclk 3.620m 121.083ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.398m 120.355ms 5 5 100.00
usbdev_freq_loclk_max 2.761m 109.075ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.343m 119.108ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 2.103m 4.305ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.976m 4.081ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 41.740s 4.701ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 44.500s 7.016ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.017m 23.493ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.640s 494.179us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 43.720s 31.291ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 29.880s 21.077ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 16.960s 12.050ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.830m 5.891ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.490m 3.223ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.695m 5.636ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 3.649m 8.457ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 3.352m 7.635ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 5.228m 14.584ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.341m 2.757ms 25 25 100.00
usbdev_max_usb_traffic 1.106m 2.412ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 3.521m 11.035ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.818m 13.214ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.510s 1.417ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.500s 401.042us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 2.920s 431.234us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 2.050s 678.460us 500 500 100.00
V2 intr_test usbdev_intr_test 0.800s 77.991us 50 50 100.00
V2 alert_test usbdev_alert_test 0.760s 85.749us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.300s 303.163us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.300s 303.163us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.010s 183.263us 5 5 100.00
usbdev_csr_rw 1.140s 106.761us 20 20 100.00
usbdev_csr_aliasing 3.810s 334.326us 5 5 100.00
usbdev_same_csr_outstanding 1.790s 218.201us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.010s 183.263us 5 5 100.00
usbdev_csr_rw 1.140s 106.761us 20 20 100.00
usbdev_csr_aliasing 3.810s 334.326us 5 5 100.00
usbdev_same_csr_outstanding 1.790s 218.201us 20 20 100.00
V2 TOTAL 3599 3599 100.00
V2S tl_intg_err usbdev_sec_cm 2.050s 1.009ms 5 5 100.00
usbdev_tl_intg_err 6.240s 2.158ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 6.240s 2.158ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 50.090s 5.108ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.660s 36.141us 0 10 0.00
usbdev_stress_all 0.620s 0 50 0.00
TOTAL 3740 3800 98.42

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 85 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.27 98.14 95.96 97.44 88.89 98.26 98.17 90.05

Failure Buckets

Past Results