USBDEV Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.240s 241.104us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.020s 141.774us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.190s 143.432us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 8.980s 1.477ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.140s 119.672us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.590s 95.419us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.190s 143.432us 20 20 100.00
usbdev_csr_aliasing 3.140s 119.672us 5 5 100.00
V1 mem_walk usbdev_mem_walk 5.060s 711.128us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.440s 212.772us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.170s 316.523us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 2.070s 605.958us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.830s 65.936us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.040s 191.313us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.044m 23.243ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.170s 304.773us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.910s 176.258us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.160s 287.129us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.070s 224.284us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.050s 251.231us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.050s 218.973us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.000s 205.419us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.090s 238.319us 50 50 100.00
usbdev_stream_len_max 3.550s 1.359ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.170s 310.671us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.940s 193.700us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.010s 170.945us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.050s 185.327us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.040s 221.117us 50 50 100.00
V2 out_stall usbdev_out_stall 1.030s 273.375us 50 50 100.00
V2 in_stall usbdev_in_stall 0.920s 210.177us 50 50 100.00
V2 out_iso usbdev_out_iso 1.080s 241.054us 50 50 100.00
V2 in_iso usbdev_in_iso 1.330s 233.896us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.090s 202.971us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.060s 235.484us 50 50 100.00
V2 disconnected usbdev_disconnected 0.930s 188.517us 50 50 100.00
V2 host_lost usbdev_host_lost 9.800s 4.166ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.890s 207.086us 1 1 100.00
V2 link_suspend usbdev_link_suspend 16.060s 10.307ms 50 50 100.00
V2 link_resume usbdev_link_resume 59.360s 32.595ms 50 50 100.00
V2 av_empty usbdev_av_empty 0.980s 233.234us 5 5 100.00
V2 rx_full usbdev_rx_full 1.370s 364.685us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.900s 181.330us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.080s 230.334us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.970s 229.811us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 0.960s 238.192us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.970s 220.331us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.640s 553.697us 1 1 100.00
V2 enable usbdev_enable 0.850s 46.756us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 30.080s 20.169ms 20 20 100.00
V2 device_address usbdev_device_address 1.548m 47.683ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.520s 475.602us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.990s 244.786us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.700s 965.442us 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 2.540s 1.109ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 1.980s 833.734us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.080s 262.695us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.030s 217.364us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.090s 254.916us 50 50 100.00
V2 stall_trans usbdev_stall_trans 0.980s 251.188us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.110s 294.736us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0.990s 205.080us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.930s 164.679us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.794m 3.760ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.017m 109.198ms 5 5 100.00
usbdev_freq_loclk 2.938m 106.101ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.403m 121.048ms 5 5 100.00
usbdev_freq_loclk_max 3.319m 107.968ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.200m 114.143ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.968m 4.056ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.843m 3.896ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 45.980s 6.773ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 50.470s 2.082ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.044m 23.243ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.650s 554.844us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 46.290s 31.101ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 27.320s 20.986ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 16.690s 11.026ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.648m 5.341ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.749m 3.524ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.077m 4.168ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 7.550m 19.211ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 3.049m 6.696ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 2.843m 9.250ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.643m 3.359ms 25 25 100.00
usbdev_max_usb_traffic 1.331m 2.679ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 1.765m 7.054ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.822m 12.849ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.340s 1.210ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.540s 478.882us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 2.640s 354.865us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 2.040s 701.543us 500 500 100.00
V2 intr_test usbdev_intr_test 0.810s 48.339us 50 50 100.00
V2 alert_test usbdev_alert_test 0.780s 53.881us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.410s 256.807us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.410s 256.807us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.020s 141.774us 5 5 100.00
usbdev_csr_rw 1.190s 143.432us 20 20 100.00
usbdev_csr_aliasing 3.140s 119.672us 5 5 100.00
usbdev_same_csr_outstanding 2.330s 345.210us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.020s 141.774us 5 5 100.00
usbdev_csr_rw 1.190s 143.432us 20 20 100.00
usbdev_csr_aliasing 3.140s 119.672us 5 5 100.00
usbdev_same_csr_outstanding 2.330s 345.210us 20 20 100.00
V2 TOTAL 3599 3599 100.00
V2S tl_intg_err usbdev_sec_cm 2.200s 1.272ms 5 5 100.00
usbdev_tl_intg_err 6.360s 1.748ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 6.360s 1.748ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 49.490s 5.172ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.690s 61.307us 0 10 0.00
usbdev_stress_all 0.660s 0 50 0.00
TOTAL 3740 3800 98.42

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 85 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.56 98.11 95.94 97.44 94.92 98.30 98.17 93.03

Failure Buckets

Past Results