USBDEV Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.200s 305.750us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.020s 231.787us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.060s 72.236us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 8.300s 1.755ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.810s 311.224us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.810s 121.028us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.060s 72.236us 20 20 100.00
usbdev_csr_aliasing 3.810s 311.224us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.610s 635.490us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.500s 201.318us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.200s 320.296us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 1.940s 568.218us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.850s 81.823us 50 50 100.00
V2 av_buffer usbdev_av_buffer 0.980s 235.167us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 58.180s 19.875ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.130s 302.472us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.840s 166.216us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.160s 259.887us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.080s 259.534us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.040s 214.782us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.000s 239.099us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.940s 222.769us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.090s 275.944us 50 50 100.00
usbdev_stream_len_max 3.540s 1.366ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.150s 257.165us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.000s 218.482us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.950s 237.229us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.030s 257.031us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.040s 235.946us 50 50 100.00
V2 out_stall usbdev_out_stall 0.950s 230.388us 50 50 100.00
V2 in_stall usbdev_in_stall 0.970s 214.408us 50 50 100.00
V2 out_iso usbdev_out_iso 1.030s 218.175us 50 50 100.00
V2 in_iso usbdev_in_iso 1.340s 241.106us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.070s 255.943us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.130s 283.893us 50 50 100.00
V2 disconnected usbdev_disconnected 0.960s 227.094us 50 50 100.00
V2 host_lost usbdev_host_lost 10.010s 4.173ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.820s 174.105us 1 1 100.00
V2 link_suspend usbdev_link_suspend 16.840s 11.236ms 50 50 100.00
V2 link_resume usbdev_link_resume 57.810s 34.129ms 50 50 100.00
V2 av_empty usbdev_av_empty 0.960s 216.621us 5 5 100.00
V2 rx_full usbdev_rx_full 1.490s 398.077us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.870s 155.812us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.130s 256.075us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.010s 203.071us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 0.950s 225.874us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.970s 224.372us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.370s 429.481us 1 1 100.00
V2 enable usbdev_enable 0.800s 116.980us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 27.650s 20.170ms 20 20 100.00
V2 device_address usbdev_device_address 1.471m 46.586ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.440s 479.103us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.960s 208.073us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.820s 1.019ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 2.290s 979.707us 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 2.020s 790.729us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 0.960s 233.981us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.950s 197.624us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.150s 228.134us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.020s 252.103us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.140s 306.579us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0.960s 244.375us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.970s 219.601us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.980m 3.992ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.575m 116.193ms 5 5 100.00
usbdev_freq_loclk 3.339m 119.126ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.240m 111.380ms 5 5 100.00
usbdev_freq_loclk_max 3.084m 108.195ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 2.995m 110.178ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 2.001m 3.982ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.803m 3.615ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 1.002m 9.114ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 51.010s 7.742ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 58.180s 19.875ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.390s 437.409us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 44.420s 28.903ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 28.110s 20.864ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 17.020s 11.116ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.371m 4.843ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.856m 3.696ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.874m 5.659ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 2.335m 7.697ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 1.226m 3.518ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 5.180m 13.933ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.819m 4.132ms 25 25 100.00
usbdev_max_usb_traffic 1.428m 3.025ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 1.117m 5.904ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.569m 12.173ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.480s 1.350ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.400s 398.648us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 3.100s 482.442us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 1.980s 658.120us 498 500 99.60
V2 intr_test usbdev_intr_test 0.850s 106.688us 50 50 100.00
V2 alert_test usbdev_alert_test 0.770s 91.749us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.570s 310.935us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.570s 310.935us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.020s 231.787us 5 5 100.00
usbdev_csr_rw 1.060s 72.236us 20 20 100.00
usbdev_csr_aliasing 3.810s 311.224us 5 5 100.00
usbdev_same_csr_outstanding 1.860s 196.310us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.020s 231.787us 5 5 100.00
usbdev_csr_rw 1.060s 72.236us 20 20 100.00
usbdev_csr_aliasing 3.810s 311.224us 5 5 100.00
usbdev_same_csr_outstanding 1.860s 196.310us 20 20 100.00
V2 TOTAL 3597 3599 99.94
V2S tl_intg_err usbdev_sec_cm 1.840s 921.800us 5 5 100.00
usbdev_tl_intg_err 5.970s 1.508ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.970s 1.508ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 2.482m 5.119ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.700s 62.638us 0 10 0.00
usbdev_stress_all 0.610s 0 50 0.00
TOTAL 3738 3800 98.37

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 84 98.82
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.56 98.14 95.98 97.44 94.92 98.34 98.17 92.94

Failure Buckets

Past Results