USBDEV Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.190s 267.000us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.040s 182.278us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.090s 144.211us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.080s 910.577us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.570s 357.595us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.220s 83.451us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.090s 144.211us 20 20 100.00
usbdev_csr_aliasing 3.570s 357.595us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.520s 501.957us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.410s 170.652us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.110s 260.226us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 2.300s 758.376us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.810s 126.505us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.010s 256.882us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 59.620s 22.802ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.140s 318.701us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.920s 153.223us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.180s 270.235us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.130s 248.219us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 0.970s 215.701us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.130s 299.188us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.930s 220.443us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.060s 253.844us 50 50 100.00
usbdev_stream_len_max 3.630s 1.387ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.170s 316.490us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.960s 189.442us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.000s 214.099us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.110s 246.081us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.120s 304.854us 50 50 100.00
V2 out_stall usbdev_out_stall 1.030s 222.253us 50 50 100.00
V2 in_stall usbdev_in_stall 0.950s 167.148us 50 50 100.00
V2 out_iso usbdev_out_iso 1.000s 206.030us 50 50 100.00
V2 in_iso usbdev_in_iso 1.400s 296.600us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.040s 235.335us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.080s 250.771us 50 50 100.00
V2 disconnected usbdev_disconnected 0.900s 174.381us 50 50 100.00
V2 host_lost usbdev_host_lost 9.890s 4.160ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.920s 207.331us 1 1 100.00
V2 link_suspend usbdev_link_suspend 16.020s 10.698ms 50 50 100.00
V2 link_resume usbdev_link_resume 56.040s 34.025ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.070s 236.639us 5 5 100.00
V2 rx_full usbdev_rx_full 1.630s 388.425us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.890s 150.698us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.050s 265.742us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.020s 231.068us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 0.960s 209.364us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.950s 175.888us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.430s 475.610us 1 1 100.00
V2 enable usbdev_enable 0.870s 74.933us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 30.090s 20.173ms 20 20 100.00
V2 device_address usbdev_device_address 1.454m 47.674ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.400s 393.688us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.940s 190.720us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.820s 1.038ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 2.530s 937.488us 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 2.250s 1.095ms 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.070s 279.796us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.980s 207.874us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.140s 271.505us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.020s 175.443us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.020s 211.254us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.020s 264.562us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.000s 213.337us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.950m 3.998ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.216m 112.205ms 5 5 100.00
usbdev_freq_loclk 3.067m 114.096ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.041m 114.012ms 5 5 100.00
usbdev_freq_loclk_max 3.240m 116.128ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 2.977m 119.234ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 2.128m 4.327ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.903m 3.920ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 57.560s 8.449ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 53.300s 2.076ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 59.620s 22.802ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.620s 557.196us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 48.310s 31.091ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 29.320s 21.321ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 17.670s 12.266ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.404m 5.009ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.749m 3.641ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.723m 5.496ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 2.822m 6.414ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 3.667m 7.486ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 5.466m 14.660ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.662m 3.396ms 25 25 100.00
usbdev_max_usb_traffic 1.632m 3.343ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 2.178m 7.805ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.670m 12.835ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.660s 1.377ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.540s 413.172us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 2.880s 408.034us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 1.910s 569.327us 500 500 100.00
V2 intr_test usbdev_intr_test 0.870s 104.230us 50 50 100.00
V2 alert_test usbdev_alert_test 0.780s 59.015us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.300s 120.389us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.300s 120.389us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.040s 182.278us 5 5 100.00
usbdev_csr_rw 1.090s 144.211us 20 20 100.00
usbdev_csr_aliasing 3.570s 357.595us 5 5 100.00
usbdev_same_csr_outstanding 1.850s 149.263us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.040s 182.278us 5 5 100.00
usbdev_csr_rw 1.090s 144.211us 20 20 100.00
usbdev_csr_aliasing 3.570s 357.595us 5 5 100.00
usbdev_same_csr_outstanding 1.850s 149.263us 20 20 100.00
V2 TOTAL 3599 3599 100.00
V2S tl_intg_err usbdev_sec_cm 2.480s 1.804ms 5 5 100.00
usbdev_tl_intg_err 5.630s 1.360ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.630s 1.360ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 2.494m 5.134ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.720s 66.447us 0 10 0.00
usbdev_stress_all 0.680s 0 50 0.00
TOTAL 3740 3800 98.42

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 85 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.57 98.12 95.94 97.44 94.92 98.34 98.17 93.03

Failure Buckets

Past Results