USBDEV Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.260s 315.375us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.020s 199.434us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.160s 150.031us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 7.730s 1.249ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.230s 123.214us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.230s 93.223us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.160s 150.031us 20 20 100.00
usbdev_csr_aliasing 3.230s 123.214us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.810s 487.994us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.380s 165.056us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.240s 292.801us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 1.850s 482.036us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.780s 74.594us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.000s 216.814us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.044m 23.372ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.100s 339.258us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.970s 178.106us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.210s 318.591us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.110s 246.982us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.100s 238.707us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.080s 249.274us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.000s 221.575us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.110s 300.127us 50 50 100.00
usbdev_stream_len_max 3.380s 1.392ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.170s 255.157us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.000s 173.009us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.010s 155.480us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.050s 205.902us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.110s 233.814us 50 50 100.00
V2 out_stall usbdev_out_stall 1.030s 202.022us 50 50 100.00
V2 in_stall usbdev_in_stall 0.990s 209.611us 50 50 100.00
V2 out_iso usbdev_out_iso 1.170s 190.593us 50 50 100.00
V2 in_iso usbdev_in_iso 1.380s 256.370us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.130s 268.495us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.150s 260.303us 50 50 100.00
V2 disconnected usbdev_disconnected 1.050s 217.557us 50 50 100.00
V2 host_lost usbdev_host_lost 10.720s 4.174ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.970s 229.148us 1 1 100.00
V2 link_suspend usbdev_link_suspend 16.140s 11.291ms 50 50 100.00
V2 link_resume usbdev_link_resume 1.043m 33.917ms 50 50 100.00
V2 av_empty usbdev_av_empty 0.950s 176.477us 5 5 100.00
V2 rx_full usbdev_rx_full 1.430s 435.760us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.890s 159.824us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.120s 240.083us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.960s 239.187us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.030s 272.885us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.970s 203.430us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.630s 457.553us 1 1 100.00
V2 enable usbdev_enable 0.800s 40.849us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 30.270s 20.151ms 20 20 100.00
V2 device_address usbdev_device_address 1.440m 51.378ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.490s 491.595us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.940s 247.882us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.900s 1.104ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 2.720s 1.128ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 2.430s 988.924us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.030s 248.714us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.960s 185.282us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.050s 266.746us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.020s 205.049us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.110s 303.390us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.050s 235.337us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.990s 197.883us 50 50 100.00
V2 streaming_test usbdev_streaming_out 2.127m 4.118ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.174m 109.191ms 5 5 100.00
usbdev_freq_loclk 3.037m 112.101ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.102m 98.231ms 5 5 100.00
usbdev_freq_loclk_max 3.062m 115.913ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.120m 111.154ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 2.208m 4.480ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.847m 3.759ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 46.270s 1.809ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 45.630s 6.774ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.044m 23.372ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.570s 520.203us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 44.660s 29.773ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 29.950s 20.580ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 18.970s 12.333ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.649m 5.486ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.816m 3.905ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.554m 5.200ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 2.886m 10.085ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 1.353m 12.860ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 3.590m 10.800ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.547m 3.138ms 25 25 100.00
usbdev_max_usb_traffic 1.691m 3.223ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 3.350m 7.539ms 4 5 80.00
V2 in_packet_retraction usbdev_iso_retraction 2.657m 12.775ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.410s 1.247ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.430s 381.183us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 2.930s 411.145us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 2.020s 687.536us 500 500 100.00
V2 intr_test usbdev_intr_test 0.860s 111.974us 50 50 100.00
V2 alert_test usbdev_alert_test 0.780s 108.171us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.710s 210.679us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.710s 210.679us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.020s 199.434us 5 5 100.00
usbdev_csr_rw 1.160s 150.031us 20 20 100.00
usbdev_csr_aliasing 3.230s 123.214us 5 5 100.00
usbdev_same_csr_outstanding 1.830s 385.049us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.020s 199.434us 5 5 100.00
usbdev_csr_rw 1.160s 150.031us 20 20 100.00
usbdev_csr_aliasing 3.230s 123.214us 5 5 100.00
usbdev_same_csr_outstanding 1.830s 385.049us 20 20 100.00
V2 TOTAL 3598 3599 99.97
V2S tl_intg_err usbdev_sec_cm 2.700s 1.920ms 5 5 100.00
usbdev_tl_intg_err 5.520s 1.192ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.520s 1.192ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 2.349m 5.107ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.740s 55.541us 0 10 0.00
usbdev_stress_all 0.630s 0 50 0.00
TOTAL 3739 3800 98.39

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 84 98.82
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.80 98.12 96.03 97.44 96.61 98.34 98.17 92.85

Failure Buckets

Past Results