USBDEV Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.200s 232.560us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.930s 123.961us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.130s 98.281us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.540s 1.674ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.700s 388.413us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.610s 96.507us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.130s 98.281us 20 20 100.00
usbdev_csr_aliasing 3.700s 388.413us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.790s 749.333us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.640s 212.044us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.150s 243.678us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 2.000s 660.835us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.800s 97.548us 50 50 100.00
V2 av_buffer usbdev_av_buffer 0.990s 227.263us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.016m 22.253ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.140s 308.222us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.940s 167.911us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.170s 271.489us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.140s 264.077us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.000s 233.117us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.000s 216.677us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.920s 188.771us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.070s 231.924us 50 50 100.00
usbdev_stream_len_max 3.310s 1.403ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.130s 302.395us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.980s 179.416us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.990s 227.562us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.090s 194.528us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.110s 304.327us 50 50 100.00
V2 out_stall usbdev_out_stall 1.000s 194.923us 50 50 100.00
V2 in_stall usbdev_in_stall 0.980s 174.536us 50 50 100.00
V2 out_iso usbdev_out_iso 1.010s 177.100us 50 50 100.00
V2 in_iso usbdev_in_iso 1.380s 279.207us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.030s 197.827us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.110s 274.743us 50 50 100.00
V2 disconnected usbdev_disconnected 0.940s 227.075us 50 50 100.00
V2 host_lost usbdev_host_lost 11.080s 4.155ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.980s 210.725us 1 1 100.00
V2 link_suspend usbdev_link_suspend 16.730s 10.288ms 50 50 100.00
V2 link_resume usbdev_link_resume 55.760s 34.613ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.000s 192.847us 5 5 100.00
V2 rx_full usbdev_rx_full 1.440s 409.466us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.920s 217.550us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.220s 254.417us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.190s 248.343us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 0.960s 174.929us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.950s 160.140us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.640s 566.652us 1 1 100.00
V2 enable usbdev_enable 0.840s 93.270us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 29.210s 20.164ms 20 20 100.00
V2 device_address usbdev_device_address 1.589m 50.174ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.410s 425.914us 1 1 100.00
V2 setup_stage usbdev_setup_stage 1.010s 188.174us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.780s 921.435us 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 2.410s 1.107ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 2.040s 902.158us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.070s 279.864us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.010s 157.916us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.070s 255.171us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.010s 204.845us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.100s 314.158us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.010s 192.238us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.950s 209.299us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.985m 4.022ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.303m 102.184ms 5 5 100.00
usbdev_freq_loclk 3.109m 99.105ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.351m 120.289ms 5 5 100.00
usbdev_freq_loclk_max 3.231m 113.058ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.248m 121.108ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 2.052m 4.154ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 2.173m 4.403ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 53.980s 5.713ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 1.020m 2.334ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.016m 22.253ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.590s 574.275us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 46.980s 30.668ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 28.810s 21.540ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 16.970s 12.005ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.489m 4.841ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.608m 3.226ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.760m 5.593ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 1.371m 3.510ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 3.616m 10.986ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 3.448m 10.147ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.561m 3.219ms 25 25 100.00
usbdev_max_usb_traffic 1.532m 3.112ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 3.909m 11.828ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.850m 13.200ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.660s 1.256ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.540s 439.736us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 2.910s 311.210us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 2.050s 552.099us 500 500 100.00
V2 intr_test usbdev_intr_test 0.850s 49.381us 50 50 100.00
V2 alert_test usbdev_alert_test 0.820s 83.803us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.060s 288.868us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.060s 288.868us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.930s 123.961us 5 5 100.00
usbdev_csr_rw 1.130s 98.281us 20 20 100.00
usbdev_csr_aliasing 3.700s 388.413us 5 5 100.00
usbdev_same_csr_outstanding 2.140s 431.120us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.930s 123.961us 5 5 100.00
usbdev_csr_rw 1.130s 98.281us 20 20 100.00
usbdev_csr_aliasing 3.700s 388.413us 5 5 100.00
usbdev_same_csr_outstanding 2.140s 431.120us 20 20 100.00
V2 TOTAL 3599 3599 100.00
V2S tl_intg_err usbdev_sec_cm 1.450s 471.392us 5 5 100.00
usbdev_tl_intg_err 6.090s 1.668ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 6.090s 1.668ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 39.120s 5.111ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.720s 86.117us 0 10 0.00
usbdev_stress_all 0.630s 0 50 0.00
TOTAL 3740 3800 98.42

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 85 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.56 98.14 95.89 97.44 94.92 98.34 98.17 93.03

Failure Buckets

Past Results