USBDEV Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.040s 274.387us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.820s 99.771us 5 5 100.00
V1 csr_rw usbdev_csr_rw 0.940s 52.168us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 8.860s 2.010ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 2.960s 332.850us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.090s 93.123us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 0.940s 52.168us 20 20 100.00
usbdev_csr_aliasing 2.960s 332.850us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.070s 517.375us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 1.940s 180.967us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.020s 271.234us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 1.940s 670.232us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.690s 127.808us 50 50 100.00
V2 av_buffer usbdev_av_buffer 0.920s 255.544us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 57.810s 24.398ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.020s 301.630us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.820s 164.000us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.040s 277.938us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.000s 288.851us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 0.950s 235.147us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 0.930s 252.225us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.830s 196.461us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 0.940s 243.298us 50 50 100.00
usbdev_stream_len_max 3.080s 1.244ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.030s 257.312us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.810s 197.455us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.890s 241.373us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 0.920s 255.255us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 0.990s 267.986us 50 50 100.00
V2 out_stall usbdev_out_stall 0.890s 219.098us 50 50 100.00
V2 in_stall usbdev_in_stall 0.830s 165.115us 50 50 100.00
V2 out_iso usbdev_out_iso 0.950s 194.517us 50 50 100.00
V2 in_iso usbdev_in_iso 1.160s 280.416us 50 50 100.00
V2 pkt_received usbdev_pkt_received 0.890s 224.549us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 0.990s 228.364us 50 50 100.00
V2 disconnected usbdev_disconnected 0.810s 160.938us 50 50 100.00
V2 host_lost usbdev_host_lost 9.630s 4.163ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.790s 192.056us 1 1 100.00
V2 link_suspend usbdev_link_suspend 14.720s 11.156ms 50 50 100.00
V2 link_resume usbdev_link_resume 52.310s 34.097ms 50 50 100.00
V2 av_empty usbdev_av_empty 0.830s 197.941us 5 5 100.00
V2 rx_full usbdev_rx_full 1.390s 417.955us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.810s 169.054us 5 5 100.00
V2 link_in_err usbdev_link_in_err 0.960s 238.460us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.920s 238.999us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 0.860s 204.459us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.860s 199.016us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.520s 508.057us 1 1 100.00
V2 enable usbdev_enable 0.690s 101.298us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 28.860s 20.146ms 20 20 100.00
V2 device_address usbdev_device_address 1.454m 51.296ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.460s 508.259us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.850s 185.847us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.730s 1.027ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 2.470s 1.057ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 1.930s 792.283us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 0.910s 190.539us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.870s 232.595us 50 50 100.00
V2 nak_trans usbdev_nak_trans 0.990s 284.896us 50 50 100.00
V2 stall_trans usbdev_stall_trans 0.910s 214.662us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 0.990s 309.772us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0.860s 206.401us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.870s 173.561us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.151m 2.922ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.203m 120.186ms 5 5 100.00
usbdev_freq_loclk 2.885m 107.095ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 2.663m 97.260ms 5 5 100.00
usbdev_freq_loclk_max 3.175m 118.105ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 2.518m 94.197ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.609m 3.990ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.569m 3.921ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 52.970s 9.701ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 53.050s 9.754ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 57.810s 24.398ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.490s 488.902us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 45.280s 31.144ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 29.070s 20.630ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 16.830s 12.082ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 1.980m 4.957ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.481m 3.810ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.427m 5.776ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 2.383m 9.088ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 2.561m 10.529ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 2.400m 9.293ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.380m 3.526ms 25 25 100.00
usbdev_max_usb_traffic 1.061m 2.734ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 1.202m 12.027ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.295m 13.483ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.190s 1.343ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.430s 458.580us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 2.550s 468.418us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 1.840s 686.730us 500 500 100.00
V2 intr_test usbdev_intr_test 0.750s 77.045us 50 50 100.00
V2 alert_test usbdev_alert_test 0.640s 69.391us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.140s 364.573us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.140s 364.573us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.820s 99.771us 5 5 100.00
usbdev_csr_rw 0.940s 52.168us 20 20 100.00
usbdev_csr_aliasing 2.960s 332.850us 5 5 100.00
usbdev_same_csr_outstanding 1.520s 195.535us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.820s 99.771us 5 5 100.00
usbdev_csr_rw 0.940s 52.168us 20 20 100.00
usbdev_csr_aliasing 2.960s 332.850us 5 5 100.00
usbdev_same_csr_outstanding 1.520s 195.535us 20 20 100.00
V2 TOTAL 3599 3599 100.00
V2S tl_intg_err usbdev_sec_cm 1.330s 694.601us 5 5 100.00
usbdev_tl_intg_err 5.540s 2.449ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.540s 2.449ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 42.430s 5.112ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.590s 68.806us 0 10 0.00
usbdev_stress_all 0.570s 0 50 0.00
TOTAL 3740 3800 98.42

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 85 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.34 98.16 96.03 97.44 93.22 98.38 98.17 92.94

Failure Buckets

Past Results