USBDEV Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.170s 270.927us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.970s 111.903us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.050s 91.533us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.130s 984.027us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.890s 294.532us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.610s 104.230us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.050s 91.533us 20 20 100.00
usbdev_csr_aliasing 3.890s 294.532us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.370s 625.961us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.480s 171.198us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.160s 233.743us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 2.010s 627.198us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.790s 111.648us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.030s 244.412us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.063m 19.212ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.100s 345.274us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.980s 231.632us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.290s 307.749us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.100s 250.364us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.070s 236.913us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 0.990s 230.413us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.000s 145.234us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.160s 194.714us 50 50 100.00
usbdev_stream_len_max 3.540s 1.340ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.160s 297.262us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.990s 236.561us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.070s 196.192us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.040s 257.578us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.230s 251.863us 50 50 100.00
V2 out_stall usbdev_out_stall 1.000s 200.647us 50 50 100.00
V2 in_stall usbdev_in_stall 1.000s 210.921us 50 50 100.00
V2 out_iso usbdev_out_iso 1.100s 200.947us 50 50 100.00
V2 in_iso usbdev_in_iso 1.500s 243.214us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.020s 200.596us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.110s 246.956us 50 50 100.00
V2 disconnected usbdev_disconnected 0.990s 175.933us 50 50 100.00
V2 host_lost usbdev_host_lost 11.230s 4.165ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.870s 191.791us 1 1 100.00
V2 link_suspend usbdev_link_suspend 16.260s 10.941ms 50 50 100.00
V2 link_resume usbdev_link_resume 57.660s 31.052ms 50 50 100.00
V2 av_empty usbdev_av_empty 0.940s 201.623us 5 5 100.00
V2 rx_full usbdev_rx_full 1.470s 424.191us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.940s 208.311us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.160s 256.689us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.970s 169.746us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.000s 225.991us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.050s 159.042us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.590s 489.854us 1 1 100.00
V2 enable usbdev_enable 0.820s 85.067us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 30.450s 20.167ms 20 20 100.00
V2 device_address usbdev_device_address 1.540m 50.644ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.670s 516.783us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.970s 199.379us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 3.060s 1.238ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 2.880s 1.418ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 2.440s 1.121ms 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.070s 240.026us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.990s 219.885us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.100s 253.321us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.050s 247.995us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.100s 304.736us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.000s 226.852us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.990s 160.316us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.802m 3.736ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.331m 116.179ms 5 5 100.00
usbdev_freq_loclk 3.620m 113.104ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.202m 99.346ms 5 5 100.00
usbdev_freq_loclk_max 2.897m 88.948ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 2.835m 102.118ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.931m 3.688ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 2.139m 4.351ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 46.930s 5.258ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 51.770s 7.786ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.063m 19.212ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.450s 419.625us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 46.840s 31.359ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 29.540s 20.652ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 17.990s 11.433ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.693m 5.299ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.787m 3.687ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 3.084m 6.213ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 3.363m 7.394ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 3.774m 10.936ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 3.674m 11.178ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.691m 3.468ms 25 25 100.00
usbdev_max_usb_traffic 1.865m 3.573ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 1.304m 12.332ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 3.044m 13.129ms 49 50 98.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.740s 1.333ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.700s 492.163us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 3.070s 435.504us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 2.050s 652.942us 500 500 100.00
V2 intr_test usbdev_intr_test 0.820s 101.162us 50 50 100.00
V2 alert_test usbdev_alert_test 0.790s 120.815us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 4.060s 362.657us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 4.060s 362.657us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.970s 111.903us 5 5 100.00
usbdev_csr_rw 1.050s 91.533us 20 20 100.00
usbdev_csr_aliasing 3.890s 294.532us 5 5 100.00
usbdev_same_csr_outstanding 1.920s 320.859us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.970s 111.903us 5 5 100.00
usbdev_csr_rw 1.050s 91.533us 20 20 100.00
usbdev_csr_aliasing 3.890s 294.532us 5 5 100.00
usbdev_same_csr_outstanding 1.920s 320.859us 20 20 100.00
V2 TOTAL 3598 3599 99.97
V2S tl_intg_err usbdev_sec_cm 1.320s 445.368us 5 5 100.00
usbdev_tl_intg_err 5.530s 1.154ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.530s 1.154ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 2.589m 5.114ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.660s 42.575us 0 10 0.00
usbdev_stress_all 0.620s 0 50 0.00
TOTAL 3739 3800 98.39

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 84 98.82
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.28 98.11 95.94 97.44 93.22 98.30 98.17 92.76

Failure Buckets

Past Results