USBDEV Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.160s 267.413us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.000s 127.051us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.060s 83.599us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.050s 1.406ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.680s 357.506us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.440s 104.843us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.060s 83.599us 20 20 100.00
usbdev_csr_aliasing 3.680s 357.506us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.480s 476.669us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.410s 164.427us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.120s 257.110us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 1.940s 637.695us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.820s 96.823us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.000s 268.597us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.068m 21.684ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.120s 315.864us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.930s 178.733us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.280s 338.210us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.060s 208.380us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.030s 217.275us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.060s 234.569us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.960s 203.494us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.080s 209.742us 50 50 100.00
usbdev_stream_len_max 3.400s 1.430ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.170s 303.160us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.040s 191.497us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.970s 206.393us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.060s 236.014us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.100s 268.949us 50 50 100.00
V2 out_stall usbdev_out_stall 1.000s 229.898us 50 50 100.00
V2 in_stall usbdev_in_stall 0.950s 236.207us 50 50 100.00
V2 out_iso usbdev_out_iso 1.030s 243.537us 50 50 100.00
V2 in_iso usbdev_in_iso 1.360s 245.858us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.010s 223.635us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.090s 235.144us 50 50 100.00
V2 disconnected usbdev_disconnected 0.940s 173.800us 50 50 100.00
V2 host_lost usbdev_host_lost 9.780s 4.160ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.880s 193.009us 1 1 100.00
V2 link_suspend usbdev_link_suspend 17.260s 11.213ms 50 50 100.00
V2 link_resume usbdev_link_resume 56.300s 35.225ms 50 50 100.00
V2 av_empty usbdev_av_empty 0.930s 183.909us 5 5 100.00
V2 rx_full usbdev_rx_full 1.510s 394.563us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.900s 180.293us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.090s 242.021us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.990s 202.725us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 0.900s 180.462us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.060s 174.515us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.540s 501.121us 1 1 100.00
V2 enable usbdev_enable 0.830s 104.789us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 29.140s 20.190ms 20 20 100.00
V2 device_address usbdev_device_address 1.485m 49.006ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.300s 391.676us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.950s 209.528us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.970s 1.007ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 2.560s 1.056ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 1.950s 954.054us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.010s 187.188us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.960s 208.002us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.100s 243.233us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.010s 188.230us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.040s 366.928us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.020s 202.492us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.980s 200.189us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.906m 4.014ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.651m 121.191ms 5 5 100.00
usbdev_freq_loclk 3.038m 115.123ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 2.900m 104.330ms 5 5 100.00
usbdev_freq_loclk_max 3.558m 120.097ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.106m 112.162ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.817m 3.531ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 2.044m 4.088ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 48.350s 5.685ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 1.011m 9.044ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.068m 21.684ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.660s 483.582us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 45.830s 31.031ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 30.500s 20.191ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 18.250s 12.045ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.775m 5.514ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 2.052m 4.039ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.321m 4.476ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 1.561m 6.622ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 1.406m 3.574ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 4.357m 12.206ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.679m 3.630ms 25 25 100.00
usbdev_max_usb_traffic 1.362m 2.726ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 1.690m 13.054ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.615m 11.862ms 49 50 98.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.550s 1.406ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.540s 412.566us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 2.810s 353.127us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 2.080s 697.828us 500 500 100.00
V2 intr_test usbdev_intr_test 0.890s 116.330us 50 50 100.00
V2 alert_test usbdev_alert_test 0.760s 120.471us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.610s 352.731us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.610s 352.731us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.000s 127.051us 5 5 100.00
usbdev_csr_rw 1.060s 83.599us 20 20 100.00
usbdev_csr_aliasing 3.680s 357.506us 5 5 100.00
usbdev_same_csr_outstanding 1.840s 284.128us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.000s 127.051us 5 5 100.00
usbdev_csr_rw 1.060s 83.599us 20 20 100.00
usbdev_csr_aliasing 3.680s 357.506us 5 5 100.00
usbdev_same_csr_outstanding 1.840s 284.128us 20 20 100.00
V2 TOTAL 3598 3599 99.97
V2S tl_intg_err usbdev_sec_cm 1.500s 576.975us 5 5 100.00
usbdev_tl_intg_err 5.210s 1.326ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.210s 1.326ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 37.920s 5.136ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.670s 26.131us 0 10 0.00
usbdev_stress_all 0.670s 0 50 0.00
TOTAL 3739 3800 98.39

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 84 98.82
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.55 98.11 95.96 97.44 94.92 98.30 98.17 92.94

Failure Buckets

Past Results