USBDEV Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.150s 271.226us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.940s 105.211us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.110s 78.139us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.420s 1.585ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.330s 151.986us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.530s 104.361us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.110s 78.139us 20 20 100.00
usbdev_csr_aliasing 3.330s 151.986us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.720s 710.113us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.420s 87.814us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.140s 245.904us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 2.250s 685.875us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.770s 91.903us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.020s 225.062us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.017m 22.102ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.110s 371.587us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.910s 161.763us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.150s 266.840us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.200s 250.119us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.070s 244.944us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 0.990s 218.458us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.950s 227.985us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.060s 206.938us 50 50 100.00
usbdev_stream_len_max 3.430s 1.270ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.180s 296.745us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.000s 196.109us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.970s 168.393us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.060s 280.325us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.100s 304.685us 50 50 100.00
V2 out_stall usbdev_out_stall 1.060s 247.417us 50 50 100.00
V2 in_stall usbdev_in_stall 0.930s 194.846us 50 50 100.00
V2 out_iso usbdev_out_iso 1.020s 196.114us 50 50 100.00
V2 in_iso usbdev_in_iso 1.310s 234.016us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.030s 219.259us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.070s 229.189us 50 50 100.00
V2 disconnected usbdev_disconnected 0.940s 170.106us 50 50 100.00
V2 host_lost usbdev_host_lost 10.400s 4.155ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.890s 217.956us 1 1 100.00
V2 link_suspend usbdev_link_suspend 16.410s 11.358ms 50 50 100.00
V2 link_resume usbdev_link_resume 56.770s 33.298ms 50 50 100.00
V2 av_empty usbdev_av_empty 0.920s 172.834us 5 5 100.00
V2 rx_full usbdev_rx_full 1.480s 395.212us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.900s 165.509us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.110s 282.441us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.020s 200.207us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 0.970s 232.982us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.970s 217.297us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.560s 503.640us 1 1 100.00
V2 enable usbdev_enable 0.830s 99.941us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 31.160s 20.151ms 20 20 100.00
V2 device_address usbdev_device_address 1.434m 45.684ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.470s 456.686us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.960s 230.946us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 3.020s 1.049ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 2.330s 900.346us 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 1.950s 852.775us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.010s 178.943us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.010s 203.034us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.100s 258.643us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.060s 217.807us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.200s 363.165us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0.990s 177.422us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.000s 216.698us 50 50 100.00
V2 streaming_test usbdev_streaming_out 2.027m 4.213ms 49 50 98.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.565m 118.205ms 5 5 100.00
usbdev_freq_loclk 3.628m 118.092ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.207m 120.260ms 5 5 100.00
usbdev_freq_loclk_max 3.407m 110.205ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.269m 109.194ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 2.144m 4.415ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.912m 3.942ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 54.770s 8.393ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 52.120s 7.710ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.017m 22.102ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.430s 409.516us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 44.090s 29.219ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 31.010s 20.909ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 17.390s 12.094ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.623m 5.342ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.473m 3.082ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 3.190m 6.195ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 2.892m 6.674ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 5.167m 11.377ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 3.782m 11.435ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.683m 3.525ms 25 25 100.00
usbdev_max_usb_traffic 1.724m 3.680ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 2.374m 8.745ms 4 5 80.00
V2 in_packet_retraction usbdev_iso_retraction 2.825m 12.935ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.640s 1.414ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.480s 397.527us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 2.980s 459.328us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 2.010s 694.555us 500 500 100.00
V2 intr_test usbdev_intr_test 0.840s 99.354us 50 50 100.00
V2 alert_test usbdev_alert_test 0.770s 83.362us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.680s 290.733us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.680s 290.733us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.940s 105.211us 5 5 100.00
usbdev_csr_rw 1.110s 78.139us 20 20 100.00
usbdev_csr_aliasing 3.330s 151.986us 5 5 100.00
usbdev_same_csr_outstanding 1.900s 268.674us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.940s 105.211us 5 5 100.00
usbdev_csr_rw 1.110s 78.139us 20 20 100.00
usbdev_csr_aliasing 3.330s 151.986us 5 5 100.00
usbdev_same_csr_outstanding 1.900s 268.674us 20 20 100.00
V2 TOTAL 3597 3599 99.94
V2S tl_intg_err usbdev_sec_cm 1.590s 630.467us 5 5 100.00
usbdev_tl_intg_err 5.370s 874.929us 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.370s 874.929us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 2.369m 5.100ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.760s 115.080us 0 10 0.00
usbdev_stress_all 0.620s 0 50 0.00
TOTAL 3738 3800 98.37

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 83 97.65
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.55 98.11 95.98 97.44 94.92 98.30 98.17 92.94

Failure Buckets

Past Results