USBDEV Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.240s 326.214us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.130s 247.819us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.120s 166.567us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.120s 1.289ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.620s 366.811us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.060s 101.400us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.120s 166.567us 20 20 100.00
usbdev_csr_aliasing 3.620s 366.811us 5 5 100.00
V1 mem_walk usbdev_mem_walk 3.890s 165.347us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.320s 220.517us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.120s 280.455us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 2.310s 625.245us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.820s 55.630us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.000s 226.388us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.084m 23.354ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.130s 334.951us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.940s 189.277us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.190s 310.255us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.120s 278.386us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.070s 263.029us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.010s 225.931us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.970s 216.163us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.070s 240.058us 50 50 100.00
usbdev_stream_len_max 3.520s 1.363ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.180s 317.540us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.960s 175.666us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.010s 159.635us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.050s 212.281us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.130s 251.454us 50 50 100.00
V2 out_stall usbdev_out_stall 1.090s 276.147us 50 50 100.00
V2 in_stall usbdev_in_stall 0.970s 152.768us 50 50 100.00
V2 out_iso usbdev_out_iso 0.990s 256.848us 50 50 100.00
V2 in_iso usbdev_in_iso 1.320s 260.520us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.070s 204.928us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.090s 254.449us 50 50 100.00
V2 disconnected usbdev_disconnected 0.980s 191.204us 50 50 100.00
V2 host_lost usbdev_host_lost 11.590s 4.251ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.810s 165.534us 1 1 100.00
V2 link_suspend usbdev_link_suspend 15.300s 10.975ms 50 50 100.00
V2 link_resume usbdev_link_resume 56.950s 34.047ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.010s 233.240us 5 5 100.00
V2 rx_full usbdev_rx_full 1.450s 360.483us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.900s 178.868us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.100s 255.886us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.020s 201.912us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.020s 198.295us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.970s 182.978us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.570s 533.437us 1 1 100.00
V2 enable usbdev_enable 0.810s 75.728us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 29.890s 20.160ms 20 20 100.00
V2 device_address usbdev_device_address 1.493m 51.013ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.470s 489.893us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.950s 195.386us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 3.090s 1.109ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 2.830s 1.248ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 2.020s 735.033us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 1.010s 224.535us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.970s 170.636us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.140s 279.567us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.100s 222.648us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.020s 205.276us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.050s 168.378us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.000s 227.887us 50 50 100.00
V2 streaming_test usbdev_streaming_out 2.109m 4.232ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 3.434m 115.202ms 5 5 100.00
usbdev_freq_loclk 3.427m 119.115ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.632m 115.291ms 5 5 100.00
usbdev_freq_loclk_max 3.914m 119.158ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.523m 117.172ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.996m 4.061ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.928m 4.018ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 59.060s 8.400ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 58.480s 6.150ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.084m 23.354ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.610s 486.464us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 43.750s 28.741ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 29.100s 21.426ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 16.780s 10.782ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.732m 5.405ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.735m 3.553ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.658m 5.113ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 1.458m 3.238ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 1.948m 7.343ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 3.221m 10.376ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.581m 3.324ms 25 25 100.00
usbdev_max_usb_traffic 1.897m 3.747ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 2.677m 14.925ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.645m 12.849ms 50 50 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.800s 1.396ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.560s 472.984us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 3.140s 322.385us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 2.080s 595.528us 500 500 100.00
V2 intr_test usbdev_intr_test 0.840s 102.830us 50 50 100.00
V2 alert_test usbdev_alert_test 0.760s 122.784us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.410s 315.419us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.410s 315.419us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.130s 247.819us 5 5 100.00
usbdev_csr_rw 1.120s 166.567us 20 20 100.00
usbdev_csr_aliasing 3.620s 366.811us 5 5 100.00
usbdev_same_csr_outstanding 1.870s 287.255us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.130s 247.819us 5 5 100.00
usbdev_csr_rw 1.120s 166.567us 20 20 100.00
usbdev_csr_aliasing 3.620s 366.811us 5 5 100.00
usbdev_same_csr_outstanding 1.870s 287.255us 20 20 100.00
V2 TOTAL 3599 3599 100.00
V2S tl_intg_err usbdev_sec_cm 2.620s 1.513ms 5 5 100.00
usbdev_tl_intg_err 5.720s 1.332ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.720s 1.332ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 49.730s 5.130ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.690s 87.037us 0 10 0.00
usbdev_stress_all 0.650s 0 50 0.00
TOTAL 3740 3800 98.42

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 85 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.77 98.11 96.01 97.44 96.61 98.30 98.17 92.76

Failure Buckets

Past Results