e45ccd274a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | usbdev_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | usbdev_csr_hw_reset | 1.130s | 239.812us | 5 | 5 | 100.00 |
| V1 | csr_rw | usbdev_csr_rw | 1.200s | 78.967us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | usbdev_csr_bit_bash | 11.920s | 1.718ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | usbdev_csr_aliasing | 3.640s | 431.406us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | usbdev_csr_mem_rw_with_rand_reset | 2.570s | 96.775us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | usbdev_csr_rw | 1.200s | 78.967us | 20 | 20 | 100.00 |
| usbdev_csr_aliasing | 3.640s | 431.406us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | usbdev_mem_walk | 4.360s | 511.907us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | usbdev_mem_partial_access | 2.300s | 149.983us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | in_trans | usbdev_in_trans | 0 | 50 | 0.00 | ||
| V2 | data_toggle_clear | usbdev_data_toggle_clear | 0 | 50 | 0.00 | ||
| V2 | phy_pins_sense | usbdev_phy_pins_sense | 0 | 50 | 0.00 | ||
| V2 | av_buffer | usbdev_av_buffer | 0 | 50 | 0.00 | ||
| V2 | rx_fifo | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | phy_config_tx_osc_test_mode | usbdev_phy_config_tx_osc_test_mode | 0 | 1 | 0.00 | ||
| V2 | phy_config_eop_single_bit_handling | usbdev_phy_config_eop_single_bit_handling | 0 | 1 | 0.00 | ||
| V2 | phy_config_pinflip | usbdev_phy_config_pinflip | 0 | 50 | 0.00 | ||
| V2 | phy_config_rand_bus_type | usbdev_phy_config_rand_bus_type | 0 | 5 | 0.00 | ||
| V2 | phy_config_rx_dp_dn | usbdev_phy_config_rx_dp_dn | 0 | 1 | 0.00 | ||
| V2 | phy_config_tx_use_d_se0 | usbdev_phy_config_tx_use_d_se0 | 0 | 1 | 0.00 | ||
| V2 | phy_config_usb_ref_disable | usbdev_phy_config_usb_ref_disable | 0 | 50 | 0.00 | ||
| V2 | max_length_out_transaction | usbdev_max_length_out_transaction | 0 | 50 | 0.00 | ||
| usbdev_stream_len_max | 0 | 50 | 0.00 | ||||
| V2 | max_length_in_transaction | usbdev_max_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_out_transaction | usbdev_min_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_in_transaction | usbdev_min_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_out_transaction | usbdev_random_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_in_transaction | usbdev_random_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | out_stall | usbdev_out_stall | 0 | 50 | 0.00 | ||
| V2 | in_stall | usbdev_in_stall | 0 | 50 | 0.00 | ||
| V2 | out_iso | usbdev_out_iso | 0 | 50 | 0.00 | ||
| V2 | in_iso | usbdev_in_iso | 0 | 50 | 0.00 | ||
| V2 | pkt_received | usbdev_pkt_received | 0 | 50 | 0.00 | ||
| V2 | pkt_sent | usbdev_pkt_sent | 0 | 50 | 0.00 | ||
| V2 | disconnected | usbdev_disconnected | 0 | 50 | 0.00 | ||
| V2 | host_lost | usbdev_host_lost | 0 | 1 | 0.00 | ||
| V2 | link_reset | usbdev_link_reset | 0 | 1 | 0.00 | ||
| V2 | link_suspend | usbdev_link_suspend | 0 | 50 | 0.00 | ||
| V2 | link_resume | usbdev_link_resume | 0 | 50 | 0.00 | ||
| V2 | av_empty | usbdev_av_empty | 0 | 5 | 0.00 | ||
| V2 | rx_full | usbdev_rx_full | 0 | 50 | 0.00 | ||
| V2 | av_overflow | usbdev_av_overflow | 0 | 5 | 0.00 | ||
| V2 | link_in_err | usbdev_link_in_err | 0 | 50 | 0.00 | ||
| V2 | rx_crc_err | usbdev_rx_crc_err | 0 | 50 | 0.00 | ||
| V2 | rx_pid_err | usbdev_rx_pid_err | 0 | 5 | 0.00 | ||
| V2 | rx_bitstuff_err | usbdev_bitstuff_err | 0 | 50 | 0.00 | ||
| V2 | link_out_err | usbdev_link_out_err | 0 | 1 | 0.00 | ||
| V2 | enable | usbdev_enable | 0 | 50 | 0.00 | ||
| V2 | resume_link_active | usbdev_resume_link_active | 0 | 20 | 0.00 | ||
| V2 | device_address | usbdev_device_address | 0 | 50 | 0.00 | ||
| V2 | invalid_data1_data0_toggle_test | usbdev_invalid_data1_data0_toggle_test | 0 | 1 | 0.00 | ||
| V2 | setup_stage | usbdev_setup_stage | 0 | 50 | 0.00 | ||
| V2 | endpoint_access | usbdev_endpoint_access | 0 | 50 | 0.00 | ||
| V2 | disable_endpoint | usbdev_disable_endpoint | 0 | 50 | 0.00 | ||
| V2 | endpoint_types | usbdev_endpoint_types | 0 | 200 | 0.00 | ||
| V2 | out_trans_nak | usbdev_out_trans_nak | 0 | 50 | 0.00 | ||
| V2 | setup_trans_ignored | usbdev_setup_trans_ignored | 0 | 50 | 0.00 | ||
| V2 | nak_trans | usbdev_nak_trans | 0 | 50 | 0.00 | ||
| V2 | stall_trans | usbdev_stall_trans | 0 | 50 | 0.00 | ||
| V2 | setup_priority_over_stall_response | usbdev_setup_priority_over_stall_response | 0 | 5 | 0.00 | ||
| V2 | stall_priority_over_nak | usbdev_stall_priority_over_nak | 0 | 50 | 0.00 | ||
| V2 | pending_in_trans | usbdev_pending_in_trans | 0 | 50 | 0.00 | ||
| V2 | streaming_test | usbdev_streaming_out | 0 | 50 | 0.00 | ||
| V2 | max_clock_error_untracked | usbdev_freq_hiclk | 0 | 5 | 0.00 | ||
| usbdev_freq_loclk | 0 | 5 | 0.00 | ||||
| V2 | max_clock_error_tracking | usbdev_freq_hiclk_max | 0 | 5 | 0.00 | ||
| usbdev_freq_loclk_max | 0 | 5 | 0.00 | ||||
| V2 | max_phase_error | usbdev_freq_phase | 0 | 5 | 0.00 | ||
| V2 | min_inter_pkt_delay | usbdev_min_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | max_inter_pkt_delay | usbdev_max_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | device_timeout_missing_host_handshake | usbdev_timeout_missing_host_handshake | 0 | 50 | 0.00 | ||
| V2 | device_timeout | usbdev_device_timeout | 0 | 50 | 0.00 | ||
| V2 | packet_buffer | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | nak_to_out_trans_when_avbuffer_empty_rxfifo_full | usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full | 0 | 1 | 0.00 | ||
| V2 | aon_wake_resume | usbdev_aon_wake_resume | 0 | 50 | 0.00 | ||
| V2 | aon_wake_reset | usbdev_aon_wake_reset | 0 | 50 | 0.00 | ||
| V2 | aon_wake_disconnect | usbdev_aon_wake_disconnect | 0 | 50 | 0.00 | ||
| V2 | invalid_sync | usbdev_invalid_sync | 0 | 50 | 0.00 | ||
| V2 | spurious_pids_ignored | usbdev_spurious_pids_ignored | 0 | 50 | 0.00 | ||
| V2 | low_speed_traffic | usbdev_low_speed_traffic | 0 | 50 | 0.00 | ||
| V2 | rand_bus_resets | usbdev_rand_bus_resets | 0 | 10 | 0.00 | ||
| V2 | rand_disconnects | usbdev_rand_bus_disconnects | 0 | 10 | 0.00 | ||
| V2 | rand_suspends | usbdev_rand_suspends | 0 | 10 | 0.00 | ||
| V2 | max_usb_traffic | usbdev_max_non_iso_usb_traffic | 0 | 25 | 0.00 | ||
| usbdev_max_usb_traffic | 0 | 15 | 0.00 | ||||
| V2 | stress_usb_traffic | usbdev_stress_usb_traffic | 0 | 5 | 0.00 | ||
| V2 | in_packet_retraction | usbdev_iso_retraction | 0 | 50 | 0.00 | ||
| V2 | data_toggle_restore | usbdev_data_toggle_restore | 0 | 50 | 0.00 | ||
| V2 | setup_priority | usbdev_setup_priority | 0 | 5 | 0.00 | ||
| V2 | fifo_resets | usbdev_fifo_rst | 0 | 50 | 0.00 | ||
| V2 | usbdev_tx_rx_disruption | usbdev_tx_rx_disruption | 0 | 500 | 0.00 | ||
| V2 | intr_test | usbdev_intr_test | 0.880s | 49.869us | 50 | 50 | 100.00 |
| V2 | alert_test | usbdev_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | usbdev_tl_errors | 3.340s | 300.443us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | usbdev_tl_errors | 3.340s | 300.443us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | usbdev_csr_hw_reset | 1.130s | 239.812us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.200s | 78.967us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.640s | 431.406us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 2.170s | 327.328us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | usbdev_csr_hw_reset | 1.130s | 239.812us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.200s | 78.967us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.640s | 431.406us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 2.170s | 327.328us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 3599 | 2.50 | |||
| V2S | tl_intg_err | usbdev_sec_cm | 0 | 5 | 0.00 | ||
| usbdev_tl_intg_err | 5.480s | 1.358ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | usbdev_tl_intg_err | 5.480s | 1.358ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | dpi_config_host | usbdev_dpi_config_host | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | usbdev_stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| usbdev_stress_all | 0 | 50 | 0.00 | ||||
| TOTAL | 175 | 3800 | 4.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 85 | 85 | 3 | 3.53 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 61.31 | 65.57 | 60.87 | 86.57 | 0.00 | 71.17 | 97.77 | 47.24 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 1813 failures:
0.usbdev_aon_wake_disconnect.71769621595919739782632131505500179281913810815354829701714534259610318528970
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_disconnect/latest/run.log
2.usbdev_aon_wake_disconnect.77442972981471328567650723820361878326337675935187415414132425698167572950941
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_disconnect/latest/run.log
... and 21 more failures.
0.usbdev_aon_wake_resume.32390154465003959067630899545104216822936003236049783233499573770202973969598
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_resume/latest/run.log
2.usbdev_aon_wake_resume.38910253588129958549613318565711041346126920609761867048962868296419522455076
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_resume/latest/run.log
... and 21 more failures.
0.usbdev_av_empty.50002406452610745447001933685351430784055648683472528341519413054612932638091
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_empty/latest/run.log
2.usbdev_av_empty.10691832799203261407385445368787906772935144853815729029917668420846306385047
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_empty/latest/run.log
... and 1 more failures.
0.usbdev_bitstuff_err.39403164111113175513337430673543543924429967537009505626715600849679676255012
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_bitstuff_err/latest/run.log
2.usbdev_bitstuff_err.110336809386929317036680636256756022541367921849702797984552805359757163423856
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_bitstuff_err/latest/run.log
... and 21 more failures.
0.usbdev_data_toggle_restore.52518759764225499690901151862330835849660253409096779857108527072850234828664
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_restore/latest/run.log
2.usbdev_data_toggle_restore.7607774371216684414263187853857528775280790117327191886827483644535342014516
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_data_toggle_restore/latest/run.log
... and 21 more failures.
Job killed most likely because its dependent job failed. has 1812 failures:
0.usbdev_aon_wake_reset.11612361583968970919518248759407166647771898776855377062448437144459479139417
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_reset/latest/run.log
2.usbdev_aon_wake_reset.23023204610119962441984298828567386615921576363092913337692281141383042942649
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_reset/latest/run.log
... and 21 more failures.
0.usbdev_av_buffer.29321653670560893468554974133353978816030348305580761133032139274505621208280
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_buffer/latest/run.log
2.usbdev_av_buffer.20690610024586699933595662980710117362558051141589440863509923469171445129717
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_buffer/latest/run.log
... and 21 more failures.
0.usbdev_av_overflow.87256253548252831376819807237070122588327059101284014407281961351860593694785
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_overflow/latest/run.log
2.usbdev_av_overflow.16308151102542715030162451246670419834568702523394036467135749682598651664616
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_overflow/latest/run.log
... and 1 more failures.
0.usbdev_data_toggle_clear.85198250037620116569117163512761517456601083848393416062241275794247133618867
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_clear/latest/run.log
2.usbdev_data_toggle_clear.87697361640751196574986948031376355863135528768916596690348416410770506438268
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_data_toggle_clear/latest/run.log
... and 21 more failures.
0.usbdev_device_address.4937216824975216861752263017105399820925455289483630919952550141356192059904
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_device_address/latest/run.log
2.usbdev_device_address.53015632708509417963592400713969229123246630242553979305260883605648300418316
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_device_address/latest/run.log
... and 21 more failures.