USBDEV Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.910s 257.503us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.190s 143.497us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.390s 121.162us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 7.630s 1.411ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.590s 112.467us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.450s 141.327us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.390s 121.162us 20 20 100.00
usbdev_csr_aliasing 3.590s 112.467us 5 5 100.00
V1 mem_walk usbdev_mem_walk 3.320s 259.899us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.680s 178.947us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.930s 261.834us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 4.010s 645.321us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 1.280s 97.724us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.690s 242.029us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.570m 21.628ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 2.150s 348.435us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 1.580s 160.167us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 2.140s 285.090us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.810s 277.285us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.500s 283.813us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.650s 230.868us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.590s 223.113us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.840s 213.585us 50 50 100.00
usbdev_stream_len_max 6.320s 1.246ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.950s 306.309us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 1.600s 207.238us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.770s 248.194us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.770s 213.616us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.920s 240.782us 50 50 100.00
V2 out_stall usbdev_out_stall 1.700s 188.172us 50 50 100.00
V2 in_stall usbdev_in_stall 1.660s 209.206us 50 50 100.00
V2 out_iso usbdev_out_iso 1.780s 232.349us 50 50 100.00
V2 in_iso usbdev_in_iso 2.280s 238.259us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.860s 225.792us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.900s 250.648us 50 50 100.00
V2 disconnected usbdev_disconnected 1.600s 213.579us 50 50 100.00
V2 host_lost usbdev_host_lost 15.580s 4.152ms 1 1 100.00
V2 link_reset usbdev_link_reset 1.400s 169.470us 1 1 100.00
V2 link_suspend usbdev_link_suspend 32.630s 9.242ms 50 50 100.00
V2 link_resume usbdev_link_resume 1.854m 33.798ms 50 50 100.00
V2 av_empty usbdev_av_empty 1.680s 215.844us 5 5 100.00
V2 rx_full usbdev_rx_full 2.720s 392.770us 50 50 100.00
V2 av_overflow usbdev_av_overflow 1.630s 174.793us 5 5 100.00
V2 link_in_err usbdev_link_in_err 2.100s 268.258us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 1.700s 177.904us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.510s 190.531us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.640s 195.225us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.560s 387.462us 1 1 100.00
V2 enable usbdev_enable 1.240s 90.986us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 1.031m 20.165ms 20 20 100.00
V2 device_address usbdev_device_address 2.515m 47.267ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 2.350s 504.907us 1 1 100.00
V2 setup_stage usbdev_setup_stage 1.630s 211.498us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 5.050s 909.965us 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 6.320s 1.295ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 49.303s 195 200 97.50
V2 out_trans_nak usbdev_out_trans_nak 1.820s 218.913us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.650s 191.944us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.860s 227.204us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.670s 187.312us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.830s 301.626us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.730s 245.614us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.560s 226.606us 50 50 100.00
V2 streaming_test usbdev_streaming_out 2.798m 4.309ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 5.710m 95.188ms 5 5 100.00
usbdev_freq_loclk 6.173m 121.087ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 6.301m 107.131ms 5 5 100.00
usbdev_freq_loclk_max 6.646m 109.222ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 5.527m 99.119ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 2.491m 4.425ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 2.530m 4.373ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 1.162m 6.156ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 1.246m 6.126ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.570m 21.628ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 2.570s 500.546us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 1.636m 29.635ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 56.970s 20.353ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 33.930s 11.766ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 3.142m 5.013ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 2.421m 3.981ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 3.086m 5.082ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 4.715m 10.886ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 1.609m 6.289ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 6.529m 13.834ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 2.202m 3.536ms 25 25 100.00
usbdev_max_usb_traffic 2.162m 3.283ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 1.771m 7.070ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 3.603m 13.677ms 49 50 98.00
V2 data_toggle_restore usbdev_data_toggle_restore 6.760s 1.304ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 2.220s 432.753us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 4.330s 413.626us 50 50 100.00
V2 usbdev_tx_rx_disruption usbdev_tx_rx_disruption 49.319s 490 500 98.00
V2 intr_test usbdev_intr_test 1.150s 113.261us 50 50 100.00
V2 alert_test usbdev_alert_test 1.260s 101.311us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 5.100s 336.706us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 5.100s 336.706us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.190s 143.497us 5 5 100.00
usbdev_csr_rw 1.390s 121.162us 20 20 100.00
usbdev_csr_aliasing 3.590s 112.467us 5 5 100.00
usbdev_same_csr_outstanding 2.910s 391.771us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.190s 143.497us 5 5 100.00
usbdev_csr_rw 1.390s 121.162us 20 20 100.00
usbdev_csr_aliasing 3.590s 112.467us 5 5 100.00
usbdev_same_csr_outstanding 2.910s 391.771us 20 20 100.00
V2 TOTAL 3583 3599 99.56
V2S tl_intg_err usbdev_sec_cm 3.170s 885.904us 5 5 100.00
usbdev_tl_intg_err 5.890s 1.318ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.890s 1.318ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 3.268m 5.107ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 1.060s 50.966us 0 10 0.00
usbdev_stress_all 0.880s 0 50 0.00
TOTAL 3724 3800 98.00

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 85 85 82 96.47
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.82 98.16 96.01 97.44 96.61 98.38 98.17 92.94

Failure Buckets

Past Results